VISHAY SI4830ADY-T1-E3

Si4830ADY
Vishay Siliconix
Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode
FEATURES
PRODUCT SUMMARY
VDS (V)
30
RDS(on) (Ω)
ID (A)
0.022 at VGS = 10 V
7.5
0.030 at VGS = 4.5 V
6.5
SCHOTTKY PRODUCT SUMMARY
VDS (V)
VSD (V)
Diode Forward Voltage
IF (A)
30
0.50 at 1 A
2.0
• Halogen-free According to IEC 61249-2-21
Definition
• LITTLE FOOT® Plus Schottky
• Si4830DY Pin Compatible
• PWM Optimized
• 100 % Rg Tested
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Asymmetrical Buck-Boost DC/DC Converter
D1
D2
SO-8
S1/D2
1
8
D1
G1
2
7
D1
S2
3
6
S1/D2
G2
4
5
S1/D2
Schottky Diode
G1
G2
Top View
Ordering Information: Si4830ADY-T1-E3 (Lead (Pb)-free)
Si4830ADY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
S2
N-Channel MOSFET
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Symbol
VDS
VGS
Continuous Drain Current (TJ = 150 °C)a
TA = 25 °C
TA = 70 °C
7.5
6.0
ID
IDM
IS
Pulsed Drain Current
Continuous Source Current (Diode Conduction)a
TA = 25 °C
TA = 70 °C
Maximum Power Dissipationa
10 s
1.7
2.0
1.3
PD
TJ, Tstg
Operating Junction and Storage Temperature Range
Steady State
30
± 20
5.7
4.6
30
0.9
1.1
0.7
- 55 to 150
Unit
V
A
W
°C
THERMAL RESISTANCE RATINGS
MOSFET
Parameter
Symbol
a
Maximum Junction-to-Ambient
Maximum Junction-to-Foot (Drain)
t ≤ 10 s
Steady State
Steady State
RthJA
RthJF
Typ.
52
93
35
Max.
62.5
110
40
SCHOTTKY
Typ.
Max.
53
62.5
93
110
35
40
Unit
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
Document Number: 72021
S09-0868-Rev. G, 18-May-09
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1
Si4830ADY
Vishay Siliconix
MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
VGS(th)
VDS = VGS, ID = 250 µA
IGSS
VDS = 0 V, VGS = ± 20 V
VDS = 30 V, VGS = 0 V
Zero Gate Voltage Drain Current
IDSS
VDS = 30 V, VGS = 0 V, TJ = 85 °C
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb
Diode Forward Voltageb
ID(on)
RDS(on)
gfs
VSD
Dynamica
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off DelayTime
1.4
1
Ch-2
100
Ch-1
15
Ch-2
VGS = 4.5 V, ID = - 6.5 A
A
0.017
0.022
0.024
0.030
VDS = 15 V, ID = 7.5 A
19
0.75
1.2
Ch-2
0.47
0.5
7
11
VDS = 15 V, VGS = 4.5 V, ID = 7.5 A
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
Ω
S
Ch-1
2.9
V
nC
2.5
Rg
tr
µA
2000
20
0.5
1.5
2.4
9
15
td(on)
td(off)
V
nA
Ch-1
VDS = 5 V, VGS = 10 V
VGS = 10 V, ID = 7.5 A
IS= 1 A, VGS = 0 V
3.0
± 100
VDD = 15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
IF = 1.7 A, dI/dt = 100 µs
10
17
19
30
9
15
Ch-1
35
55
Ch-2
32
55
Ω
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
SCHOTTKY SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Forward Voltage Drop
Maximum Reverse Leakage Current
Junction Capacitance
Symbol
VF
Irm
CT
Test Conditions
Min.
Typ.
Max.
IF = 1.0 A
0.47
0.50
IF = 1.0 A, TJ = 125 °C
0.36
0.42
VR = 30 V
0.004
0.100
VR = 30 V, TJ = 100 °C
0.7
10
VR = - 30 V, TJ = 125 °C
3.0
20
VR = 10 V
50
Unit
V
mA
pF
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 72021
S09-0868-Rev. G, 18-May-09
Si4830ADY
Vishay Siliconix
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
30
30
VGS = 10 V thru 5 V
4V
25
I D - Drain Current (A)
I D - Drain Current (A)
25
20
15
10
20
15
10
TC = 125 °C
5
5
25 °C
3V
- 55 °C
0
0
0
2
4
6
8
10
0
1
VDS - Drain-to-Source Voltage (V)
Output Characteristics
4
5
1200
Ciss
960
C - Capacitance (pF)
0.030
VGS = 4.5 V
0.020
VGS = 10 V
720
480
Coss
0.010
240
0.000
Crss
0
0
5
10
15
20
25
30
0
5
ID - Drain Current (A)
10
15
20
25
30
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
10
1.8
VDS = 15 V
ID = 7.5 A
1.6
8
6
4
2
VGS = 10 V
I D = 7.5 A
1.4
(Normalized)
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
3
Transfer Characteristics
0.040
R DS(on) - On-Resistance (Ω)
2
VGS - Gate-to-Source Voltage (V)
1.2
1.0
0.8
0
0
3
6
9
12
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 72021
S09-0868-Rev. G, 18-May-09
15
0.6
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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Si4830ADY
Vishay Siliconix
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
0.06
0.05
R DS(on) - On-Resist ance (Ω)
I S - Source Current (A)
10
TJ = 150 °C
1
TJ = 25 °C
0.04
ID = 7.5 A
0.03
0.02
0.01
0.1
0.0
0.00
0.2
0.4
0.6
0.8
1.0
0
1.2
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
100
0.2
80
0.0
60
Power (W)
V GS(th) Variance (V)
ID = 250 µA
- 0.2
40
- 0.4
20
- 0.6
- 0.8
- 50
- 25
0
25
50
75
100
125
0
10-3
150
10-2
10-1
1
10
Time (s)
TJ - Temperature (°C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
Limited by RDS(on)*
1 ms
ID - Drain Current (A)
10
10 ms
1
100 ms
0.1
1s
10 s
TC = 25 °C
Single Pulse
DC
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VDS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Foot
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Document Number: 72021
S09-0868-Rev. G, 18-May-09
Si4830ADY
Vishay Siliconix
MOSFET TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 93 °C/W
3. TJM − TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 72021
S09-0868-Rev. G, 18-May-09
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Si4830ADY
Vishay Siliconix
SCHOTTKY TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
20
10
I F - Forward Current (A)
IR - Reverse Current (mA)
TJ = 150 °C
1
30 V
0.1
24 V
0.01
TJ = 25 °C
0.001
1
0.0
0.0001
0
25
50
75
100
125
150
0.3
0.6
0.9
1.2
1.5
VF - Forward Voltage Drop (V)
TJ - Temperature (°C)
Forward Voltage Drop
Reverse Current vs. Junction Temperature
200
C - Capacitance (pF)
160
120
80
Coss
40
0
0
6
12
18
24
30
VDS - Drain-to-Source Voltage (V)
Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72021.
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Document Number: 72021
S09-0868-Rev. G, 18-May-09
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72606
Revision: 21-Jan-08
Legal Disclaimer Notice
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000