STMICROELECTRONICS STV0299B

STV0299B

QPSK/BPSK LINK IC
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MULTISTANDARD
QPSK
AND
BPSK
DEMODULATION
EASY IMPLEMENTATION WITH LOW COST
DIRECT CONVERSION TUNERS
EXTREMELY
LOW
BER
WHEN
CO-CHANNEL INTERFERENCE
WIDE CARRIER LOOP TRACKING RANGE TO
COMPENSATE FOR DISH FREQUENCY DRIFT
COMMON INTERFACE COMPLIANT
VERY LOW POWER CONSUMPTION
INTEGRATED DUAL 6-BIT ANALOG TO
DIGITAL CONVERTERS
DUAL DIGITAL AGC
DIGITAL NYQUIST ROOT FILTER WITH
ROLL-OFF OF 0.35 OR 0.20
DIGITAL CARRIER LOOP WITH LOCK
DETECTOR,
ON-CHIP
WIDE
RANGE
DEROTATOR
AND
TRACKING
LOOP
(TYP ± 45 MHz)
DIGITAL TIMING RECOVERY WITH LOCK
DETECTOR
CHANNEL BIT RATE UP TO 90 Mbps AND
SYMBOL
FREQUENCY
RATE
FROM
1 TO 50 MSYMBOLS
INNER DECODER:
- VITERBI
SOFT
DECODER
FOR
CONVOLUTIONAL CODES, M=7, RATE 1/2
- PUNCTURED CODES 1/2, 2/3, 3/4, 5/6, 6/7 AND 7/8
SYNCHROWORD EXTRACTION
CONVOLUTIVE DEINTERLEAVER
OUTER DECODER:
- REED-SOLOMON
DECODER
FOR
16 PARITY BYTES; CORRECTION OF UP
TO 8 BYTE ERRORS
- ENERGY DISPERSAL DESCRAMBLER
ON-CHIP FLEXIBLE CLOCK SYSTEMS TO
ALLOW USE OF EXTERNAL CLOCK
SIGNALS IN 4 MHz TO 30 MHz RANGE
EASY-TO-USE C/N ESTIMATOR WITH 2 TO
18 dB RANGE
I2C SERIAL BUS AND REPEATER
DVB COMMON INTERFACE COMPLIANT
PARALLEL OUTPUT FORMAT
PARALLEL AND SERIAL DATA OUTPUT
LNB SUPPLY CONTROL WITH STANDARD I/O,
22 KHz TONE AND DISEQCTM MODULATOR
WITH TTL OUTPUT
CMOS TECHNOLOGY: 2.5 V OPERATION;
JEDEC (EIA/JESD8-5)
May 2000
TQFP64 (10 x 10 x 1.4 mm)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV0299B (No Slug)
APPLICATIONS
■ DIGITAL
SATELLITE
SET-TOP BOXES
RECEIVER
AND
DESCRIPTION
The STV0299 Satellite Receiver with FEC is a
CMOS single-chip multistandard demodulator for
digital satellite broadcasting. It consists of two A/D
converters for I-input and Q-input, a multistandard
QPSK and BPSK demodulator, and a forward
error correction (FEC) unit having both an inner
(Viterbi) and outer (Reed-Solomon) decoder.
The FEC unit is compliant with the DVB-S and
DSSTM specifications. Processing is fully digital.
It integrates a derotator before the Nyquist root
filter, allowing a wide range of offset tracking.
The high sampling rate facilitates the
implementation of low-cost, direct conversion
tuners.
A variety of configurations and behaviours can be
selected through a bank of control/configuration
registers via an I2C. The chip outputs MPEG
Transport Streams and interfaces seamlessly to
the Packet Demultiplexers embedded in ST’s
ST20-TPx or STi55xx. High sampling frequency
(up to 90MHz) considerably reduces the cost of
LPF of direct conversion tuners.
The multistandard capability associated with a
broad range of input frequency operations makes
it easy-to-use. Its low power consumption, small
package and optional serial output interface
makes it perfect for embedding into a tuner.
1/36
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STV0299B
TABLE OF CONTENTS
Page
1 PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pinout Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 SYSTEM CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Front End Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.1 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.2 Write Operation (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.3 Read Operation (Normal Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.4 I2C Interface in Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.5 Specific Concerns about SCL Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.6 Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.7 Sampling Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.8 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.9 Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.10 I2C Bus Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.11 General Purpose Σ∆ DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.12 DiSEqC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.13 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.1 I and Q Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.2 Main AGC (or AGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.3 Nyquist Root and Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.4 Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.5 Signal AGC (or AGC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.1 Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.2 Loop Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.3 Timing Lock Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Carrier Recovery and Derotator Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.1 Loop Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.2 Carrier Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.3 Derotator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.4 Carrier Frequency Offset Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Noise Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.1 FEC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.2 Viterbi Decoder and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.4 Error Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.5 Convolutional Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.6 Reed-Solomon Decoder and Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.7 Parallel Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.8 Serial Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 REGISTER LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/36
STV0299B
TABLE OF CONTENTS (continued)
6.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 I2C Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 APPLICATION BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
29
29
31
32
33
35
3/36
STV0299B
1
PIN INFORMATION
1.1 Pin Connections
62
61
60
59
58
57
56
55
54
53
52
51
50
VSSA
IP
IN
VSSA
QN
QP
VDDA
VTOP
VSSA
DIRCLK-DIS
SCLT
SDAT
63
TEST
64
TEST
VDD
Pinout for 64-pin TQFP (10x10 mm)
VSS
Figure 1:
49
CLK_IN/XTAL_IN
1
48
VBOT
XTAL_OUT
2
47
VDDA
VSSA
3
46
TEST
VDDA
4
45
TEST
AUX_CLK
5
44
TEST
VSS
6
43
TEST
VDD
7
42
STDBY
VSS
8
41
VDD
AGC
9
40
DAC
VDD
10
39
VSS
VSS
11
38
IP0
SDA
12
37
TEST
VDD_3.3 V
13
36
D0
SCL
14
35
D1
RESET
15
34
D2
33
D3
4/36
28
29
30
31
32
VDD
D4
VSS
27
D5
26
D6
25
VSS
24
SERIAL DATA/D7
23
VDD_3.3 V
22
CLK_OUT
21
VSS
20
STR_OUT
19
ERROR
18
LOCK/OP2
OP0
17
D/P
16
OP1
F22/DiSEqC
STV0299B
1
PIN INFORMATION (continued)
1.2 Pinout Description
Pin Number
I/O1
Name
Description
SIGNAL INPUTS
50, 51
IP, IN
I
Analog in Phase Component
53, 54
QN, QP
I
Analog in Quadrature Component
FRONT END CONTROLS
1
CLK_IN/XTAL IN
I
2
XTAL OUT
O
9
5
17-18
AGC
AUX_CLK
OP0, OP1
Crystal Input or CLK_IN
OD
Crystal Output
3
Control Signal to the Tuner
2
Programmable Output Port or Programmable Output Clock
2
Programmable Output Ports
2
Carrier Found or Data Found or Output Port
O
O
19
LOCK/OP2
O
38
IP0
I
D[7:0]
O2
Output Data; D7 is DATA_OUT in Serial Mode
2
Output Byte Clock; or Bit Clock in Serial Mode
2
Output 1st byte Signal (synchro byte clock)
2
Data/Parity Signal
2
Output Error Signal. Set in case of uncorrectible packet.
Input Port
SIGNAL OUPUTS
26-28-29-31, 33 to 36
24
22
21
20
CLK_OUT
STR_OUT
D/P
ERROR
O
O
O
O
I2C INTERFACE
I3
Serial Clock (I2C bus)
14
SCL
12
SDA
I/OD3 Serial Data (I2C bus)
59
SCLT
OD3
OTHERS
Note:
3
Tuner Serial Clock (repeator) or Output Port
Tuner Serial Data (repeator) or Input/Output Port
60
SDAT
I/OD
37-43-44-45-46-61-62
TEST
I
Reserved for manufacturing tests; must be tied to VSS
58
DIRCLK_DIS
I
Sets the DIRCLK function at power on
3, 49, 52, 57
VSSA
S
Analog Ground
4, 47, 55
VDDA
S
Analog 2.5 V Supply
56
VTOP
S
ADC High Voltage Reference
48
VBOT
S
ADC Low Voltage Reference
6-8-11-23-27-32-39-64
VSS
S
Ground
13-25
VDD_3.3 V
S
3.3 V Supply
7-10-30-41-63
VDD
S
2.5 V Supply
15
RESET
I
Reset, active at low level
42
STDBY
I
Sets STDBY at power on
16
F22/DiSEqC
O2
DiSEqC modulation, 22 kHz Tone, Programmable
Output Port
40
DAC
O2
Programmable Digital to Analog Converter Output
1
2
3
The following abbreviations are used: I - Input; O - Output; OD - Open drain output.
3.3 V output levels.
5 V tolerant
5/36
STV0299B
2
BLOCK DIAGRAM
Nyquist &
Interpolation
Filter
Timing
Recovery
AGC2
Timing
DCO
Derotator
Carrier Lock
Indicator
AGC
AGC1
VDDA
Offset
Comp.
VTOP
Timing
Lock
Indicator
C/N
Indicator
IN/IP
ADCs
QN/QP
VBOT
Error
Monitoring
VSSA
CLK_IN/XTAL_IN
AUX_CLK
Viterbi Decoder
Clock
Generator
Deinterleaver
XTAL_OUT
F22/DiSEqC
SCL
SDA
22 kHz
Tone
DiSEqC
Interface
Reed-Solomon
Decoder
D/P
I2C
Interface
General
Purpose
Functions
ERROR
Energy
Descrambler
STR_OUT
CLK_OUT
SDAT
SCLT
DAC IP0 OP0[2:0]
3 SYSTEM CHARACTERISTICS
Performances
The following given parameters are for indication
purposes only.
Carrier Loop Tracking Range:
• ±fM_CLK/2
Carrier Loop Capture Range (C/N>=4 dB):
• up to ± 5% fs in less than 100 Ksymbols
• up to ± 2% fs in less than 10 Ksymbols
C/N Threshold (lowest C/N at which capture is
possible) = 1 dB.
D[7:0] VDD_3.3V VDD
Timing Loop Capture Range (C/N>=2 dB):
• up to ±250 ppm in less than 100 Ksymbols
• conventions used for the above characteristics
are:
fsampling = fm_clk = fmaster_clock
fs = fsymbol
Eb
No
C/N = Carrier/Noise = -------- x2 xPR
PR = Puncture Rate
6/36
VSS
STV0299B
4
FUNCTIONAL DESCRIPTION
4.1.2 Write Operation (Normal Mode)
The byte sequence is as follows:
1 The first byte gives the device address plus the
direction bit (R/W = 0).
2 The second byte contains the internal address
of the first register to be accessed.
3 The next byte is written in the internal register.
Following bytes (if any) are written in
successive internal registers.
4 The transfer lasts until stop conditions are
encountered.
5 The STV0299B acknowledges every byte
transfer.
The STV0299B is a multistandard demodulator
and error correction decoder IC for the reception
of QPSK and BPSK modulated signals. It is
intended for use in digital satellite television
applications. The IC can accept two standards of
QPSK modulated signals (DVB and DSS) as well
as BPSK modulated signals over a wide symbol
frequency range (from 1 to 50 Msymbols/s). The
signals are digitized via an integrated dual 6-bit
analog to digital converter, and interpolated and
digitally filtered by a Nyquist root filter (with a
settable roll-off value of either 0.35 or 0.20).
There are two built-in digital Automatic Gain
Controls (AGCs). The first AGC allows the tuner
gain to be controlled by the pulse density
modulated output. The second AGC performs
power optimization of the digital signal bandwidth
(internal to the STV0299B). The digital signal then
passes through the digital carrier loop fitted with
an on-chip derotator and tracking loop, lock
detector, and digital timing recovery.
Forward error correction is integrated by way of an
inner Viterbi soft decoder, and an outer
Reed-Solomon decoder.
4.1.3 Read Operation (Normal Mode)
The address of the first register to read is
programmed in a write operation without data, and
terminated by the stop condition. Then, another
start is followed by the device address and R/
W = 1. All following bytes are now data to be read
at successive positions starting from the initial
address. Figure 2 shows the I2C Normal Mode
Write and Read Registers.
4.1.4 I2C Interface in Standby Mode
Only three registers can be addressed while in
standby mode: RCR (address 01 Hex), MCR
(address 02 Hex) and ACR (address 03 Hex).
These three registers can be either read or written
to (refer to Figure 3).
4.1 Front End Interfaces
4.1.1 I2C Interface
The standard I2C protocol is used whereby the
first byte is Hex D0 for a write operation, or Hex
D1 for a read operation. The I2C interface
operates differently depending on whether it is in
normal or standby mode.
Figure 2:
Only one register may be read or written to per
sequence (no increment). While in standby mode,
the Serial Clock (SCL) frequency must be lower than
one tenth of the CLK_IN frequency (fCLK_IN / 10).
I2C Read and Write Operations in Normal Mode
Write registers 0 to 3 with AA, BB, CC, DD
Start
Device
Address,
Write D0
ACK
Register
Address
00
ACK
Data
AA
ACK
Data
BB
ACK
Data
CC
ACK
Data
DD
ACK
Stop
Read registers 2 and 3
Start
Device Address, Write D0
ACK
Register Address 02
ACK
Start
Device Address,
Read D1
ACK
Data Read CC
ACK
Figure 3:
Stop
ACK
Data Read DD
Stop
I2C Read and Write Operations in Standby Mode
Write operation
Start
Device Address, Write D0
ACK
Register Address 01, 02 or 03
ACK
Data
ACK
Stop
Read operation
Start
Device Address
, Read D0
ACK
Register Address
ACK
Stop
Start
Device Address,
Read D1
ACK
Reader Data
ACK (or no
ACK1)
Stop
Note: 1 ACK is not absolutely necessary after Data
7/36
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.1.5
Specific Concerns about SCL
Frequency
For reliable operation in Normal Mode, the SCL
frequency must be lower than 1/40 of the Master
Clock (M_CLK) frequency. Consequently, care
should be taken to observe the following:
1 Before returning to Normal Mode from Standby
Mode, the M_CLK frequency must be selected
such that fM_CLK ≥ 40 fSCL
2 After Power-on reset signal, the STV0299B
operates in Normal Mode. There are two possible cases:
- DIRCLK-DIS
(pin
58)
is
grounded.
M_CLK = CLK_IN, the fSCL frequency of the
I2C bus must satisfy:
fSCL ≤ CLK_IN
--------------------40
.
- DIRCLK-DIS (pin 58) is tied to VDD
---------- ⋅ fCLK_IN), and the fSCL
(where f M_CLK = 100
16
frequency of the I2C bus must satisfy:
100
f SCL ≤ ------------------- ⋅ CLK_IN and fSCL ≤ 400 kHz.
16 × 40
For example, this second operating mode is
required when the application features both a
4 MHz XTAL and a 400 kHz I2C bus.
4.1.6 Identification Register
The Identification Register (at address Hex 00)
gives the release number of the circuit.
The content of this register at reset is presently A1
(same as STV0299).
4.1.7 Sampling Frequency
The STV0299B converts the analog inputs into
digital 6-bit I and Q flows. The sampling frequency
is fM_CLK which is derived from an external
reference described in Section 4.1.8 ‘Clock
Generation’. The maximum value of fM_CLK is 90
MHz.
8/36
The sampling causes the repetition of the input
spectrum at each integer multiple of fM_CLK. One
has to ensure that no frequency component is
folded in the useful signal bandwidth of fS(1+α)/2
where fS is the symbol frequency, and α is the
roll-off value.
4.1.8 Clock Generation
An integrated VCO (optimised to run in the range
of 300 to 400 MHz) is locked to a reference
frequency provided by a crystal oscillator by the
following relation:
M+1
f V CO = f ref ⋅ 4 ⋅ ( M + 1 ) = f X TAL ⋅ 4 ⋅ -------------K+1
The VCO’s loop filter is optimized for a reference
frequency between 4 and 8 MHz.
The VCO generates the following by division:
• The Master Clock (M_CLK)
• An auxiliary clock (AUX_CLK) which may either
be in the MHz range or in the 25 Hz to 1500 Hz
range for some specific LNB control (for
example, 60 Hz).
• A lower frequency, F22, typically 22 KHz,
needed for LNB control or DiSEqCTM control.
When DIRCLK_CTRL = 1, the crystal signal is
routed directly to M_CLK; the VCO may still be
used to generate AUX_CK and/or the F22 (used
by the DiSEqCTM interface).
If the internal VCO is not used by any of the
dividers, it may be stopped in order to decrease
the power consumption and/or radiation
emissions. The only guaranteed function in
standby mode is the I2C Write/Read function of
the three clock control registers.
There are restrictions on the high and low level
durations, and on the crystal (or external clock)
frequency when the direct clock is used.
These restrictions are explained in Section 4.1.5
Specific Concerns about SCL Frequency.
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
Figure 4:
Clock Signal Generation
LPF
Reg 01[7:6]
÷(K+1)
OSC
XTAL OUT
Reg 01[4:0]
VCO
1/4
VCO
ON/OFF
I2C
1/6
PHASE
COMPARATOR
÷(M+1)
XTAL IN/CLK-IN
Reg 02[2:0]
1
÷P(Note 1)
0
VCO ON/OFF
DIRCLK-CTRL
Note 2
M_CLK
STDBY
(I2C bit)
STDBY
Note 2
I2C
2
DIRCLK-DIS
DIRCLK (I C bit)
1/16
1/2
÷R
TO SERIAL
SHIFTER
DiSEqC/tone
burst modulator
Reg 04
F22/
DiSEqCTM
1/0
Reg 08[2:0]
PRESCALER
1/0
PROGRAMABLE
DIVIDER
AUX_CLK
1/2
Reg 03
Note:
1
2
Table 1:
Refer to the Register List P[2:0] in table 1
At the rising edge of RESET signal (pin 15) the corresponding bit of the I2C bus register is forced to the status of pin STDBY or
to DIRCLK-DIS.
Divider Programming
K(1:0) in register
fREF = fXTAL divided by:
00
1
01
2
10
3
11
4
M(4:0) in register
P(2:0) in register
fM_CLK = fVCO
divided by P:
000
4
001
6
fVCO = fREF
multiplied by:
00000
4
00001
8
00010
12
00011
16
...
...
11111
128
Table 2:
010
8
011
12
100
16
101
24
110
32
111
48
Summary of FM_CLK
M+1
f V CO = fX TAL × 4 ⋅ -------------K+1
f V CO
f M_CLK = ----------P
DIRCLK_CTRL = 0
f M_CLK = f CLK_IN
DIRCLK_CTRL =1
fM_CLK = 0
STDBY = 1
9/36
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.1.9 Clock Registers
The Reference Clock, Master Clock, Auxiliary
Clock and F22 Frequency Registers are in
Addresses 01, 02, 03 and 04.
4.1.10 I2C Bus Repeater
In low symbol rate applications, signal pollution
generated by the SDA/SCL lines of the I2C bus
may dramatically worsen tuner phase noise. In
order to avoid this problem, the STV0299B offers
an I2C bus repeater so that the SDAT and SCLT
are active only when necessary and muted once
the tuner frequency has settled.
Both SDAT and SCLT pins are set high at reset.
When the microprocessor writes a 1 into register
bit I2CT, the next I2C message on SDA and SCL is
repeated on the SDAT and SCLT pins respectively,
until stop conditions are detected.
To write to the tuner, the external microprocessor
must, for each tuner message, perform the
following:
• Program 1 in I2CT.
• Send the message to the tuner.
Any size of byte transfers are allowed, regardless
of the address, until the stop conditions are
detected. Transfers are fully bi-directional.
The I2CT bit is automatically reset at the stop
condition. If not used for the I2C repeater, both
SDAT and SCLT outputs may be used as general
purpose output ports.
SDAT status may be read on the DiSEqC register.
Configuration is controlled by the I2C repeater
register in Address 0Ah.
In the first version of the STV0299, operation of
the repeater was very fast, and often too fast
versus the rise time of the SDAT and SCLT
signals. In the STV0299B, a programmable delay
is implemented to accept a wide range of rise
times on SDAT and SCLT. The delay is
programmed with Reg.05 [5:4]. In practice,
operation of the repeater is ensured in the
following case:
• Reg.05 [5:4]: xx
• fM_CLK ≤ 90 MHz
• RC≤ 250ns (R: pull-up resistor, C:
capacitance on either SDAT or SCLT).
total
4.1.11 General Purpose Σ∆ DAC
A DAC is available in order to control external
analog devices. It is built as a sigma-delta
first-order loop, and has 12-bit resolution-it only
requires an external low-pass filter (simple RC
filter). The clock frequency is derived from the
main clock by programmable division. The
converter is controlled by two registers-one for
10/36
clock divider control and 4 MSBs, and the other for
the 8 LSBs.
If the DAC is not needed, the DAC output may be
used as an output port. The DAC Registers are in
Addresses 06 and 07.
4.1.12 DiSEqC Interface
This interface allows for the simplification of real
time processing of the dialog from microprocessor
to LNB. It includes a FIFO that is filled by the
microprocessor via the I2C bus, and then
transmitted by modulating the F22 clock adjusted
beforehand to 22 kHz.
Two control signals are available on the I2C bus:
FE (FIFO empty) and FF (FIFO full).
A typical byte transfer loop, as seen from the
microprocessor, may be the following:
While (there is data to transfer)
1 Read the control signals
2 If FF=1, go to 1
3 Write byte to transfer in the FIFO
Note, for the above transfer loop, the following:
• At the beginning, the FIFO is empty (FE=1,
FF=0). This is the idle state.
• As soon as a byte is written in the FIFO, the
transfer will begin.
• After the last transmitted byte, the interface will
go into the idle state.
Modulation
The output is a gated 22 kHz square signal.
• In the idle state, modulation is permanently
inactive.
• In byte transmission, the byte is sent (MSB
first) and is followed by an odd parity bit.
A byte transmission is therefore a serial 9-bit
transmission with an odd number of “1’s”.
Each bit lasts 33 periods of F22 and the
transmission is PWM-modulated.
- Transmission of “0’s”. There are two
submodes controlled by PortCtrl(2):
a) PortCtrl2 = 1: Modulation is active during
22 pulses, then inactive during 11 pulses
(2/3 PWM).
b) PortCtrl2 = 0: Modulation is active during
33 pulses (3/3 PWM).
- Transmission of “1’s”. During transmission
of “1’s”, modulation is active during 11 pulses,
then inactive during 22 pulses (1/3 PWM).
This is compatible with “Tone Burst” in older LNB
protocols.
For the “Modulated Tone Burst”, only one byte
(with value Hex FF) is written in the FIFO.
The parity bit is 1, and as a result, the output
signal is 9 bursts of 0.5 ms, separated by
8 intervals of 1 ms.
STV0299B
For the “Unmodulated Tone Burst” Port CTRL 2 is
set to 0 and, only one byte, of value 00h is sent.
The parity bit is still 1, and as a result, the signal is
a continuous train of 12.5 ms. When the
modulation is active, the DiSEqC output is driven
Figure 5:
alternatively to VDD and VSS levels. The DiSEqC
and Lock Control, DiSEqC FIFO and DiSEqC
Status Registers are in Addresses 08, 09 and
0Ah.
Schematic showing Bit Transmission
Idle
11 Periods
11 Periods
11 Periods
Next bit
Transmission of 1’s
Transmission of 0’s:
a) PortCtrl2 = 1
b) PortCtrl2 = 0
Table 3:
PortCtrl (1:0)
PortCtrl (2)
FIFO
Output
00
X
empty
0
01
X
empty
1
10
0
DATA = 00
Unmodulated tone burst
1
DATA = FFor00
Modulated tone burst
1
Note 1
DiSEqC signal
X
XX
Continuous tone
11
Note:
1
2
Byte to transfer in DiSEqC mode.
In mode PortCtrl (1:0)=10, the F22/DiSEqC pin returns to High -2 mode once the transmission is completed.
4.1.13 Standby Mode
A low power consumption mode (standby mode)
can be implemented (in this mode, fM_CLK = 0). In
standby mode, the I2C decoder still operates, but
with some restrictions (see Sections 4.1.4 and
4.1.5).
Standby mode can be initiated or stopped by I2C
bus commands as described in MCR Register 02.
At power-on, the circuit starts to operate in
standby mode when the STDBY pin (pin 42) is
tied to VDD. This guarantees low power
consumption for the stand-alone modules
(PCMCIA size front-end modules) before any
command is initiated. After the power-on
sequence, the standby mode is entirely controlled
via MCR Register (02).
11/36
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.2 Signal Processing
4.2.1 I and Q Inputs
The ADC features differential inputs, but in most
applications I & Q signals are single-ended. In
such applications, I and Q signals from the tuner
are fed to the respective IP and QP inputs through
a capacitor. The IN and QN pins are DC biased,
typically to VBOT.The internal biasing of the ADC is
done on the circuit at the mid-voltage between
VTOP and VBOT.
The Input/Output Configuration Register is
described in Address 0Ch.
4.2.2 Main AGC (or AGC1)
The modulus of the I/Q input is compared to a
programmable threshold, m1, and the difference
is integrated. This signal is then converted into a
pulse density modulation signal to drive the AGC
output. It should be filtered by a simple analog
filter to control the gain command of any amplifier
before the A to D converter.
The output converter operates at fM_CLK/8 in order
to decrease the radiated noise and to simplify the
filter design. The output is a 5 V tolerant open
drain stage.
The reset value of the coefficient allows an initial
settling time of less than 100k master clock
periods.
The 8 integrator MSBs may be read or written at
any time by the microprocessor. When written, the
LSB’s are reset and the coefficient may be set to
zero by programming (in this case, the AGC is
reduced to a programmable 8-bit voltage
synthesizer).
The time constant of agc1 is estimated as
followed:
26 – β a gc1
T agc1 = 2
----------------------- × T M_CLK
m1
with m1 = AGC1 reference level.
The AGC1 Control, AGC1 Reference and AGC1
Integrator Registers are in Addresses 0D and 0F.
4.2.3 Nyquist Root and Interpolation Filters
Two roll off values are available: 0.35 and 0.20.
Refer to the Input/Output Configuration Register
in Address 0C.
4.2.4 Offset Cancellation
This device suppresses the residual DC
component on I and Q. The compensation may be
frozen to its last value by resetting the DC offset
12/36
compensation bit in the AGC Control Register in
Address 0D.
4.2.5 Signal AGC (or AGC2)
The rms value of I and Q is measured after the
Nyquist filter and compared to a programmable
value, m2, such as that of the main AGC.
The integrated error signal is applied to a
multiplier on each I and Q path.
The AGC2 Control Register is in Address 10.
Bits [7:5] give the AGC2 coefficient, which sets
beta_agc2, the gain of the integrator. Table 4
shows how beta_agc2 is programmed with AGC2
coefficient (which is related to the time constant of
the AGC).
Table 4:
AGC2 Coefficient
beta_agc2
0
0
1
1
2
4
3
16
4
64
5
256
6
N/A
7
N/A
If AGC2 Coefficient = 0, the gain remains
unchanged from its last value.
The time constant is independent of the symbol
frequency, however it does depend on the
modulus, m1, of the input signal, programmed in
AGC1, with the following approximate relation:
3
60 × 10 ⋅ T M_CLK
Tagc2 = -------------------------------------------m1 ⋅ beta_agc2
The AGC2 Integrator Registers (2 bytes - MSB
and LSB) are in Addresses 18 and 19. These
values may be read or written by the
microprocessor. When written, all the LSB’s
integrator bits are reset. This value is an image of
the signal power in the useful band. Compared
with the total power of the signal, the out-of-band
power may be computed (noise, or other channel).
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.3 Timing Recovery
4.3.1 Timing Control
The loop is parametrized by two coefficients:
alpha_tmg and beta_tmg. alpha_tmg can take
values from 0 to 4, and beta_tmg from 0 to 7
(Register 0E).
When the parameter is 0, the actual coefficient
value is zero. The 8 MSBs of the frequency
accumulator may be read or written at any time by
the I2C bus—when written, all LSBs are reset.
The Symbol Frequency Registers (MSB, Middle
Bits and LSB) are in Addresses 1F, 20 and 21.
These must be programmed with the expected
symbol frequency.
The units are:
f M_CLK
---------------20
2
Write mode is effective when writing the Middle Bit
Register. The MSB Register must be loaded
before the Middle Bit Register.
The value of the Timing Frequency Register, when
the system is locked, is an image of the frequency
offset. The unit is fS/219 (approx. 2 ppm). It should
be as close as possible to 0 (by adjusting symbol
frequency register value) in order to have a
symmetrical capture range. Reading it allows for
optimal trimming of the timing range (Register
1A).
The actual symbol frequency is:
fS
act
( f M_CLK ⋅ f s_reg ) + ( 2 ⋅ fs ⋅ T mg_reg )
= -------------------------------------------------------------------------------------20
2
where fs_reg is the content of the symbol frequency
register and Tmg_reg the content of the timing
frequency register.
4.3.2 Loop Equation
The timing loop may be considered as a second
order loop. The natural frequency and the
damping factor may be calculated using the
following formula:
–6
f n = 5.2 ⋅ 10 fS m2 ⋅ β
where, fS is the symbol frequency, m2 is the AGC2
reference level and β is programmed by the timing
register:
β = 2
beta_tmg
The damping factor is:
alpha_tmg
0.134 ⋅ m2 ⋅ 2
ξ = -------------------------------------------------------------beta_tmg
2
where m2 is the reference level of the AGC2
register.
Table 5 shows the natural frequency in DVB, with
nominal reference level m2 = 20, for different
values of beta_tmg and alpha_tmg, without noise.
4.3.3 Timing Lock Indicator
The timing lock indicator reports a value
dependent upon the signal-to-noise ratio and on
the signal lock state.
With an AGC2 Reference level m2 = 20, if the
timing lock indicator is above 48, the timing is
locked; if it is above 42, this shows that a QPSK
signal is present, either locked with low C/N
(<3.6 dB) or unlocked with higher C/N; the
ambiguity may be solved by changing on purpose
the timing frequency of 1%; if it was locked before,
the indicator should be now under 42.
The indicator needs 30K symbols for stabilization
from unlock to lock after a frequency change.
The timing lock registers - the Timing Lock Setting
Register and the Timing Lock Indicator Register are in Addresses 11 and 17.
Table 5:
alpha_tmg
1
2
3
4
beta_tmg
Natural Frequency for
fS = 20 Mbaud
1
0.66 kHz
0.85
1.70
3.38
6.77
2
0.93 kHz
0.60
1.20
2.40
4.80
3
1.32 kHz
0.42
0.85
1.70
3.38
4
1.86 kHz
0.30
0.60
1.20
2.40
5
2.63 kHz
0.21
0.42
0.85
1.70
6
3.72 kHz
0.15
0.30
0.60
1.20
7
5.26 kHz
0.10
0.21
0.42
0.85
Damping Factor
13/36
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.4 Carrier Recovery and Derotator Loop
The tracking range of the derotator is ± fM_CLK/2
(± fsampling/2). The initial frequency search may
therefore be performed on several MHz ranges
without reprogramming the tuner.
Three phase detectors are selectable using
software:
• Phase detector algorithm 0: This algorithm
should only be used for BPSK reception.
• Phase detector algorithm 1: This algorithm is
used with QPSK reception, over a small range
of capture phases and with a channel noise
value over 4.5 dB.
• Phase detector algorithm 2: For QPSK
reception, it is used after locking, to minimize
the bit error rate in low channel noise
conditions. Algorithm 2 is recommended for
most applications.
The loop is controlled through α and β
parameters.
The carrier loop control registers (the Alpha
Carrier Register, the Beta Carrier Register and the
Carrier Frequency Register) are in Addresses 13,
14, 22 and 23.
4.4.1 Loop Parameters
Like the timing loop, the carrier loop is a
second-order system where two parameters, α
and β, may be programmed with alpha_car and
beta_car respectively.
The natural frequency (fn) is:
f n = 7 ⋅ 10
–6
fS
⋅ fM_CLK ( m2 ⋅ β ) ---------------fM_CLK
The damping factor is:
ξ = 22 ⋅ 10
–6
m2 f S
⋅ α --------- ---------------β f M_CLK
α = (2+a)⋅2b⋅214, with
where
b ≥ 1,
and
β = (4+2c+d)⋅2e, with e ≥ 1. m2 is the reference
level in the AGC2 register.
4.4.2 Carrier Lock Detector
The carrier lock detector provides an indicator
with a high value when the carrier is locked,
dependent on the channel noise. When the carrier
is not locked, the indicator value is low.
The indicator value is compared to a
programmable 8-bit threshold (Register 15h). The
14/36
result of this comparison (1 if greater than the
threshold, else 0 if not) is written as the Carrier
Found flag (CF), and may be read in the status
register. The CF signal may be permanently
routed on the output LOCK (see Register 08h).
The Lock Detector Threshold Register and Lock
Detector Value Register are in Addresses 15 and
1C.
4.4.3 Derotator Frequency
The derotator frequency can be either measured
(read operation) or forced (write operation).
Derot_freq
( freq )kHz = ------------------------------ ⋅ ( f M_CLK ) kHz
16
2
Derot_freq is a 16-bit signed value.
The Derot_freq Registers are Registers 22 and
23.
4.4.4 Carrier Frequency Offset Detector
The carrier recovery loop features a carrier
frequency offset detector and two phase
detectors. When the carrier frequency offset
detector is enabled, the central loop frequency is
modified proportionally to the carrier offset. The
gain and time constants of the detector are set by
CFD[6:4] and CFD[3:2] respectively. When the
carrier loop is about to “phase lock” with the
carrier, the frequency detector stops automatically
and the phase lock is ensured by the selected
phase detector. This switchover point is
determined by the threshold CFD [1:0].
For stability reasons, the gain CFD [6:4] should
not exceed the coefficient e[3:0] of Register
BCLC.
The carrier frequency offset detector is in Address
12.
4.5 Noise Indicator
The noise indicator may be used to facilitate the
antenna pointing or to give an idea of the RF
signal quality and of the front-end installation
(dish, LNB, cable, tuner or ADC).
A simple C/N estimator can be easily
implemented by comparing the current indications
with a primarily-recorded look-up table.
The time constant ranges from 4 k to 256 k
symbols. The 16 MSB of the result may be read by
the microprocessor (Registers 24 and 25).
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.6 Forward Error Correction
4.6.1 FEC Modes
Since the STV0299B is a multistandard decoder,
several combinations are possible, at different
levels:
• The demodulator may accept either QPSK or
BPSK signals - the only impact is on the carrier
algorithm choice (refer to Chapter 4.4).
The algorithm choice also affects the carrier
lock detector and the noise evaluation.
• There two primary options concerning the FEC
operation - between DVB, DSS and Reserved
Mode.
• There are two options concerning the FEC
feeding. The first is IQ flow, which is the usual
case in QPSK modes DVB or DSS. The second
mode is I-only flow, used for BPSK.
The FEC Mode Register is in Address 28.
In Modes DVB and DSS, data is fed to the Viterbi
decoder. Other parts of the decoding (such as the
Convolutional Deinterleaver) may be bypassed.
4.6.2 Viterbi Decoder and Synchronization
The convolutive codes are generated by the
polynomial Gx = 171 octets and Gy = 133 octets in
modes DVB or DSS.
The Viterbi decoder computes for each symbol
the metrics of the four possible paths, proportional
to the square of the Euclidian distance between
the received I and Q and the theoretical symbol
value.
The puncture rate and phase are estimated on the
error rate basis. Several rates are allowed and
may be enabled/disabled through register
programming:
• 1/2, 2/3, 3/4, 5/6, 7/8 in DVB.
• 1/2, 2/3, 3/4, 5/6 and 6/7 in DSS.
For each enabled rate, the current error rate is
compared to a programmable threshold. If it is
greater than this threshold, another phase (or
another rate) is tried until the right rate is obtained.
A programmable hysteresis is added to avoid
losing the phase during short term perturbation.
The rate may also be imposed by external
software, and the phase is incremented only upon
request by the microprocessor. The error rate may
be read at any time in order to use an algorithm
other than that implemented.
The Viterbi decoder produces an absolute
decoding. The decoder is controlled via several
Viterbi Threshold Registers (Registers 29, 2A, 2B,
2C and 2D). For each Viterbi Threshold Register,
bits 6 to 0 represent an error rate threshold - the
average number of errors occurring during 256-bit
periods. The maximum programmable value is
127/256 (higher error rates are of no practical
use).
The Puncture Rate and Synchro Register is in
Address 31.
The automatic rate research is only done through
the enabled rates (see the corresponding bit set in
the Puncture and synchro register). In DSS, the
puncture rate 6/7 replaces the puncture rate 7/8.
In DSS, it is recommended that you disable
puncture rates 3/4 and 5/6 in order to save time in
the synchronization process.
The VSEARCH Register is in Address 32.
VSEARCH bit 7 (A/M) and bit 6 (F) programs the
automatic/manual (or computer aided) search
mode as follows:
• If A/M =0 and F=0, automatic mode is set.
Successive enabled punctured rates are tried
with all possible phases, until the system is
locked and the block synchro found. This is the
default (reset) mode.
• If A/M=0 and F=1, the current puncture rate is
frozen. If no sync is found, the phase is
incremented, but not the rate number.
This mode allows shortening of the recovery
time in case of noisy conditions. The puncture
rate is not supposed to change in a given
channel.
In
a
typical
computer-aided
implementation, the research begins in
automatic mode. The microprocessor reads the
error rate or the PRF flag in order to detect the
capture of a signal, then it switches F to 1, until
a new channel is requested by the remote
control.
• If AM=1 manual mode is set. In this case, only
one puncture rate should be validated the system is forced to this rate, on the current
phase, ignoring the time-out register and the
error rate. In this mode, each 0 to 1 transition of
the bit F leads to a phase incrementation,
allowing full control of the operation by an
external microprocessor by choosing the lowest
error rate.
The reset values are A/M=0, and F=0 (automatic
search mode).
The VERROR Register (a read only register) is in
Address 26. The last value of the error rate may
be read at any time in the register. Unlike the VTH,
the possible range is from 0 to 255/256.
The VSTATUS Register (a read only register) is in
Address 1B.
15/36
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.6.3 Synchronization
In DVB, the packet length after inner decoding is
204. The sync word is the first byte of each
packet. Its value is Hex 47, but this value is
complemented every 8 packets. In DSS, the
packet length is 147 and the sync word is Hex 1D.
An Up/Down Sync counter counts whenever a
sync word is recognized with the correct timing,
and counts down during each missing sync word.
This counter is bounded by a programmable
maximum - when this value is reached, the LK bit
(“locked”) is set in the VSTATUS register. When
the event counter counts down to until 0, this flag
is reset.
4.6.5 Convolutional Deinterleaver
In DVB, the convolutional deinterleaver is 17 x 12.
The periodicity of 204 bytes per sync byte is
retained. In DSS, the convolutional deinterleaver
is 146 x 13, and there is also a periodicity of
147 bytes per sync byte. The deinterleaver may
be bypassed - for details, see Section 4.6.6
‘Reed-Solomon Decoder and Descrambler’.
4.6.4 Error Monitoring
A 16-bit counter, ERRCNT, allows the counting of
errors at different levels. ERRCNT is fed either by:
• the input QPSK bit errors (that are corrected by
the Viterbi decoder), or,
• the bit, or,
• the byte error (that are corrected by the
Reed-Solomon decoder), or,
• the packet error (not corrigible, leading to a
pulse at the ERROR output).
The content of ERRCNT may be transferred to the
read only registers ERRCNT_LOW (LSB) and
ERRCNT_HIGH (MSB).
Two functional modes are proposed, depending
on a control register bit:
1 Error Mode = 0. This is an error rate measure,
that tells the number of errors occurring within
a specified number of output bytes, NB. NB has
four possible values given in the Error Control
Register in Address 34. Every NB bytes, the
state of the error counter is transferred to a
16-bit register, then the error counter is reset.
The Error Count Registers in Addresses 1D
and 1E may be read by the microprocessor via
I2C bus. Two ways of reading may be used:
16-bit reading, starting with MSB, or 8-bit
reading (LSB only or MSB only).
2 Error Mode = 1. The error counter just counts
the error; the I2C register permanently copies
the content of the error counter. When the MSB
byte is read, the error counter is reset. In both
modes, the 16-bit counter is saturated to its
maximum value.
g ( x ) = ( x – ω ) ( x – ω ) (… ) ( x – ω )
16/36
4.6.6
Reed-Solomon Decoder and
Descrambler
The input blocks are 204-byte long with 16 parity
bytes in DVB. The synchro byte is the first byte of
the block. Up to 8 byte errors may be fixed.
The Code Generator polynomial is:
0
1
15
over the Galois Field generated by:
8
4
3
2
x + x + x + x + 1= 0
Energy dispersal descrambler and output energy
dispersal descrambler generator:
x
15
+x
14
+1
The polynomial is initialized every eight blocks
with the sequence 100101010000000.
The synchro words are unscrambled and the
scrambler is reset every 8 packets.
The output interface may be forced into high
impedance mode by setting bit 0 of Address 28.
Doing this affects the D[7:0], CLK_OUT,
STR_OUT, D/P and ERROR pins. This also allows
for board testing, and “OR” wiring several link
circuits (for example, cable links). The output
stream is either parallel (byte stream) or serial (bit
stream) depending on bit 1 of Address 28.
The outputs are controlled by the RS Control
Register in Address 33.
4.6.7 Parallel Output Interface
A schematic diagram of the parallel output
interface is shown in Figure 7. The parallel output
format is compliant with the DVB common
interface protocol.
When the SYNC is not found (LK = 0 in the status
register), D/P (corresponding to the MiVAL signal
of the DVB common interface standard) remains
at a low level.
CLK_OUT has a duty cycle between 40 and 60%.
STV0299B
4
FUNCTIONAL DESCRIPTION (continued)
4.6.8 Serial Output Interface
The serial output interface is shown in Figure 6.
The serial bit stream is available on D7,
where MSB is first to reconstruct the original
order. If RS0 = 0, then the parity bits are output
(Register 33). If RS0 = 1, the data is null during
the parity time slots.
STR_OUT is only high during the first bit of each
packet, instead of during the first byte in parallel
mode.
ERROR has the same function as in parallel
mode.
CLK_OUT is the serial bit clock; it is derived from
either the master clock, M_CLK, (if SerClk = 0 in
Registers 02 and B3), or from the internal VCO
frequency divided by 6, (if SerClk = 1), by skipping
some pulses to accommodate the frequency
difference.
Figure 6:
All of the outputs are synchronous of the same
master clock edge.
D0, STR_OUT, D/P and ERROR may be properly
sampled externally by the rising edge of
CLK_OUT, if RS1 = 0, or by the falling edge of
CLK_OUT if RS1 = 1. This clock runs
continuously, even during parity data, whatever
the value of RS0.
The first bit detected in a valid packet may be
decoded if it is found on the appropriate edge of
CLK_OUT, where STR_OUT = 1, ERROR = 0,
D/P = 1. The following bits only require the
assertion of D/P (while D/P = 1,...).
Outputs D0 to D6 remain at low level in serial
mode.
Serial Output Interface
STR_OUT
1/fM-CLK or 6/fVCO
CLK_OUT
RS1 = 1
RS1 = 0
Data
Parity
D/P
First bit of the packet
RS0 = 0
Useful Data
Parity
D7
RS0 = 1
RS0 = 0
ERROR
RS0 = 1
1 Packet
Figure 7:
Parallel Output Interface
No Error
Data
Uncorrectible Packet
No Error
Parity
RS0 = 0
RS1 = 0
RS0 = 1
CLK_OUT
RS0 = 0
RS1 = 1
RS0 = 1
D/P
STR_OUT
ERROR
RS0 = 0
RS0 = 1
17/36
STV0299B
Table 6:
Functional I2C Register Map
Name
ID
RCR *
MCR *
ACR *
F22FR
12CRPT
DACR1
DACR2
DiSEqC
DiSEqC FIFO
Address
$00(r/w)
$01(w)
$02(w)
$03(w)
$04(w)
$05(w)
$06(w)
$07(w)
$08(w)
$09(w)
DiSEqC Status
$0A(r)
IOCFG
$0C(w)
AGC1C
RTC
AGC1R
ACG2O
TLSR
CFD
ACLC
BCLC
CLDT
AGC1I
TL1R
ACG2I1
ACG2I2
RTF
VSTATUS
CLDI
ECNTH
ECNTL
SFRH
SFRM
SFRL
CFRM
CFRL
NIRH
NIRL
VERROR
FECM
VTH0
VTH1
VTH2
VTH3
VTH4
PR
VSEARCH
$0D(w)
$0E(w)
$0F(w)
$10(w)
$11(w)
$12(w)
$13(w)
$14(w)
$15(w)
$16(r/w)
$17(w)
$18(r/w)
$19(r/w)
$1A(r/w)
$1B(r)
$1C(r)
$1D(r)
$1E(r)
$1F(w)
$20(w)
$21(w)
$22(r/w)
$23(r/w)
$24(r)
$25(r)
$26(r)
$28(w)
$29(w)
$2A(w)
$2B(w)
$2C(w)
$2D(w)
$31(w)
$32(w)
$33(w)
$34(w)
RS
ERRCNT
18/36
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Chip identification number
Release number
K(1:0)
dirclk
M(4:0)
stdby
VCO off
serclock
P(2:0)
prescaler
divider
frequency register f_reg(7:0)
12CT
T- constant T- constant
SCLT value
SDAT value
DAC mode
DAC(11:8)
DAC(7:0)
LOCK output
LOCK conf
DiSEqC
DiSEqC mode
DiSE1C FIFO1(7:0)
SDAT input
IP
FE
FF
status
OP1_
OP0_
OP1_1
OP01
Nyquist filter
I/Q conv
opdrain
opdrain
DCadj
beta_agc1(2:0)
alpha_tmg(2:0)
beta_tmg(2:0)
Iagc
Reference Value
AGC2 coeff(2:0)
ACG2_Ref
step_minus(3:0)
step_plus(3:0)
FD on/off
beta_fd
FDTC
LDL
derot on/off
noise_TC
alpha_car
Ph_detect_algo
beta_car
Lock detector threshold
AGC integrator value
Timing lock indicator(7:0)
ACG2 integrator MSB
ACG2 integrator LSB
Timing loop frequency(7:0)
CF
PRF
LK
PR(2:0)
Lock detector integrator
Error count MSBs
Error count LSBs
Symb_freq(19:12)
Symb_freq(11:4)
Symb_freq(3:0)
Carrier frequency register MSB
Carrier frequency register LSB
Noise indicator MSBs
Noise indicator LSBs
Error value
FEC mode
out type
out imp
t0[6:0]
t1[6:0]
t2[6:0]
t3[6:0]
t4[6:0]
E4
E3
E2
E1
E0
A/M
F
SN(1:0)
TO(1:0)
H(1:0)
deint
sync
RS
descram
err bit
MPEG
clk pol
clk cfg
Errmode
tsters
Error source
NoE
STV0299B
5
REGISTER LIST
Note:
All register addresses are hexadecimal values. Signed registers are 2’s complement. All registers are read/write registers except
those specifically flagged as read-only (RO). All registers not listed in the below table, between 0 and 4E, should be programmed to
0.
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
IDENTIFICATION REGISTER (Read Only) (refer to Section 4.1.6 on page 8)
ID
00
A1
[7:0]
Gives the release number of the circuit in order to ensure software
compatibility.
REFERENCE CLOCK REGISTER (refer to Section 4.1.8 on page 8)
RCR
01
18 or 38
[7:6]
5
[4:0]
K[1:0]
DIRCLK (Reset value depends on the polarity of DIRCLK-DIS pin).
M[4:0]
MASTER CLOCK REGISTER (refer to Section 4.1.8 on page 8)
MCR
02
34 or B4
7
STDBY (Reset value depends on the polarity of STDBY pin).
6
VCO ON/OFF
0: ON
1: OFF
[5:4]
3
These bits must be programmed to one.
SERCLK
0: Maximum instantaneous SERCL = Master Clock
1: Maximum instantaneous SERCL =
[2:0]
F VCO
----------------6
P[2:0]
VC0 to M_CLK divider
19/36
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
AUXILIARY CLOCK REGISTER (refer to Section 4.1.8 on page 8)
ACR
03
2A
[7:0]
ACR Prescaler and Divider
This register is made up of the ACR [7:5] Prescaler field and the ACR
[4:0] Divider field. The values in these fields configure the auxiliary
clock function, the prescalar value, the clock signal frequency.
The frequency range is given for fVCO = 400 MHz.
ACR [7:0]
Function
Prescaler
Signal Frequency
Range
000XXXX0
Output
Port
N/A
output port = 0
N/A
000XXXX1
Output
Port
N/A
output port = 1
N/A
001XXXXX
HF
generator
1
fVCO/8/ACR[4:0]
1.6 to
50 MHz
010XXXXX
LF
generator
64
fVCO/8192/(32+ACR[4:0])
775 to
1525 Hz
011XXXXX
LF
generator
128
fVCO/16384/(32+ACR[4:0])
388 to
762 Hz
100XXXXX
LF
generator
256
fVCO/32768/(32+ACR[4:0])
194 to
381 Hz
101XXXXX
LF
generator
512
fVCO/65536/(32+ACR[4:0])
97 to
190 Hz
110XXXXX
LF
generator
1024
fVCO/131072/(32+ACR[4:0])
49 to
95 Hz
111XXXXX
LF
generator
2048
fVCO/262144/(32+ACR[4:0])
24 to
47 Hz
In the LF generator, the programmable division factor is
32 + ACR[4:0]. In the HF generator, it is simply ACR[4:0]. This allows
the building of any frequency from 24 Hz to 1.1 kHz (within ±1.5%) in
the full operating range. The output signal is square in all cases.
When the auxiliary register is written, the prescaler and the programmable divider are reset.
F22 FREQUENCY REGISTER (refer to Section 4.1.8 on page 8)
F22FR
04
8E
[7:0]
The actual frequency is fVCO/(128 R[7:0]). When this register is
accessed, the divider by 16 (also common to AUX_CLK) and the
divider by R[7:0] are initialized.
I2CRPT REGISTER (refer To Section 4.1.10 on page 10)
I2CRPT
05
0F
7
I2CT
1: I2C repeater
0: Output port
[6]
Must be programmed to zero.
[5:4]
20/36
Repeater response time; value does not matter if the external time
constant ≤ 250ns.
[3]
Must be programmed to zero.
2
SCLT Port value
1
This bit must be programmed to zero.
0
SDAT Port value
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
DAC REGISTERS (refer to Section 4.1.11 on page 10)
DACR1 (MSB)
06
A2
[7:5]
4
DACR2 (LSB)
07
00
DAC Mode
This field controls the DAC:
000: Functions as output port. The DAC output permanently 0.
001: Functions as output port. DAC output permanently 1.
010: High impedance mode.
100: Functions as DAC. Duty cycle modulated at fCLK/16.
101: Functions as DAC. Duty cycle modulated at fCLK/4.
110: Functions as DAC. Duty cycle modulated at fCLK.
Other: Reserved functions.
This bit must be programmed to zero.
[3:0]
DAC: 4 MSB
[7:0]
DAC: 8 LSB
DISEQC AND LOCK CONTROL REGISTER (refer to Section 4.1.12 on page 10)
DiSEqC
08
60
[7:6]
5
[4:3]
2
[1:0]
Lock Output
00: 0
01: 1
10: CF
11: LK
Lock Configuration
1: Open drain
0: Push-pull
These bits must be programmed to zero.
DiSEqC/Unmodulated Burst
DiSEqC Mode
DISEQC FIFO (refer to Section 4.1.12 on page 10)
DiSEqC FIFO
09
00
[7:0]
FIFO byte
DISEQC STATUS (refer to Section 4.1.12 on page 10)
DiSEqC
Status
0A
R0
7
Input Port: This bit gives the input level on the pin IP0. It is an input
port for general use purposes.
6
SDAT Input State
[5:2]
Not relevant.
1
FIFO empty
0
FIFO full
RESERVED
0B
Reserved
21/36
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
INPUT/OUTPUT CONFIGURATION REGISTER (refer to Section 4.2.1 on page 12)
IOCFG
0C
F0
7
OP1 control
1: Open drain
0: Normal
6
OP1 value
5
OP0 control
1: Open drain
0: Normal
4
OP0 value
3
This bit must be programmed to zero.
[2:1]
0
Nyquist Filter
These bits determine Nyquist filter settings:
00 = raised cosine at 35%
01 = raised cosine at 20%
10 = reserved
11 = reserved
Bit 0 when set, multiplies the data on the Q input by -1 in order to
accommodate QPSK modulation with another convention of rotation
sense. This is equivalent to a permutation of I and Q inputs, or a spectral symmetry. This permutation is performed after derotation.
AGC1 CONTROL REGISTER (refer to Section 4.2.2 on page 12)
AGC1C
0D
81
7
DC offset compensation:
1: On
0: Off
[6:3]
These bits must be programmed to zero.
[2:0]
beta_agc1
TIMING LOOP REGISTER (refer to Section 4.3.1 on page 13)
RTC
0E
23
7
[6:4]
3
[2:0]
This bit must be programmed to zero.
alpha_tmg
This bit must be programmed to zero.
beta_tmg
AGC1 REFERENCE REGISTER (refer to Section 4.2.2 on page 12)
AGC1R
0F
54
7
Iagc
1: Invert
0: Normal
If Iagc is set, the output signal is complemented (i.e. a high value for
the AGC voltage will cause a high gain in the tuner).
6
This bit must be programmed to zero.
[5:0]
AGC1 Reference Value (m1). Refer to page 12.
AGC2 AND OFFSET CONTROL REGISTER (refer to Section 4.2.5 on page 12)
AGC2O
22/36
10
74
[7:5]
AGC2 Coefficient
[4:0]
AGC2_Ref (m2)
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
TIMING LOCK SETTING REGISTER (refer to )
TLSR
11
88
[7:4]
Must be programmed to 8 (to be confirmed)
[3:0]
Must be programmed to 4 (to be confirmed)
CARRIER FREQUENCY DETECTOR REGISTER (refer to Chapter 4.4 on page 14)
CFD
12
F7
7
1: Carrier Frequency Offset Detector coupled to Carrier recover loop
0: Carrier Frequency Offset Detector disabled
[6:4]
Gain for Carrier Frequency Offset Detector
[3:2]
Time constant for Carrier Frequency Offset Detector
[1:0]
Lock Detector threshold to disable the Carrier Frequency Offset
Detector:
00: -16
01: -32
10: -48
11: -64
ALPHA CARRIER AND NOISE ESTIMATOR REGISTER (refer to Chapter 4.5 on page 14)
ACLC
13
88
7
Derotator On/Off
1: On
0: Off
6
This bit must be programmed to zero.
[5:4]
Noise Estimator Time Constant
00: 4 k symbols
01: 16 k symbols
10: 64 k symbols
11: 256 k symbols
[3:0]
alpha_car
Bits 3, 2 and 1: b[2:0]
Bit 0: a
BETA CARRIER REGISTER (refer to Chapter 4.4 on page 14)
BCLC
14
5C
[7:6]
phase_detector_algo
Phase detector algorithm:
00: Algorithm 0 (BPSK application)
01: Algorithm 1 (QPSK application)
10: Algorithm 2 (QPSK application)
11: Reserved
[5:0]
beta_car
Bits 5 to 2: e[3:0]
Bit 1: c
Bit 0: d
CARRIER LOCK DETECTOR THRESHOLD REGISTER (refer to Section 4.4.2 on page 14)
CLDT
15
14
[7:0]
Signed Number
AGC1 INTEGRATOR REGISTER (refer to Section 4.2.2 on page 12)
AGC1I
16
[7:0]
AGC Integrator Value (Signed Number)
TIMING LOCK INDICATOR REGISTER (refer to Section 4.3.3 on page 13)
TLIR
17
R0
[7:0]
(Not Signed)
23/36
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
AGC2 INTEGRATOR REGISTERS (refer to Section 4.2.5 on page 12)
AGC2I1 (MSB)
18
[7:0]
AGC2 Integrator MSB Bits (Not Signed)
AGC2I2 (LSB)
19
[7:0]
AGC2 Integrator LSB Bits (Not Signed)
TIMING FREQUENCY REGISTER (refer to Section 4.3.1 on page 13)
RTF
1A
[7:0]
Signed Number
VSTATUS REGISTER (Read Only) (refer to Section 4.6.3 on page 16)
VSTATUS
1B
RO
7
[6:5]
Carrier Found Flag
When the Carrier Found (CF) flag (see Chapter 4.4 on page 14) is
set, it indicates that a QPSK signal is present at the input of the Viterbi
decoder.
Not relevant.
4
Puncture Rate Found
The Puncture Rate Found (PRF) bit indicates the state of the puncture rate research: 0 for searching and 1 when found. This bit is irrelevant in manual mode.
3
Locked/Searching Sync Word
The LK bit indicates the state of the sync word search: 0 for searching
and 1 when found.
[2:0]
Current Puncture Rate, PR[2:0]
The Current Puncture Rate (CPR) bits hold the current puncture rate
indices, as follows:
100: Basic 1/2 (modes DVB and DSS) or Punctured 1/2 (reserved
mode)
000: Punctured 2/3
001: Punctured 3/4
010: Punctured 5/6
011: Punctured 7/8 (modes DVB and DSS) or 6/7 (reserved mode)
CARRIER LOCK DETECTOR VALUE REGISTER (refer to Section 4.4.2 on page 14)
CLDI
1C
[7:0]
Signed Number
ERROR COUNT REGISTERS (refer to Section 4.6.4 on page 16)
ERRCNT_HIGH
1D
[7:0]
MSB byte (Not Signed)
ERRCNT_LOW
1E
[7:0]
LSB byte (Not Signed)
SYMBOL FREQUENCY REGISTERS (refer to Section 4.3.1 on page 13)
SFRH
1F
80
[7:0]
Symb_freq (MSBs)
The reset value of Hex 800000 corresponds to fM_CLK/2.
SFRM
20
00
[7:0]
Symb_freq (Middle SBS)
SFRL
21
00
[7:4]
Symb_freq (LSBS)
[3:0]
These bits must be programmed to zero.
CARRIER FREQUENCY REGISTER (refer to Chapter 4.4 on page 14)
CFRM
22
[7:0]
Derotator Frequency (MSB) (signed value)
CFRL
23
[7:0]
Derotator Frequency (LSB) (signed value)
NOISE INDICATOR REGISTERS (Read Only) (refer to Chapter 4.5 on page 14)
24/36
NIRH
24
RO
[7:0]
Noise Indicator (MSB) (Not Signed)
NIRL
25
RO
[7:0]
Noise Indicator (LSB) (Not Signed)
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
VERROR REGISTER (Read Only) (refer to Section 4.6.2 on page 15)
VERROR
26
RO
[7:0]
Error Rate (Not Signed)
FEC MODE REGISTER (refer to Section 4.6.1 on page 15)
FECM
28
01
[7:4]
FEC Mode
This field indicates the FEC Operation mode and the FEC feeding.
0000: DVB (QPSK), FEC feeding IQ/IQ/IQ/IQ
0001: DVB (BPSK extension), FEC feeding IX/IX/IX/IX
001X: Reserved
0100: DSS, FEC feeding IQ/IQ/IQ/IQ
1XXX: Reserved
[3:2]
These bits must be programmed to zero.
1
Output Type
1: Serial
0: Parallel
0
Output Impedance
1: High Impedance
0: Normal Impedance
VITERBI THRESHOLD REGISTERS (refer to Section 4.6.2 on page 15)
VTH0
29
1E
[7:0]
Rate = 1/2 Threshold.
VTH1
2A
14
[7:0]
Rate = 2/3 Threshold.
VTH2
2B
0F
[7:0]
Rate = 3/4 Threshold.
VTH3
2C
09
[7:0]
Rate = 5/6 Threshold.
VTH4
2D
05
[7:0]
Rate = 7/8 or 6/7 Threshold.
PUNCTURE RATE AND SYNCHRO REGISTER (refer to Section 4.6.2 on page 15)
PR
31
1F
[7:6:5]
These bits must be programmed to zero.
4
Enable punctured rates 7/8 (in DVB) or 6/7 (in DSS).
3
Enable punctured rate 5/6.
2
Enable punctured rate 3/4.
1
Enable punctured rate 2/3.
0
Enable basic or punctured rate 1/2.
25/36
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
VITERBI AND SYNCHRO SEARCH REGISTER (refer to Section 4.6.2 on page 15)
VSEARCH
26/36
32
19
7
0: Automatic search mode
1: Manual search mode
6
Freeze
[5:4]
SN[1:0]
This is the averaging period. The field gives the number of bits
required to calculate the rate error.
00 = 1024
01 = 4096
10 = 16384
11 = 65536
Reset Value: SN = 01 (4096 bits)
[3:2]
TO[1:0]
This is the time out value (given in 1024-bit periods). This field is used
to program the maximum duration of the synchro word research in
automatic mode. If no sync is found within this duration, and if bit RS6
(Sync Enable) is set in the Reed-Solomon register, another phase or
puncture rate is tried. If RS6 = 0, the time-out has no effect.
00 = 16
01 = 32
10 = 64
11 = 128
Reset Value: TO = 10 (64k bit periods)
[1:0]
H[1:0]
This is the hysteresis value. This field is used to program the maximum value of the Sync counter. The unit is the block duration
(204 bytes in DVB, 147 in DSS).
00: 16
01: 32
10: 64
11: 128
Reset Value: H = 01 (32 blocks)
STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
RS CONTROL REGISTER (refer to Section 4.6.6 on page 16)
RS
33
F8
7
RS7 - Deinterleaver Enable
1: The input flow is deinterleaved.
0: The input flow is not affected.
6
RS6 - Synchro Enable
1: The synchro is processed.
0: The synchro word search is disabled. The bit-to-byte conversion
remains in its current phase regardless of whether the synchro
word is recognized or not. This allows the use of the STV0299BB
with
inner convolutional coding only.
5
RS5 - Reed-Solomon Enable
1: The input code is corrected.
0: No correction happens, all the data is fed to the descrambler.
The error signal remains inactive.
4
RS4 - Descrambler Enable
1: The output flow from Reed-Solomon decoder is descrambled.
0: The descrambler is disactivated.
3
RS3 - Write Error Bit
1: If an uncorrectible error happens in DVB, the MSB of the first byte
following the sync byte is forced to 1 after descrambling.
0: The output flow is unchanged.
2
RS2 - Block Synchro
1: The first byte of each packet is forced to Hex 47 in mode A.
0: The first byte is the one that is received. In DVB, it should be the
synchro byte, complemented every 8th packet.
1
RS1 - Output Clock Polarity
1: The data and control signals are clocked during the high-to-low
transition of CLK_OUT.
0: The data and control signals are clocked during the low-to-high
transition of CLK_OUT.
0
RS0 - Output Clock Signal Configuration during Parity Bytes
1: D[7:0] and ERROR are null during the parity bytes. If the packet
contains more than 8 errors, ERROR only remains high during the
data transmission. In parallel mode, CLK_OUT remains low during
the parity bytes. In serial mode, the output bit clock is always
running.
0: CLK_OUT is continuous and the parity bytes are transmitted. If the
packet contains more than 8 errors, ERROR remains high during
the entire packet.
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STV0299B
5
REGISTER LIST (continued)
Name
HEX
Address
Reset
Value
Bit
Position
Signal Description
ERROR CONTROL REGISTER (refer to Section 4.6.4 on page 16)
ERRCNT
28/36
34
01
7
Error Mode
1: Error count
0: Error rate
6
This bit must be programmed to zero.
[5:4]
Error Source
The error sources are as follows:
00: QPSK bit errors
01: Viterbi bit errors
10: Viterbi byte errors
11: Packet errors.
[3:2]
These bits must be programmed to zero.
[1:0]
NOE
The NOE bits represent the Count Period in bytes (NB):
00: 212 bytes
01: 214 bytes
10: 216 bytes
11: 218 bytes
STV0299B
6
ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
Maximum limits indicate where permanent device
damages occur. Continuous operation at these
Symbol
Parameter
VDD_3.3 V
VDD
V (1)
I
V (1)
O
Tstg
Toper
1
Value
Unit
4.0
3.0
V
V
Voltage on Input Pins
-0.5, VDD_3.3 V + 0.5
V
Voltage on Output Pins
-0.5, VDD_3.3 V + 0.5
V
-40, +150
-10, +70
°C
°C
+125
°C
Pad Power Supply Voltage
Core Level Power Supply Voltage
Storage Temperature
Operating Ambient Temperature
Tj
Note:
limits is not intended, and should be limited to
those conditions specified in Section 6.3 ‘DC
Electrical Characteristics’.
Junction Temperature
Except for AGC, SDA, SCL, SDAT, SCLT pin, which can be connected to 5 V +10% via a resistor.
6.2 Thermal Data
Symbol
Parameter
Max. Value
Rth(j-a)
Junction-ambient Thermal Resistance
Rth(j-c)
Junction-case Thermal Resistance
Note:
Note:
2
3
Unit
(4)
70
45(5)
11
°C/W
°C/W
Single-layer PCB.
Multi-layer PCB.
6.3 DC Electrical Characteristics
VDD = 2.5 V, VDD_3.3 V = 3.3 V and Tamb = 25°C unless otherwise specified.
Symbol
VDD_3.3 V
VDD_core
VDDA
VDD_STDBY
IDD 30M
IDDA 30M
IDD 45M
IDDA 45M
IDDsb
Parameter
Operating Voltage
Operating Voltage
Operating Voltage
Test Conditions
Circuit in stand-by
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
2.3
2.2
2.5
2.5
2.7
2.6
V
V
2.3
2.5
2.7
V
Operating Voltage
Average VDD_2.5V Current
Average VDDA Current
Circuit in stand-by
VDD=2.7V = 76MHz
200
mA
VDD=2.6V = 76MHz
50
mA
Average VDD_2.5V Current
Average VDDA Current
VDD=2.7V = 88MHz
240
mA
50
mA
Average Current in Standby Mode
VCO stopped
4
mA
0.8
V
V
1
µA
0.4
V
V
VDD=2.6V = 88MHz
VIL
VIH
ILK
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
3.6 V
VOL
VOH
High Level Output Voltage
Low Level Output Voltage
VDD_3.3 V = 3.3 V - 10%
0.5
2.0
ISOURCE = 1.6 mA
2.4
29/36
STV0299B
6
ELECTRICAL CHARACTERISTICS (continued)
6.3 DC Electrical Characteristics (continued)
VDD = 2.5 V, VDD_3.3 V = 3.3 V and Tamb = 25°C unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
2.0
V
V
2.0
V
V
RESET
VILT
VIHT
Low Level Threshold Falling Input
High Level Threshold Falling Input
0.8
VIL
VIH
Low Level Input Voltage
High Level Input Voltage
0.8
CIN
Input Capacitance
CLK_IN
3
pF
AGC/SDA/SCL/SDAT/SCLT
VOIL
ILK
Low Level Output Voltage
Input Leakage Current
ISINK = 2 mA
0.4
V
VAGC = 5.5 V
4.0
µA
0.8
Vpp
A/D CONVERTER
Vin
Differential Input Voltage
VTOP
High Voltage Reference
1.5
V
VBOT
Low Voltage Reference
1
V
Rin
DC Input Resistance
I/Q Inputs
106
Cin
Input Capacitance
I/Q Inputs
5
INL
Integral Non-Linearity
-1.5
+1.5
LSB
DNL
Differential Non-Linearity
-0.8
+0.8
LSB
SNR
Signal to Noise Ratio
30
33
36
dB
Neff
Effective Number of bits(1)
5.0
5.5
6.0
bits
Note:
30/36
1
Test conditions: F clock = 52MHz, FIN = 8MHz, VIN = 0.5 Vpp
0.4
0.5
∞
Ω
pF
STV0299B
6
ELECTRICAL CHARACTERISTICS (continued)
6.4 Timing Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
fVCO
Internal VCO frequency
300
400
fCLK_IN
CLK_IN or XTAL frequency
4
30
PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). Refer to Figure 8
tCLK_duty
CLK_OUT duty cycle
40
50
60
D[7:0],
D/P,
STR_OUT,
ERROR
stable
before
CLK_OUT
tCKSU
2*Tm(1)
Falling Edge
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
tCKH
2*Tm(1)
Falling Edge
tCKSU
tCKH
SERIAL
tCKSU
tCKH
%
ns
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). Refer to Figure 9
D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT
2*Tm(1)
Falling Edge
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
2*Tm(1)
Falling Edge
OUTPUT D7, D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 10
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
3.5
Falling Edge
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
3
Falling Edge
tCKH
1
ns
ns
ns
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 11
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
3.5
Falling Edge
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
2
Falling Edge
tCKSU
Note:
MHz
MHz
ns
ns
Tm = Master clock period in ns
Figure 8:
Figure 10:
CLK_OUT
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
D7, D/P.
STR_OUT,
ERROR
tCKSU
tCKH
tCKSU
tCKH
Figure 11:
Figure 9:
CLK_OUT
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
D7, D/P.
STR_OUT,
ERROR
tCKSU
tCKH
tCKSU
tCKH
31/36
STV0299B
6
ELECTRICAL CHARACTERISTICS (continued)
6.5 I2C Bus Characteristics
Symbol
Parameter
Test Conditions
Min.
VIL
VIH
Low Level Input Voltage
High Level Input Voltage
Pull up to 5 V ±10%
-0.5
2.0
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
Pull up to 5 V ±10%
ILK
Input Leakage Current
CIN
Input Capacitance
IOL
VIN = 0 V to 5 V
Output Sink Current
Typ.
-10
0
3.5
VOL = 0.5 V
10
Max.
Unit
0.8
5.5
V
V
5.5
0.4
V
V
10
µA
pF
mA
fSCLN
fSCLS
SCL Clock Frequency
tBUF
Bus Free Time between a STOP and START
Condition
1.3
µs
tHD, STA
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
0.6
µs
tLOW
tHIGH
Low Period of the SCL Clock
High Period of the SCL Clock
1.3
0.6
µs
µs
tSU, STA
Setup Time for a repeated START Condition
0.6
µs
tSU, STO
Setup Time for STOP Condition
0.6
µs
tSU, DAT
Data Setup Time
100
tR, tF
Rise and Fall Time of both SDA and SCL signals
300
ns
CB
Capacitive Load for each Bus Line
400
pF
Normal Mode
Standby Mode
fM_CLK/40
fCLK_IN/10
0
0
ns
Figure 12: I2C bus timing diagram
SD A
tBU F
tLOW
tR
tF
tH D ,STA
tSP
SC L
tH D ,STA
32/36
tH IG H
tSU ,D AT
tSU ,STA
-
tSU ,STO
STV0299B
7
APPLICATION BLOCK DIAGRAMS
Figure 13: Application Block Diagram
AGC Control
AGC1
I
ZIF or
Double Conversion
Q
2
Dual
ADC
QPSK
I2C Repeater
to PLL Synthesizer
FEC
4 MHz
LNB Supply
Serial or
Parallel
I/O +
DiSEqC
I 2C
4 serial or 12 parallel
To Transport IC
33/36
STV0299B
7
APPLICATION BLOCK DIAGRAMS (continued)
Typical Application Diagram
ZIF tuner or convential tuner
5V
5V
5V
R≤10K
R
R
5V 30V
2V5A
100 nF
5V
100 nF
120 Ω
5%
2V5A
22kΩ
2x
470Ω
(option)
4MHz
Clock
10kΩ
2V5D
10nF
2x
47 pF
2V5D
120 Ω
5%
120Ω
5%
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
4 MHz
22 pF
22 pF
2V5A
22V
12 Ω
3W
2V5D
48
2
47
3
46
4
45
5
44
6
43
7
42
2V5D
LNBP 15SP
2V5D
10kΩ
OLF
10kΩ
3V3
41
STV0299B
9
100 nF
2x
2.2 µF
1
8
2x
100 nF
2V5A
2V5D
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
OLF
10nF
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10kΩ
3V3
2V5D
12 x 47Ω
SDA
SCL
D7
D0
34/36
CONTROL
Serial Data
Serial Clock
CLK_OUT
Requirements: The digital ground and
the analog ground must be connected
by only one track.
Error
D/P
STR_OUT
RESET
Serial
DATA O/P
Parallel DATA O/P
Symbols:
this symbol represents a
Digital ground
this symbol represents an
Analog ground
STV0299B
8
PACKAGE MECHANICAL DATA
64 Pins Thin Plastic Quad Flat Pack (TQFP No Slug)
A
A2
e
64
A1
49
48
16
33
E3
E1
E
B
1
0,10 mm
.004 inch
SEATING PLANE
c
32
L
D3
D1
D
L1
17
K
0,25 mm
.010 inch
GAGE PLANE
Millimeters
Inches
Dimensions
Min.
Typ.
A
Max.
Min.
Typ.
1.60
Max.
0.063
A1
0.05
0.15
0.002
A2
1.35
1.40
1.45
0.053
0.055
0.057
0.006
B
0.17
0.22
0.27
0.007
0.009
0.011
C
0.09
0.20
0.004
0.008
D
12.00
0.472
D1
10.00
0.394
D3
7.50
0.295
0.0197
e
0.50
E
12.00
0.472
E1
10.00
0.394
E3
L
L1
K
7.50
0.45
0.60
0.75
0.018
1.00
0.295
-
0.024
0.030
0.039
0° (Min.), 7° (Max.)
35/36
STV0299B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support
devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
DiSEqCTM is a trademark of EUTELSAT.
DSSTM is a trademark of Hughes Inc. (USA).
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36/36