June 2003 Datasheet DMR01 Low Power Digital Multichannel Receiver FEATURES APPLICATIONS • • • • • • • • • • • • • • • • LOW COST MICRO POWER DESIGNED FOR DBPSK CODED DATA ERROR CORRECTING DECODER DIFFERENT TRANSMIT FREQUENCIES UNLICENSED FREQUENCY BAND DIFFERENT DATA RATES SHORT RANGE APPLICATIONS (up to 3m/10ft) TSSOP20 PACKAGE BATTERY POWERED SYSTEMS WIRELESS DATA TRANSMISSION ACCESS CONTROL ALARM FUNCTIONS WIRELESS INTERFACE REMOTE CONTROL WIRELESS TRANSMISSIONS THROUGH CONDUCTING FLUIDS General Description The DMR01 is a micro power receiver chip for low frequency data transmission systems. Based on a 32 kHz clock source, 8 different carrier frequencies from 8.192 kHz to 122.88 kHz are possible (fcr = (2n+1) x 8192 Hz, n = 0..7). Depending on the transmit distance and the transmit time, the DMR01 works with 4 different data rates from 1 to 8 kBaud. The DMR01 is able to receive coded data until with a maximum length of 128 bit for each transmit package. A frame detector gives the possibility to separate the data for different applications. The DMR01 uses a serial SPI register for a simple data exchange with external microcontrollers. Features like input amplifier gain, ADC sensitivity, data rate, selection of coded or uncoded data are programmable via the SPI interface. Block Diagram page 1 / 13 Datasheet_DMR01 June 2003 Electrical Specifications AC / DC Characteristics @ VDD = 3.3V ,TA = 25°C unless otherwise specified PARAMETER CONDITION MIN TYP MAX UNITS INPUT RECEIVER BANDWIDTH BW0 = 0 BW0 = 1 DATA RATE 10 130 kHz kHz Br = 00 Br = 01 Br = 10 Br = 11 INPUT @ BW0 = 1 1024 2048 4096 8192 Bit/s Bit/s Bit/s Bit/s Input Bias Voltage Input Impedance Voltage Gain (@ GA = 00) Voltage Gain (@ GA = 01) Voltage Gain (@ GA = 10) Voltage Gain (@ GA = 11) INPUT @ BW0 = 0 Input Bias Voltage Input Impedance Voltage Gain (@GA = 00) Voltage Gain (@GA = 01) Voltage Gain (@GA = 10) Voltage Gain (@GA = 11) PREAMPLIFIER NOISE @ BW0 = 1 small signal small signal 0.95 271 55 49 43 35 1.35 315 67 61 55 47 1.90 370 70 64 58 50 V kΩ dB dB dB dB 0.95 287 55 49 43 35 1.28 340 69 63 57 49 1.75 410 70 64 58 50 V kΩ dB dB dB dB Spectral Noise Voltage referred to Input (RMS) Broadband Output Noise PREAMPLIFIER NOISE @ BW0 = 0 @100kHz 1Hz – 1 MHz 77 165 nV/√ Hz mV Spectral Noise Voltage referred to Input (RMS) Broadband Output Noise POWERUP TIME @ 10kHz 1Hz – 1 MHz 213 193 nV /√ Hz mV 100 µs 100 µs 0.3VDD 10 10 5 5 10 10 V V MHz ns ns ns ns ns ns ns ns RECEIVER WAKE-UP TIME SPI-INTERFACE (Sin, Sout, Sck) Logical low level Logical high level Clock frequency Clock high time Clock low time Rise time (Clock) Fall time (Clock) Data input setup time Data input hold time Chip select setup time Chip select hold time 0.7VDD 5 80 80 POWER SUPPLY @ BW0 = 1 Standby current (Rec on = 0) Operating current (Rec on = 1) POWER SUPPLY @ BW0 = 0 No load, no clock fClk =32kHz 1 56 5 105 µA µA Standby current (Rec on = 0) Operating current (Rec on = 1) TEMPERATURE No load, no clock fClk =32kHz 1 43 5 90 µA µA 27 60 °C Specified range -20 page 2 / 13 Datasheet_DMR01 June 2003 Absolute maximum ratings PARAMETER CONDITION MIN TYP 2.5 3.6 Supply Voltage Voltage @ all Inputs and Outputs Pins VSS-0.3 ESD protection on all pins MAX 5.5 V VDD+0.3 V 1 Current @ all Input and Output Pins UNITS kV 10 mA Operating Temperature -20 85 °C Storage Temperature -65 150 °C 250 °C Soldering Temperature 10 seconds Pin Configuration TSSOP20 package Pin # ANAIN ANATST CMPIN AVDD AVSS NC TESTB RECON DVSS RESB F32K DMR01 CSB SOUT SIN IRQB SCK DVSS DVDD CKOUT DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 page 3 / 13 Name Description ANAIN CMPIN AVSS RECON DVSS RESB F32K IRQB DVSS CLKOUT DOUT DVDD SCK SIN SOUT CSB TESTB NC AVDD ANATST RF input signal Level detect input Analog Ground Power for external circuit Digital ground Reset Input for external clock Interrupt (valid data received) Digital ground Clock for uncoded data Uncoded data output Digital supply voltage Serial data clock for SPI Serial data input for SPI Serial output for SPI Chip select Test pin Not connected Analog supply voltage Test pin (output) Datasheet_DMR01 June 2003 Module Description Input Amplifier and A/D Conversion Fig. 2 shows a block diagram of the input stage. The input stage consists of an input amplifier, a flash A/D-converter and a comparator for high energy detection of the input signal. The input amplifier has a gain of about 2’000 which simplifies external circuitry. The A/D-converter has a resolution of 4 Bit and converts the input signal into a signed 4 bit word within less than 1µs. Sampling frequency is 32’768 Hz. To save power in stand by mode the analog input stage can be switched of (‘RecOn’). The comparator detects high level input signals on it’s input Cmpin. This input is normally connected directly to the receiving antenna. Due to the modulation technique, there will always be a number of sinusoidal waves per transmitted bit. The output of the comparator enters therefore a counter (located in the interface part) which counts the number of waves with high energy. At the end of a transmission the value of this counter gives an information about the energy level of the received data stream. This feature is used to detect if a transmitter is located very close to the receiving antenna. Bit Estimator Fig. 3 shows a block diagram of the bit estimator. The bit estimator uses a very sophisticated and efficient algorithm to estimate incoming data out of the 4 bit information of the A/D-converter. It is designed to work with phase modulated input signals. More precisely, the modulation technique is differential binary phase shift keying (DBPSK). This means that there is a phase shift of 180° with every transmitted logic 1. Depending on the programmed baud rate the estimator expects 1, 2, 4 or 8 sinusoidal waves per bit for baud rates of 8’192, 4’096, 2’048 or 1’024 bit/s. The estimator is also able to detect the signal energy. ‘Aqual’ is high if the estimated bit ‘Aest’ has an energy level of more than programmed in ‘BitQLevel’. ‘Aest’ and ‘Aqual’ are updated with the negative edge of ‘Clka’. To save power in stand by mode the bit estimator can be switched off (‘RecOn’). page 4 / 13 Datasheet_DMR01 June 2003 Frame Detector Fig. 4 shows a block diagram of the frame detector. It’s function is to detect a special string in the incoming data stream of ‘Aest’ / ‘Clka’. The string which will be detected can be programmed with the 12 bit input word ‘Frame’. The detector accepts an incoming string as start frame if a certain number of bits (‘FrmQLevel’) of the incoming frame word have a high energy level (‘Aqual’ = 1) and a certain number of bits (‘NoOfMatch’) matche the frame word ‘Frame’. In this case the signal ‘FMatch’ will be change from low to high and the following input bits (‘Aest’ / ‘Clka’) will be connected to ‘Best’ / ’Clkb’. ‘Best’ is updated with the negative edge of ‘Clkb’ and the detector will not recognize any other strings until the ‘Fclr’ input is set to ‘1’. ‘Fclear’ is controlled by the interface. It resets the detector if transmission is finished. The frame detection function can be disabled (‘Fdeton’ = 0). In this case the decoder will also not work and ‘Best’, ‘Clkb’ remains 0. Decoder A Best Clkb Code- and Databit Separator Enable Di Ci Clks Syndromgenerator Majority Decision Mux B Fmatch Y Enable A/B Decode Fig. 5 shows a block diagram of the decoder. It decodes a convolutional code with rate ½ using a polynomial function. The incoming bits are grouped in pairs of 2 bits whereas Cest the first one is the code bit and the second one is the original data bit. The threshold decoder decodes these Clkc set of pairs into a data stream appearing at ‘Cest’ / ‘Clkc’. Data will be updated on the negative edge of ‘Clkc’. The decoding procedure will be started with a high level at ‘Fmatch’. It is also possible to disable the decoding function. If ‘Decode’ is low the decoder will map ‘Best’ / ‘Clkb’ to ‘Cest’ / ‘Clkc’ if Fmatch is high. Fig.5: Decoder Interface Fig. 7 shows the block diagram of the Interface. The interface has different functions: - Communication with a microprocessor (SPI-interface) Saving all register values for programming Saving incoming data Interrupt function Counting pulses for high input energy detection Additionally the interface also handles the end of a transmission. The first 4 incoming bits (MSB first) after the low to high transition of ‘Fmatch’ define the number of bytes the currently transmitted block will have. The interface resets the frame detector exactly after this number of bytes is stored. An interrupt will be generated after completion of transmission (IRQ changes to low) and a request flag is set in the interrupt register. A counter counts the pulses from the comparator. The upper 8 bit of the 11bit counter can be read by the SPIinterface. page 5 / 13 Datasheet_DMR01 June 2003 Communication via SPI Interface Each data transfer is initialized with a 8bit control word: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Cmd2 Cmd1 Cmd0 Adr4 Adr3 Adr2 Adr1 Adr0 Cmd2...Cmd0 represent the command word and define the action. Adr4..Adr0 is the address which will be accessed. The following commands are possible: Cmd2 Cmd1 Cmd0 Action 0 0 0 Not defined 0 0 1 Read register (address 00 to 07H) 0 1 0 Read YCUML (only for test) 0 1 1 Read YCUMH (only for test) 1 0 0 Read incoming data (address 00 to 11H) 1 0 1 Write register (address 00 to 07H) 1 1 0 Read ZINTL (only for test) 1 1 1 Read ZINTH (only for test) Each data transfer starts with a command and a corresponding address. Communication is initialized with the falling edge of CS. There is an auto increment function implemented for read and write operation. This means that the command word is necessary only once for consecutive addresses. The MSB (most significant bit, bit7) has to be set first in write operation and will be present first in read operation. Data at ‘Sin’ is sampled with the positive edge of ‘Sck’ whereas Data at ‘Sout’ will be updated with the negative edge of ‘Sck’. Bus Timing Write Sequence Fig.8 shows the write timing. In this case the command word is “write register (address 00H)”. The value which is stored in this register is AAH. Read Sequence Fig.9 shows the read timing. In this case the command word is “read register (address 00H)”. The value which is clocked at ‘Sout’ is AAH. page 6 / 13 Datasheet_DMR01 June 2003 Registers for DMR01 configuration The system consists of several registers for programming the desired function. All registers will be reset to 0 with ‘Res’ = ‘0’. Control register Register name: Access: Description: CNT R/W Control register for programming the function of the DMR-01 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Out1 Out0 Br1 Br0 Dec on Fdet on Rec on Description: Bit 0 00H Out1,Out0 = 00 : no internal signals available at Pin ‘Datout’ and Pin ‘Clkout’ 01 : ‘Aest’ is mapped to ‘Datout’, ‘Clka’ is mapped to ‘Clkout’ 10 : ‘Best’ is mapped to ‘Datout’, ‘Clkb’ is mapped to ‘Clkout’ 11 : ‘Cest’ is mapped to ‘Datout’, ‘Clkc’ is mapped to ‘Clkout’ Br1,Br0 = 00 : baud rate is set to 1’024 bit/s 01 : baud rate is set to 2’048 bit/s 10 : baud rate is set to 4’096 bit/s 11 : baud rate is set to 8’192 bit/s Dec on = 0 : Decoder is not enabled 1 : Decoder is enabled Fdet on = 0 : Frame detector is off 1 : Frame detector is on Rec on = 0 : Receiver is off (including input amplifier) 1 : Receiver is on Address In order to guarantee proper function ‘Rec on’ must be set to ‘0’ before any of Bit2 to Bit5 is changed. Interrupt register Register name: Access: Description: Bit 7 INT R/W (write access is only possible for IE) Interrupt status register Bit 6 Bit 5 IRQ Bit 4 Bit 3 Bit 2 IE Description: IE = 0 : Interrupt capability disabled 1 : Interrupt capability enabled IRQ = 0 : Interrupt not requested 1 : Interrupt request after received data Bit 1 Bit 0 Address 01H An interrupt request will be reset by ‘Res’ = ‘0’ or by reading any of the data registers. In this case the positive edge of ‘CS’ will trigger the clear function. This means that ‘CS’ must be high to start the receiver again. page 7 / 13 Datasheet_DMR01 June 2003 Bit Quality level registers Register name: BITQLEVELH (high byte) BITQLEVELL (low byte) R/W Bit quality level (energy level which represents good bit quality) Access: Description: High byte: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address BQL15 BQL14 BQL13 BQL12 BQL11 BQL10 BQL9 BQL8 02H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address BQL7 BQL6 BQL5 BQL4 BQL3 BQL2 BQL1 BQL0 03H Low Byte: Frame quality level Register Register name: Access: Description: FRMQLEVEL R/W Frame quality level (number of bits out of the 12 frame bits which must have an energy level which is higher than programmed in “Bit Quality level register” such that a frame is accepted) and number of matches (number of incoming bits which have to match the frame word) for acceptance. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address NOM3 NOM2 NOM1 NOM0 FQL3 FQL2 FQL1 FQL0 04H The numbers represented in FQL3..FQL0 and NOM3..NOM0 must be less or equal 12. Frame registers Register name: FRAMEH (high byte) FRAMEL (low byte) R/W High Byte of the frame word Access: Description: High byte: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address - - - - FRM11 FRM10 FRM9 FRM8 05H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 06H Low byte: page 8 / 13 Datasheet_DMR01 June 2003 Controlregister for analog part Register name: Access: Description: ANACNTRL R/W Setup of analog part Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address GA1 GA0 BW0 ADR1 ADR0 CPS2 CPS1 CPS0 07H Description: CPS2,CPS1,CPS0: This 3 Bits define the reference level of the comparator. “000” is Vdd/2. “111” means Vdd*15/16. ADR1,ADR0: 00 : Input range for A/D-converter is about +/- 0.4 * Vdd 01 : Input range for A/D-converter is about +/- 0.2 * Vdd 10 : Input range for A/D-converter is about +/- 0.1 * Vdd 11 : Input range for A/D-converter is about +/- 0.05 * Vdd BW0 = 0 : 8 kHz Input Receiver Bandwidth Mode 1 : 122 kHz Input Receiver Bandwidth Mode GA1,GA0: 00 : Input amplifier voltage gain is about 2’000 01 : Input amplifier voltage gain is about 1’000 10 : Input amplifier voltage gain is about 500 11 : Input amplifier voltage gain is about 200 Cumulator output registers Register name: YCUMH (high byte) YCUML (low byte) R Output of the cumulator (only for test purposes) Access: Description: High byte: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address YCUM15 YCUM14 YCUM13 YCUM12 YCUM11 YCUM10 YCUM9 YCUM8 - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address YCUM7 YCUM6 YCUM5 YCUM4 YCUM3 YCUM2 YCUM1 YCUM0 - Low byte: These 2 registers are read by direct commands (see 5.7). Statistic output registers Register name: ZINTH (high byte) ZINTL (low byte) R Statistic of the Bitestimator (only for test purposes) Access: Description: High byte: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address ZINT15 ZINT14 ZINT13 ZINT12 ZINT11 ZINT10 ZINT9 ZINT8 - Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address ZINT7 ZINT6 ZINT5 ZINT4 ZINT3 ZINT2 ZINT1 ZINT0 - Low byte: These 2 registers are read by direct commands. page 9 / 13 Datasheet_DMR01 June 2003 Registers for data receiving All data registers will be reset to 0 with ‘Res’ = ‘0’. Number of received Bytes Register name: Access: Description: NOB R Number of received bytes - 1 of the last reception. If NOB is zero, then one byte of data was transmitted. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address 0 0 0 0 NOB3 NOB2 NOB1 NOB0 00H Data bytes Access: Description: Bit 7 R Received data. The end address depends on the message length (max. 10H) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MSB Bit 0 Address LSB 01H to 10H High energy detector Register name: Access: Description: ECOUNTER R Number of signal waves at the comparator input with high energy. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address EC10 EC9 EC8 EC7 EC6 EC5 EC4 EC3 * th ECOUNTER represents the number of signal waves at the ‘Cmpin’ input with a level higher than the reference value. Only every 8 clock is counted (positive edge triggered). *: The address of this register depends on the length of the received data stream. ECONTER is attached at the end of the message. ECOUNTER will be reset after reading data. page 10 / 13 Datasheet_DMR01 June 2003 Received data Dataformat and Coding Uncoded: Coded: 8 Bit 12 Bit 4 Bit Preamble Frameword No.of Bytes 8 Bit 12 Bit 8 Bit Max. 128 Bit Data max. 16Bytes Max. 256 Bit 0 Bit Postamble 12 Bit Fig. 10: Dataformat For a proper function of the receiver, the transmitter has to do the correct function. First it is important to note the used dataformat as described in Fig. 8. Each datastream consists of a 8 bit preamble, a 12 bit frameword, a 4 bit information for the number of transmitted bytes, the data (up to 16 Bytes) and a postamble. A ‘0000’ for the number of bytes means that 1 byte is transmitted. A ’1111’ means that 16 bytes are transmitted. For each bit, the transmitter must transmit a number of consecutive sinusoidal waves. This number is 8 for a baud rate of 1kbit/s, 4 for a baud rate of 2 kBit/s, 2 for a baud rate of 4 kbit/s and 1 for baud rate 8 kbit/s. The modulation technique is Differential Binary Phase Shift Keying (DBPSK). Therefore the phase of the sinusoidal waves has to be shifted by 180° if the bit (which actually should be transmitted) is logic high. The phase remains unchanged during transmission of this bit. If the coding function is used, the information has to be encoded according to a special function (not disclosed at the moment). Note that in case of coded transmissions only the data after the frameword has to be encoded. The postamble is necessary to bring the decoder to it’s default state. Preamble and postamble should use an all one sequence(’11...11’) In case of uncoded transmission the postamble is not necessary. The encoder must be initialized with ‘000000’ prior to every datastream. page 11 / 13 Datasheet_DMR01 June 2003 Package Information TSSOP20 page 12 / 13 Datasheet_DMR01 June 2003 MIN NOM A MAX NOTE 1.10 A1 0.05 0.15 A2 0.85 0.90 0.95 D 6.40 6.50 6.60 3, 8 E1 4.30 4.40 4.50 4, 8 E 6.4 BSC e 0.65 BSC L 0.50 R 0.09 R1 0.09 b 0.19 0.60 0.75 0.30 0.22 b1 0.19 c 0.09 0.20 c1 0.09 0.16 θ1 0° 8° L1 1.0 REF aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 e 0.65 BSC θ2 12° REF θ3 4.40 mm Body 0.65 mm Lead Pitch 5 0.25 12° REF Note : 1, 2 Issue : A BSC = Basic ... NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M – 1994. 3. DIMENSION ’D’ DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. 4. DIMENSION ’E1’ DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. 5. DIMENSION ’b’ DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE ’b’ DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07 MM FOR 0.5 MM PITCH PACKAGES. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DATUMS -A - AND - B - TO BE DETERMINED AT DATUM PLANE - H - 8. DIMENSIONS ’D’ ANO ’E1’ ARE TO BE DETERMINED AT DATUM PLANE - H - 9. THIS DIMENSION APPLIES ONLY TO VARIATIONS WITH AN EVEN NUMBER OF LEADS PER SIDE. FOR VARIATION WITH AN ODD NUMBER OF LEADS PER SIDE, THE “CENTER“ LEAD MUST BE COINCIDENT WITH THE PACKAGE CENTERLINE,. DATUM A. 10. ACROSS SECTION A – A TO BE DETERMINED AT 0.10 TO 0.25 MM FROM THE LEADTIP. 11. THIS VARIATION IS NOT REGISTERED WITH JEDEC. page 13 / 13