CXD1961AQ
DVB-S Frontend IC (QPSK demodulation + FEC) Preliminary
For the availability of this product, please contact the sales office.
Description
The CXD1961AQ is a single chip DVB compliant
Satellite Broadcasting Frontend IC, including dual
A/D converter for analog baseband I/Q input, QPSK
demodulator, Viterbi decoder Reed-Solomon decoder
and Energy Dispersal descrambler. It is suitable for
use in a DVB Integrated Receiver Decoder.
100 pin QFP (Plastic)
Features
• Dual 6 bit A/D converter
Absolute Maximum Rating (Ta = 25°C, GND = 0V)
• QPSK demodulator
• Power Supply
VDD
–0.5 to +4.6
V
Multi-symbol rate operation
• Input Voltage
VIN
–0.5 to VDD + 0.5 V
Nyquist Roll off filter (α = 0.35)
• Output Voltage
VOUT –0.5 to VDD + 0.5 V
Clock recovery circuit
• I/O Voltage
VI/O –0.5 to VDD + 0.5 V
Carrier recovery circuit
• CPU I/F pin
Vcpuif –0.5 to +5.5
V
AGC control (PWM output)
• Storage Temperature Tstg
–55 to +150
°C
• Viterbi decoder
Constraint length 7
Recommended Operating Condition
Truncation length 144
(Ta = 0 to 75°C, GND = 0V)
BER monitor of QPSK demodulator output
• Power Supply
VDD
3.15 to 3.45
V
• Frame synchronization circuit
• Input High level
VIH 0.7 × VDD to VDD + 0.5 V
• Convolutional de-interleaver
• Input Low level
VIL
0.3 to 0.2 × VDD
V
• Reed-Solomon decoder (204,188)
BER monitor of Viterbi decoder output
• Energy dispersal descrambler
• CPU interface circuit
I2C bus interface (5V input capability)
• Package
QFP 100pin
• Operating frequency
20 to 30MSPS
• Power consumption
750mW (@3.3V 30MSPS typical)
• Process
0.4µm CMOS Technology
Application
DVB-S Set Top Box (Satellite)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE97854-PS
VSS9
QSYNC
FSYNC
AVD4
AVS4
AVD2
OPOUT
VCOC
OPXIN
OPOUT
RT1
VCOEN
AVD1
QIN
AVS1
RT0
RB1
AVD0
IIN
Block Diagram
AVS2
CXD1961AQ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AVS0
1
RB0
2
80 VDD9
analog I/O
Sampling
Clock
2ch ADC
VDD0 3
VSS0
4
TEST1
5
79 CR7
PLL
VCO
78 CR6
77 CR5
76 CR4
QPSK
Demodulator
TEST2 6
75 VSS8
74 VDD8
TEST3 7
TEST4 8
73 CR3
NC 9
72 CR2
71 CR1
VDD1 10
VSS1 11
70 CR0
NCO
Viterbi Decoder
SDAT/SCL 12
69 CKV
SCLK 13
68 AGCPWM
67 VSS7
SEN/SDA 14
VDD2 15
66 VDD7
VSS2 16
65 VCK
De-interleaver
64 VDT
Oscillator
TCK 17
TMS 18
TEST6 19
TEST7 20
63 XI
62 XO
61 AVS3
CK8OUT 21
60 AVD3
RESET 22
Reed-Solomon
Decoder
TE 23
59 SDA
CPU I/F
I2C bus
58 SCL
VDD3 24
57 TEST22
VSS3 25
56 TEST21
55 TEST20
PKTCLK 26
Energy Dispersal
BYTCLK 27
54 VSS6
53 VDD6
PKTERR 28
decoded data
& clock
DATA0 29
DATA1 30
52 TEST19
51 TEST18
TEST17
TEST16
TEST15
TEST14
TEST13
VSS5
VDD5
TEST12
TEST11
TEST9
TEST10
TEST8
DATA7
DATA6
VSS4
DATA5
VDD4
DATA4
DATA3
DATA2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Typical Block Diagram
LNB
QPSK + FEC
I/Q
detector
Amp
Data
SAW
LPF
SONY
CXD1961AQ
Clock
LPF
VCO
PLL
479.5MHz
90°
Reference
OSC
Micro Controller
–2–
LPF
Crystal
CXD1961AQ
Functional Description
(1) A/D Converters
The CXD1961AQ has dual 6 bit A/D converters to quantize the analog baseband I/Q signal. The sampling rate
is two times the symbol rate. The input range is determined by the external resisters. See reference circuit (1).
The DC offset cancellation function is set by setting CPU I/F register 1E,1F(hex).
(2) Clock Recovery Circuit
The CXD1961AQ can operate at multiple symbol rates between 20 to 30MSPS. Initial sampling clock
frequency is set by a 24 bit control word via CPU I/F register 18, 19, 1A (hex). This control word is written to
the numerically controlled oscillator (NCO). The internal clock recovery loop feeds clock error data to the
above NCO to provide sampling timing correction. The relation between the symbol rate and the control word
is;
(symbol rate) = 4 × NCO [23:0] × Fcrystal ÷ 224 (Hz)
where NCO [23:0] is the 24 bit control word and Fcrystal is crystal frequency (Hz).
The clock recovery loop coefficient and the loop gain are set by setting CPU I/Fregister 0C (hex) accordingly.
See reference circuit (2). The recovered symbol clock can be monitored at Pin 69.
There are three internal sub-registers to save the NCO control word. By setting the number of the preset subregister, the control word corresponded to the certain symbol rate is set to the internal NCO. Contents of the
sub-register are deleted by power off or reset by pin 22. Refer to the explanation of CPU I/F register 0D (hex).
(3) Carrier Recovery Circuit
Any carrier frequency offset which remains on the analog baseband I/Q input is compensated by the internal
digital costas loop. The capture range is ±Rs/8 (Rs: symbol rate). When the carrier capture is performed,
QPSK lock flag QSYNC goes high. QSYNC is output at Pin 82 and CPU I/F register 09 (hex). In QPSK
synchronization, the carrier offset estimation value is output at CPU I/F register 02 (hex) as AFC [7:0]. The
frequency offset is;
(carrier offset) = Rs × AFC [7:0] ÷ 512 (Hz)
where AFC7 is the sign bit that represents the direction of the offset.
(4) Nyquist Roll off Filter
The Nyquist roll off filter for each channel are embedded. The roll off factor is 0.35.
–3–
CXD1961AQ
(5) Auto Gain Control
By comparing the demodulated I/Q amplitude (I2 + Q2) and the reference level which is set via CPU I/F register
21 (hex), the AGC control signal is generated as PWM output at Pin 68. The polarity of the AGC can be
reversed by setting CPU I/F register 10 (hex). For the Tuner interface, see the reference circuit (4).
(6) Viterbi Decoder
The punctured decoding and Viterbi decoding are performed on the demodulated I and Q data. The punctured
rate is programmable from 1/2 to 7/8. When punctured mapping is performed, Viterbi lock flag at CPU I/F
register 09 (hex) goes one. Bit error count at QPSK demodulator output is estimated and output to CPU I/F
register 03, 04 (hex) as 16 bit data.
(7) Frame synchronization and Deinterleaver
By detecting the MPEG2 sync word 47 (hex), the synchronization of the data packet is achieved, and the
convolutional deinterleaver then recovers the original data order.
(8) Reed-Solomon Decoder
In DVB systems, 16 parity bytes are added to the 188 data bytes, so that up to 8 error bytes are correctable by
the Reed-Solomon decoder. If there are more than 8 error bytes in a packet, error correction is not performed
and the packet error flag PKTERR (Pin 28) goes high during the packet to indicate that the packet is not
correctable. The MSB of the second byte of the uncorrectable packet also becomes one. Bit error count at
Viterbi decoder output is estimated and output every 1280 packet (=204 × 8 × 1280 bit) to CPU I/F register 06,
07 (hex) at a resolution of 16 bits.
(9) Energy Dispersal Descrambler
Energy dispersal descrambling is represented by the polynomial X15 + X14 + 1. The initial sequence is loaded
when an inverted MPEG sync word B8 (hex) is detected. When MPEG sync word including inverted one is
detected every 204 bytes, the lock flag of the whole IC "FSYNC" goes high. FSYNC is output at Pin 83 and
CPU I/F register 09 (hex).
–4–
CXD1961AQ
(10) CPU Interface
The CXD1961AQ has an I2C bus interface. Serial clock SCL is Pin 58 and serial data in out SDA is Pin 59.
Slave address is "1101 111" (DChex).
STA: start condition
STP: stop condition
Input data for
sub-address
N + 1 (hex)
STP
Input data for
sub-address
N (hex)
ACK
Sub address
N (hex)
ACK
0
ACK
Slave address
1101 111
ACK
STA
<Write data>
During the write operation, the second byte is input as the sub-address of the start position. The third byte then
forms the data to be written to the start register. Successive data bytes are written to the successive subaddress registers up to 21 (hex). Note that registers of sub-addresses 00 (hex) to 0B (hex) are read only.
···
ACK: acknowledge
XACK: no acknowledge
<Read operation>
–5–
STP
···
XACK
STP
Both SCL and SDA have 5V input capability.
Output data for
sub-address
N + 1 (hex)
ACK
Output data for
sub-address
N (hex)
ACK
1
Sub address
N (hex)
ACK
Slave address
1101 111
ACK
0
ACK
STA
Slave address
1101 111
STA
Before the read operation, the sub-address of the start register to be read is input by using write operation, and
terminated with a stop condition. Read operation then begins with the second byte which is the data of the start
register. Data of the successive sub-address registers are read successively following the second byte. All
registers can be read.
CXD1961AQ
QSYNC
VSS9
FSYNC
AVD4
AVS4
OPOUT
AVD2
VCOC
OPXIN
OPOUT
AVS2
VCOEN
RT1
AVD1
QIN
AVS1
RB1
RT0
AVD0
IIN
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AVS0
1
80 VDD9
RB0
2
79 CR7
VDD0
3
78 CR6
VSS0
4
77 CR5
TEST1
5
76 CR4
TEST2
6
75 VSS8
TEST3
7
74 VDD8
TEST4
8
73 CR3
NC
9
72 CR2
VDD1 10
71 CR1
VSS1 11
70 CR0
69 CKV
SDAT/SCL 12
SCLK 13
68 AGCPWM
SEN/SDA 14
67 VSS7
VDD2 15
66 VDD7
VSS2 16
65 VCK
TCK 17
64 VDT
TMS 18
63 XI
TEST6 19
62 XO
TEST7 20
61 AVS3
CK8OUT 21
60 AVD3
RESET 22
59 SDA
TE 23
58 SCL
57 TEST22
VDD3 24
VSS3 25
56 TEST21
PKTCLK 26
55 TEST20
BYTCLK 27
54 VSS6
53 VDD6
PKTERR 28
DATA0 29
52 TEST19
DATA1 30
51 TEST18
–6–
TEST16
TEST17
TEST15
TEST14
TEST13
VDD5
VSS5
TEST12
TEST11
TEST9
TEST10
TEST8
DATA7
DATA6
DATA5
VSS4
VDD4
DATA4
DATA3
DATA2
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXD1961AQ
Pin List
Symbol
No.
I/O type
1
AVS0
Analog VSS
2
RB0
Ref. voltage input
3
VDD0
Digital VDD
4
VSS0
Digital VSS
TEST1 to 4
CMOS input
9
NC
No Connection
10
VDD1
Digital VDD
11
VSS1
Digital VSS
12
SDAT/SCL
3-state CMOS output
13
SCLK
3-state CMOS output
14
SEN/SDA
In out with Pull up
15
VDD2
Digital VDD
16
VSS2
Digital VSS
17
TCK
Input with pull up
18
TMS
Input with pull up
19
TEST6
CMOS input
20
TEST7
Input with pull up
21
CK8OUT
CMOS output
22
RESET
Input with pull up
23
TE
Input with pull down
24
VDD3
Digital VDD
25
VSS3
Digital VSS
26
PKTCLK
3-state CMOS output
27
BYTCLK
3-state CMOS output
28
PKTERR
3-state CMOS output
DATA0 to 4
3-state CMOS output
34
VDD4
Digital VDD
35
VSS4
Digital VSS
36 to 38
DATA5 to 7
3-state CMOS output
39 to 43
TEST8 to 12
CMOS in out
44
VDD5
Digital VDD
45
VSS5
Digital VSS
46 to 48
TEST13 to 15
CMOS in out
49 to 52
TEST16 to 19
CMOS input
5 to 8
29 to 33
–7–
CXD1961AQ
No.
Symbol
I/O type
53
VDD6
Digital VDD
54
VSS6
Digital VSS
TEST20 to 22
CMOS input
58
SCL
5V input
59
SDA
5V open drain in out
60
AVD3
Crystal VDD
61
AVS3
Crystal VSS
62
XO
Oscillator output
63
XI
Oscillator input
64
VDT
CMOS in out
65
VCK
CMOS in out
66
VDD7
Digital VDD
67
VSS7
Digital VSS
68
AGCPWM
CMOS output
69
CKV
CMOS in out
CR0 to 3
CMOS output
74
VDD8
Digital VDD
75
VSS8
Digital VSS
CR4 to 7
CMOS output
80
VDD9
Digital VDD
81
VSS9
Digital VSS
82
QSYNC
CMOS output
83
FSYNC
CMOS output
84
AVD4
Analog VDD
85
AVS4
Analog VSS
86
CPOUT
3-state CMOS output
87
AVD2
Analog VDD
88
VCOC
Analog input
89
OPXIN
Analog input
90
OPOUT
Analog output
91
AVS2
Analog VSS
92
VCOEN
CMOS input
93
RT1
Ref. voltage input
94
AVD1
Analog VDD
55 to 57
70 to 73
76 to 79
–8–
CXD1961AQ
No.
Symbol
I/O type
95
QIN
Analog input
96
AVS1
Analog VSS
97
RB1
Ref. voltage input
98
RT0
Ref. voltage input
99
AVD0
Analog VDD
100
IIN
Analog input
Note) Apply 0.1µF capacitor to every power supply terminal and reference voltage input (RB0, RB1, RT0, RT1).
–9–
CXD1961AQ
Pin Explanation
1. A/D Converter
ADC for I input
Function
ADC for Q input
Pin No.
Pin name
Pin No.
Pin name
Analog signal input
100
IIN
95
QIN
Top reference level input
98
RT0
93
RT1
Bottom reference level input
2
RB0
97
RB1
Analog power supply (+3.3V)
99
AVD0
94
AVD1
Analog ground
1
AVS0
96
AVS1
Pin No.
Pin name
Crystal oscillator (output)
62
XO
Crystal oscillator (input)
63
XI
Crystal oscillator power supply (+3.3V)
60
AVD3
Crystal oscillator ground
61
AVS3
Pin No.
Pin name
Charge Pump output
86
CPOUT
Charge pump power supply (+3.3V)
84
AVD4
Charge pump ground
85
AVS4
VCO control voltage input
88
VCOC
VCO enable (H: enable)
92
VCOEN
OP-Amp negative input
89
OPXIN
OP-Amp output
90
OPOUT
VCO · OP-Amp power supply (+3.3V)
87
AVD2
VCO · OP-Amp ground
91
AVS2
See reference circuit (1)
2. Clock Recovery
2-1. Crystal
Function
See reference circuit (3)
2-2. VCO · OP-Amp
Function
See reference circuit (2)
– 10 –
CXD1961AQ
2-3. Clock Recovery
Function
Pin No.
Pin name
70 to 73
76 to 79
CR0 to 3
CR4 to 7
69
CKV
Pin No.
Pin name
82
QSYNC
Pin No.
Pin name
68
AGCPWM
Pin No.
Pin name
Viterbi clock output
65
VCK
Viterbi decoded data output
64
VDT
Clock error output
(for clock recovery by VCXO)
Recovered symbol clock output
(switchable to sampling clock output)
3. Carrier Recovery
Function
Carrier lock flag (H: lock)
4. AGC
Function
AGC control data (PWM output)
See reference circuit (4)
5. Viterbi Decoder
Function
These pins can be fixed to ground by setting CPU I/F register 0E (hex).
6. Frame Synchronization
Function
Frame synchronization flag (H: sync)
– 11 –
Pin No.
Pin name
83
FSYNC
CXD1961AQ
7. Reed-Solomon Decoder/Data output
Function
Pin No.
Pin name
Data output clock
(parallel mode) Byte clock
(Serial mode) Viterbi clock
27
BYTCLK
Packet clock (H: data, L: parity)
26
PKTCLK
Uncorrectable packet flag
28
PKTERR
Data output
(Parallel mode) LSB data
(Serial mode) serial data (MSB first)
29
DATA0
Data output
(Parallel mode) DATA7 = MSB
(Serial mode) Hi-Z
30 to 33 DATA1 to 4
36 to 38 DATA5 to 7
Output mode (Serial or Parallel) is switched by setting CPU I/F register 0F (hex).
8. CPU Interface
Function
Pin No.
Pin name
I2C bus serial clock input
58
SCL
I2C
59
SDA
Pin No.
Pin name
22
RESET
Pin No.
Pin name
bus serial data in out
9. Reset
Function
Reset (L: reset/fix H for normal use)
10. Power Supply
Function
Digital power supply (+3.3V)
10, 15, 24,
34, 44, 53, VDD0 to 9
66, 74, 80
Digital ground
11, 16, 25,
35, 45, 54, VSS0 to 9
67, 75, 81
Apply 0.1µF capacitor to every power supply terminal.
– 12 –
CXD1961AQ
11. Test / Others
Function
Pin No.
Pin name
Test mode enable (Fix L for normal use)
23
TE
Test clock (Fix H for normal use)
17
TCK
Test mode Control (Fix H for normal use)
18
TMS
5 to 8, 20 TEST1 to 4, TEST7
49 to 52
TEST16 to 19
55 to 57
TEST20 to 22
Test input (Fix L)
Test output (connect nothing)
19
TEST6
39 to 43
46 to 48
TEST8 to 12
TEST13 to 15
Tuner interface
(3 wire mode) Serial data output
(I2C bus mode) Serial clock output
12
SDAT/SCL
Tuner interface (3 wire) Clock output
13
SCLK
Tuner interface
(3 wire mode) Latch enable output
(I2C bus mode) Serial data in out
14
SEN/SDA
Clock output (crystal frequency/8)
21
CK8OUT
No Connection
9
NC
Test in out (Fix L)
– 13 –
CXD1961AQ
Electrical Characteristics
(Ta = 0 to 75°C, VDD = 3.3V)
Description
Symbol
Min.
Typ.
Max.
Unit
30
MSPS
20
Symbol rate
Rs
Crystal Frequency
Fxtal
DATA0 to 7 – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
tDB0
75
ns
PKTCLK – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
tPB0
75
ns
PKTERR – BYTCLK falling edge
(Parallel output mode PBYCK = 0)
tEB0
75
ns
DATA0 to 7 – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
tDB1
75
ns
PKTCLK – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
tPB1
75
ns
PKTERR – BYTCLK rising edge
(Parallel output mode PBYCK = 1)
tEB1
75
ns
Serial output mode cycle time
(Serial output mode)
tSOC
16
ns
DATA0 to 7 – BYTCLK hold time
(Serial output mode)
tDBH
12
ns
PKTCLK, PKTERR – BYTCLK setup time
(Serial output mode)
tPBS
6
ns
PKTCLK, PKTERR – BYTCLK hold time
(Serial output mode)
tEBH
10
ns
I2C bus Serial clock cycle time
FscI
I2C bus Data setup time
tDSI
100
ns
I2C bus Data hold time
tDHI
0
ns
32
MHz
400
Timing Waveform
(1) Parallel output mode, PBYTCK = 0
tPB0
tEB0
tPB0
PKTCLK
PKTERR
BYTCLK
DATA [0:7]
tDB0 tDB0
– 14 –
tEB0
kHz
CXD1961AQ
(2) Parallel output mode, PBYTCK = 1
tPB1
tEB1
tPB1
tEB1
PKTCLK
PKTERR
BYTCLK
DATA [0:7]
tDB1 tDB1
(3) Serial output mode (Example of R = 3/4)
tPBS
tEBH
tEBH
PKTCLK
tSOC
PKTERR
BYTCLK
DATA0
tDBH
(4) I2C Bus interface
0.6µs
tDSI
SDA
SCL
1.3µs
1.3µs
tDHI
0.6µs
– 15 –
0.6µs
CXD1961AQ
READ REGISTER
CPU Interface Registers
Sub address
(hex)
Name
MSB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit0
00
INP_LEV
INP7
INP6
INP5
INP4
INP3
INP2
INP1
INP0
01
PWM_VAL
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
02
AFC_VAL
AFC7
AFC6
AFC5
AFC4
AFC3
AFC2
AFC1
AFC0
03
QBEC_LO QBEC7
QBEC3
QBEC2
QBEC1
QBEC0
QBEC15 QBEC14 QBEC13 QBEC12 QBEC11 QBEC10 QBEC9
QBEC8
04
05
QBEC_UP VBEC7
VBEC6
QBEC5 QBEC4
VBEC5
VBEC4
VBEC3
VBEC2
VBEC1
VBEC0
VBEC15 VBEC14 VBEC13 VBEC12 VBEC11 VBEC10 VBEC9
VBEC8
06
R
07
VBEC_LO
—
RO2
RO1
RO0
QBER1
QBER0
VBER1
VBER0
08
W
OFI3
OFI2
OFI1
OFI0
OFQ3
OFQ2
OFQ1
OFQ0
NAK
—
FSYNC
—
ID
09A
VBEC_UPR VCOLK
VSYNC QSYNC
09B
CODE/BER
CM7
CM6
CM5
CM4
CM3
CM2
CM1
CM0
0A
DC_OFST
CM15
CM14
CM13
CM12
CM11
CM10
CM9
CM8
0B
FLAG
OFC7
OFC6
OFC5
OFC4
OFC3
OFC2
OFC1
OFC0
0C
CM_LOW
MQS3
MQS2
MQS1
MQS0
AK1
AK0
CE1
CE0
0D
CM_UPR
—
RATE2
RATE1
RATE0 SRSAVE
—
SRS1
SRS0
DOH1Z
DOPS
PPKER
0E
WRITE REGISTER
W
QBEC6
CAR_OFST PBYCK
PPKCK MBYCK VCKVDT SEL09
SYSSEL DFSKIP RSSKIP TUNSEL TUNEN MFSYNC AGCLP
0F
MQS/CLK
SINV
10
CODE/SRS
MAGC
PAGC
11
OUT_CNT
QTH5
QTH4
QTH3
QTH2
12
MOD_CNT
VTH4
VTH3
VTH2
13
AGC/RST
TUD17
TUD16
14
QTH
TUD27
15
VTH
MVSYNC CKVSEL QPRST
VTRST
RSRST VCORST
QTH1
QTH0
TQBEC1 TQBEC0
VTH1
VTH0
TVS2
TVS1
TVS0
TUD15
TUD14
TUD13
TUD12
TUD11
TUD10
TUD26
TUD25
TUD24
TUD23
TUD22
TUD21
TUD20
TUD37
TUD36
TUD35
TUD34
TUD33
TUD32
TUD31
TUD30
16
TUN_DAT1 TUD47
TUD46
TUD45
TUD44
TUD43
TUD42
TUD41
TUD40
17
TUN_DAT2 TUD57
TUD56
TUD55
TUD54
TUD53
TUD52
TUD51
TUD50
18
TUN_DAT3
NCO7
NCO6
NCO5
NCO4
NCO3
NCO2
NCO1
NCO0
19
TUN_DAT4 NCO15
NCO14
NCO13
NCO12
NCO11
NCO10
NCO9
NCO8
1A
TUN_DAT5 NCO23
NCO22
NCO21
NCO20
NCO19
NCO18
NCO17
NCO16
1B
SYM_RATE1 CALRST CADRST CLKRST
1C
SYM_RATE2
—
—
—
—
—
—
—
—
1D
SYM_RATE3
BSI3
BSI2
BSI1
BSI0
BSQ3
BSQ2
BSQ1
BSQ0
GAIN1
GAIN0
TCAR1
TCAR0
FLOOP TRACK FLMOD FLSTEP QTLEV1 QTLEV0
1E
CAR_RST RSTEN
—
RANGE FSYSEL FSYTHD
—
MOFST OFSTEN OFSTGN
1F
N.A.
TQS1
TQS0
20
DC_BIAS
BSC7
BSC6
BSC5
BSC4
BSC3
BSC2
BSC1
BSC0
21
CAR/DC
REF7
REF6
REF5
REF4
REF3
REF2
REF1
REF0
Input "0" to write registers which are not assigned ("—").
– 16 –
CXD1961AQ
Description of CPU Interface Registers
Sub address 00 (hex)
INP7 to INP0
(MSB) (LSB)
Sub address 01 (hex)
PWM7 to PWM0
(MSB)
(LSB)
Sub address 02 (hex)
AFC7 to AFC0
(MSB) (LSB)
AFC7: Sign
Read
INP_LEV
Input level estimation
Upper 8 bit of I2 + Q2 of analog I/Q input.
(Ex.) The value is about 40 (hex) when the analog I/Q amplitude is half the input
range.
Read
PWM_VAL
AGC PWM output value
PWM output value of AGC control.
Read
AFC_VAL
Carrier offset value
Carrier offset estimation
Carrier offset = (Symbol rate) × AFC [7:0] ÷ 512 (Hz)
Ex.) 20MSPS AFC [7:0] = 11110000 (bin)
offset = 20MHz × (–16) ÷ 512
= –625kHz
In this case, by changing tuner PLL value by -625kHz, the offset may be
cancelled.
Sub address 03 (hex)
Read
QBEC_LOW
Bit error count at QPSK output
Sub address 04 (hex)
Read
QBEC_UPR
Bit error count at QPSK output
QBEC15 to QBEC0
(MSB)
(LSB)
Bit error count at the QPSK output (16 bit).
Measuring period is set by TQBEC [1:0] of CPU I/F register 11 (hex) .
BER is the ratio of QBEC [15:0] and the measuring period.
QBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.
Sub address 05 (hex)
Read
VBEC_LOW
Bit error count at Viterbi output
Sub address 06 (hex)
Read
VBEC_UPR
Bit error count at Viterbi output
VBEC15 to VBEC0
(MSB)
(LSB)
Bit error count at the Viterbi output (16 bit).
Measuring period is 204 × 8 × 1280 = 2,088,960.
BER is the ratio of VBEC [15:0] and 2,088,960.
VBEC [15:0] is valid when QSYNC, VSYNC and FSYNC are all High.
– 17 –
CXD1961AQ
Sub address 07 (hex)
RO2 to RO0
QBER1 to QBER0
VBER1 to VBER0
Read
CODE/BER
Code rate and BER
Current punctured rate (code rate)
RO2
RO1
RO0
Code rate
0
0
1
1/2
0
1
0
2/3
0
1
1
3/4
1
0
0
4/5
1
0
1
5/6
1
1
0
6/7
1
1
1
7/8
4 level BER indicator of QPSK output.
This indicator is valid when QSYNC, VSYNC and FSYNC are all High and
TQBEC [1:0] = 10 (bin). TQBEC [1:0] is in register 11 (hex).
QBER1
QBER0
Bit Error Rate
0
0
more than 10–2
0
1
10–3 < ∗ <10–2
1
0
10–4 < ∗ <10–3
1
1
less than 10–4
4 level BER indicator of Viterbi output.
This indicator is valid when QSYNC, VSYNC and FSYNC are all High.
VBER1
VBER0
Bit Error Rate
0
0
more than 10–2
0
1
10–3 < ∗ <10–2
1
0
10–4 < ∗ <10–3
1
1
less than 10–4
– 18 –
CXD1961AQ
Sub address 08 (hex)
OFI3 to OFI0
Read
DC_OFST
DC offset level of A to D converter
DC offset value of the I channel A/D converter.
OFI3: Sign
OFQ3 to OFQ0
OFQ3: Sign
DC offset value of the Q channel A/D converter.
In both cases, the value is depend on the operation mode.
MOFST (reg. IE)
Operating mode
OFI [3:0] / OFQ [3:0]
0
Offset bias mode
Current offset value.
1
Offset cancel mode
Compensation value for each
A/D converter.
Refer to the explanation of register 1E (hex).
Sub address 09 (hex)-A
Read
FLAG
Status Flag
Register 09 (hex) has an irregular structure. Two register -A and -B are correspond to the sub-address 09
(hex). When SEL09 of the register 0E (hex) is 0, register 09 (hex)-A is selected, else register 09 (hex)-B is
selected.
VCOLK
This bit become 0 in case of abnormal oscillation of embedded VCO.
NAK
(Tuner interface I2C bus mode)
This bit becomes 1 in case of no acknowledge from the tuner PLL.
FSYNC
This bit becomes 1 iwhen Frame synchronization is achieved.
VSYNC
This bit becomes 1 when the punctured mapping synchronization is achieved.
QSYNC
This bit becomes 1 when carrier lock is achieved.
ID
This bit is always 1.
Sub address 09 (hex)-B
Read
CM_LOW
Constellation Monitor
Sub address 0A (hex)
Read
CM_UPR
Constellation Monitor
These registers can be access when SEL09 of register 0E (hex) is 1.
CM15 to CM0
(MSB) (LSB)
Monitor value of the QPSK constellation. This value depends on the AGC
reference (reg. 21 (hex)). Refer to Fig.1.
– 19 –
CXD1961AQ
Sub address 0B (hex)
OFC7 to OFC0
OFC7: Sign
Sub address 0C (hex)
Read
CAR_OFST
Carrier Capture offset value
Offset frequency at the point of carrier capture
(Latest offset frequency is output to register 02 (hex))
(offset frequency) = (Symbol rate) × OFC [7:0] ÷ 1024 (Hz)
Ex.) 20MSPS OFC [6:0] = 11110000 (bin)
(offset freq.)
= 20MHz × (–16) ÷ 1024
= –312.5kHz
Write
MQS/CLK
Qsync mode/Clock recovery
MQS3 to MQS0
(MSB) (LSB)
Threshold for carrier lock detection
AK1 to AK0
Clock recovery loop filter coefficient
00: Max. 11: min.
CE1 to CE0
Clock recovery loop filter gain
00: Min. 11: Max.
Clock recovery range is approximately ±200ppm with CE (1:0) = 11.
Sub address 0D (hex)
RATE2 to RATE0
SRSAVE
Write
CODE/SRS
Code rate select/Symbol rate select
Code rate setting
RATE2
RATE1
RATE0
Code rate R
0
0
1
1/2
0
1
0
2/3
0
1
1
3/4
1
0
0
4/5
1
0
1
5/6
1
1
0
6/7
1
1
1
7/8
By saving several NCO control word to sub registers initially, symbol rate can be
changed by setting the number of the sub register in which the desired control
word is saved. There are three sub registers.
– 20 –
CXD1961AQ
SRS1 to SRS0
(To set the symbol rate directly without the above function)
Set SRSAVE = 0, SRS [1:0] = (1,1) and set control word to registers 18, 19, 1A
(hex).
(To save control word to sub registers)
Set SRSAVE = 1 and set sub register No. ((0, 0) or (0, 1) or (1, 0)) to SRS [1:0].
Then set control word to registers 18, 19, 1A (hex).
The control word is set to both the clock recovery circuit and the selected sub
register.
(To set the symbol rate with the above function)
Set SRSAVE = 0, and set sub register No. of control word to be set. The control
word saved in the sub register is set to the clock recovery circuit.
Sub address 0E (hex)
Write
OUT_CNT
Output control and polarity
PBYCK
BYTCLK polarity
0: For falling edge 1: For rising edge
DOH1Z
1: Output Hi-Z mode (PKTCLK, BYTCLK, PKTERR, DATA [7:0])
DOPS
0: Parallel output mode 1: Serial output mode
Refer to Electric characteristics
PPKER
PKTERR polarity
0: PKTERR: H at uncorrectable packet
1: PKTERR: L at uncorrectable packet
PPKCK
PKTCLK polarity
0: PKTCLK: H at data / L at parity
1: PKTCLK: L at data / H at parity
MBYCK
1: BYTCLK mask mode
In this mode BYTCLK is forced Low during parity data output
VCKVDT
1: Viterbi decode data VDT (Pin 64) and clock VCK (Pin 65) output enable
0: VDT and VCK are fixed low.
SEL09
Read register 09 (hex)-A, -B selection
0: 09 (hex)-A is selected
1: 09 (hex)-B is selected
– 21 –
CXD1961AQ
Sub address 0F (hex)
Write
MOD_CONT
Mode Control
SINV
I/Q exchange
1: normal operation
SYSSEL
Not assigned. Input 0.
DFSK1P
1: Nyquist roll off filter bypass mode
RSSK1P
1: Reed-Solomon decoder bypass mode
TUNSEL
Tuner interface mode
TUNEN
1: Tuner interface enable
0: I2C bus mode 1: 3 wire mode
TUNSEL
TUNEN
Pin 12
Pin 13
Pin 14
mode
Don't care
0
Hi-Z
Hi-Z
Hi-Z
—
0
1
clock out
Hi-Z
data in out
I2C bus
1
1
data out
clock out
Latch Enable
3 wire
Refer to reference circuit (5).
MFSYNC
Parameter for frame synchronization protection
0: normal operation mode
1: powerful protection mode
AGCLP
AGC loop filter gain
1: normal operation
0: large gain
– 22 –
CXD1961AQ
Sub address 10 (hex)
Write
AGC/RST
AGC and Reset
MAGC
AGC mode 0: normal mode 1: bus control mode
In normal mode, PWM output is controlled so that I2 + Q2 (register 00hex) should
become approximately equal to the reference level set in register 21 (hex). In bus
control mode, data of the register 21 (hex) is directly converted to PWM output.
PAGC
AGC polarity
MVSYNC
Input 0
CKVSEL
CKV (Pin 69) output mode
0: symbol clock output
1: sampling clock output
QPRST
1: QPSK block reset (set 0 for normal operation)
To reset QPSK block, set this bit to 1 and then set this bit to 0 again.
VTRST
1: Viterbi block reset (set 0 for normal operation)
Reset operation is same as QPRST.
RSRST
1: Deinterleaver and Reed-solomon block reset (set 0 for normal operation)
Reset operation is same as QPRST.
VCORST
1: NCO block reset (set 0 for normal operation)
Reset operation is same as QPRST.
0: For tuner whose gain increases by higher AGC control voltage
1: For tuner whose gain increases by lower AGC control voltage
Select mode according to tuner AGC type.
– 23 –
CXD1961AQ
Sub address 11 (hex)
Write
QTH
Qsync Threshold and QBEC period
QTH5 to QTH0
(MSB) (LSB)
Threshold for carrier lock detection
These parameters relate to QTLEV [1:0] in register 1F (hex) and
AGC reference 21 (hex).
Ex.) QTLEV [1:0] = 01 AGC ref = 32 (hex)
QTH [5:0] = 101000
TQBEC1 to TQBEC0
Count period of QPSK bit error count
TQBEC1 TQBEC0
Count period
0
0
28
0
1
216
1
0
219
1
1
223
Select TQBEC [1:0] = 10 to use QPSK BER indicator (register 07 (hex))
Sub address 12 (hex)
Write
VTH
Viterbi sync threshold and period
VTH4 to VTH0
Threshold for punctured mapping synchronization
11110: Min. 00000: Max.
TVS2 to TVS0
Detection period for punctured mapping synchronization
110: Min 000: Max.
code rate
VTH4 to VTH0, TVS2 to TVS0
1/2
8B (hex)
2/3
BB (hex)
3/4
CB (hex)
4/5
D3 (hex)
5/6
DB (hex)
6/7
E3 (hex)
7/8
E3 (hex)
– 24 –
CXD1961AQ
Sub address 13 (hex)
Write
TUN_DAT1
Tuner control data
Sub address 14 (hex)
Write
TUN_DAT2
Tuner control data
Sub address 15 (hex)
Write
TUN_DAT3
Tuner control data
Sub address 16 (hex)
Write
TUN_DAT4
Tuner control data
Sub address 17 (hex)
Write
TUN_DAT5
Tuner control data
(I2C bus mode)
Set TUNSEL = 0 and TUNEN = 1 in the register 0F (hex).
13 (hex): Tuner PLL IC slave address + 0 (write mode)
14 to 17 (hex): Write data (tuning parameter)
I2C bus starts write operation when data setting to register 17 (hex) is finished. In
case of no acknowledge from tuner PLL IC, NAK in the register 09 (hex)-A is set
to 1.
(3 wire mode)
Set TUNSEL = 1 and TUEN = 1 in the register 0F (hex). 28 bits data (register 13
to 15 (hex) and upper 4bit of the register 16 (hex)) are transmitted serially. To
start operation, dummy data setting to the register 17 (hex) is needed.
Refer to the reference circuit (5).
Sub address 18 (hex)
Write
SYM_RATE1
Control word for multi-rate oscillation
Sub address 19 (hex)
Write
SYM_RATE2
Control word for multi-rate oscillation
Sub address 1A (hex)
Write
SYM_RATE3
Control word for multi-rate oscillation
NCO23 to NCO0
(MSB)
(LSB)
The relation between symbol rate and the control word of the NCO is:
NCO [23:0] = (symbol rate) × 222 ÷ (crystal frequency)
Ex.) Symbol rate 20MSPS crystal 32MHz
NCO [23:0] = 20 × 106 × 222 ÷ 32 × 10–6
= 2,621,440
= 221 + 219
NCO21 = NCO19 = 1, other = 0
– 25 –
CXD1961AQ
Sub address 1B (hex)
Write
CAR_RST
Carrier loop reset
CARRST
1: Carrier loop filter reset
Reset operation is same as QPRST (register 10hex)
CADRST
1: Carrier recovery frequency loop reset
Reset operation is same as QPRST (register 10hex)
CLKRST
1: Clock recovery loop reset
Reset operation is same as QPRST (register 10hex)
RANGE
Carrier capture range
FSYSEL
Frame synchronization detector mode 0: Hard decision
1: Soft decision
FSYTHD
Frame synchronization threshold
Sub address 1C (hex)
Write
0: Carrier capture range = ±Rs/8
1: Carrier capture range = ±Rs/16
N.A.
0: Low
1: High
Not Assigned
Input 0 to all bits.
Sub address 1D (hex)
Write
DC_BIAS
A/D Converter DC_BIAS
DC offset is added to the output of the A/D converter when MOFST in the
register 1E (hex) is 0.
BSI3 to BSI0
DC offset for I channel A/D converter. BSI3: sign
Offset range is from –8 to +7.
BSQ3 to BSQ0
DC offset for Q channel A/D converter. BSI3: sign
Offset range is from –8 to +7.
– 26 –
CXD1961AQ
Sub address 1E (hex)
Write
CAR/DC
Carrier recovery and DC offset
RSTEN
1:Carrier loop filter reset enable (Set to 1 for normal operation)
GAIN1 to GAIN0
Gain setting for carrier recovery loop
GAIN1
GAIN0
Gain
0
0
×1
0
1
×2
1
0
×4
1
1
×8
(default ×1)
TCAR1 to TCAR0
Mode setting for carrier recovery frequency loop: default TCAR [1:0] = 10.
MOFST
1: A/D converter DC offset cancellation mode
0: A/D converter DC offset addition mode
OFSTEN
1: A/D converter DC offset control (cancel or add) enable
0: A/D converter DC offset control (cancel or add) disable
OFSTGN
A/D converter DC offset cancellation loop filter gain
1: ×1
0: ×1/2
– 27 –
CXD1961AQ
Sub address 1F (hex)
Write
CAR_MODE
Carrier recovery mode
TQS1 to TQS0
Carrier lock detection period 00: min. 11: max.
Default is TQS [1:0] = 10
FLOOP
0: Carrier recovery by phase loop
1: Carrier recovery by phase and frequency loop (default)
TRACK
default: 0
FLMOD
1: Carrier offset frequency is set by BSC [6:0].
0: Carrier offset frequency is set by the internal loop. (default)
FLSTEP
default: 1
QTLEV1 to QTLEV0
Gain for carrier lock detection circuit.
Default is QTLEV [1:0] = 00
Sub address 20 (hex)
BSC7 to BSC0
BSC7: sign
Write
CAR_BIAS
Carrier frequency offset bias
Carrier offset frequency setting
This mode is good when FLMOD = 1.
(Carrier offset) = (Symbol rate) × BSC [7:0] ÷ 1024 (Hz)
Sub address 21 (hex)
AGCR7 to AGCR0
Write
AGC_REF
AGC reference
Input level reference for AGC operation
Refer to the explanation of register 10 (hex)
– 28 –
CXD1961AQ
Application Circuit
(1) A/D Converter
390Ω
390Ω
96
95
94
Connect AVD0
and AVD1 to analog
+3.3V supply
93
RT1
97
1kΩ
AVD1
98
0.1µF
QIN
99
0.1µF
AVS1
100
RB1
0.1µF
1kΩ
390Ω
RT0
1kΩ
0.1µF
AVD0
Baseband
I input
0.1µF
0.1µF
0.1µF
IIN
Baseband
Q input
Analog
VSS
1kΩ
1
390Ω
AVS0
CXD1961AQ
0.1µF
Analog
VSS
2
RB0
(2) Clock Recovery circuit
15kΩ
Analog
VSS
Connect AVD2
and AVD4 to analog
+3.3V supply
4.7µF
2.2µF
100kΩ
22Ω
0.1µF
0.1µF
10kΩ
Analog
VSS
88
AVS2
OPOUT
OPXIN
VCOC
87
86
85
84
AVD4
89
AVS4
90
CPOUT
91
AVD2
92
VCOEN
1kΩ
CXD1961AQ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 29 –
CXD1961AQ
(3) Crystal
Crystal
Crystal
Daishinku AT-49
32.0MHz
XI 63
470kΩ
XO 62
Connect AVD3 to ditital +3.3V supply
7pF
7pF
AVS3 61
Digital
VSS
AVD3 60
0.1µF
CXD1961AQ
(4) AGC
This is an example of how to set AGC control
voltage from 0 to 5V.
Power supply for the OP-Amp is 7V.
20kΩ
OP-Amp
AGCPWM 68
To tuner AGC input
5.6kΩ
0.1µF
10kΩ
CXD1961AQ
Analog
VSS
(5) Tuner Interface
(3 wire type) suitable for GEC Plessey SP5658
100Ω
ENABLE
12
SDAT/SCL
13
SCLK
100Ω
DATA
100Ω
CLOCK
14 SEN/SDA
CXD1961AQ
SP5658
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 30 –
CXD1961AQ
(5) Tuner Interface
(I2C bus type) suitable to GEC Plessey SP5659 etc. (4 bytes of data can be written)
+3.3V
10kΩ
10kΩ
100Ω
SDA
12 SDAT/SCL
100Ω
13 SCLK
SCL
14 SEN/SDA
CXD1961AQ
SP5659
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 31 –
CXD1961AQ
Appendix
Fig.1 Constellation monitor output vs. C/N
Constellation monitor output
104
103
4
6
8
10
12
14
16
18
20
C/N [dB]
This figure is an example when AGCREF is set to 32 (hex).
The monitor output value is proportional to AGCREF.
Monitor output : CM [15:0] CPU I/F register 09-B (hex) and 0A (hex)
– 32 –
22
24
26
28
CXD1961AQ
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.24
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 33 –