STV160NF03L N - CHANNEL 30V - 0.0019Ω - 160A PowerSO-10 STripFET MOSFET TYPE STV160NF03L ■ ■ ■ ■ ■ ■ ■ V DSS R DS(on ) ID 30 V < 0.0028 Ω 160 A TYPICAL RDS(on) = 0.0019 Ω ULTRA LOW ON-RESISTANCE ULTRA FAST SWITCHING 100% AVALANCHE TESTED VERY LOW GATE CHARGE LOW THRESHOLD DRIVE LOW PROFILE, VERY LOW PARASITIC INDUCTANCE PowerSO-10 PACKAGE 10 1 PowerSO-10 INTERNAL SCHEMATIC DIAGRAM DESCRIPTION The STV160NF03L represents the second generation of Application Specific STMicroelectronics well established STripFET process based on a very unique strip layout design. The resulting MOSFET shows unrivalled high packing density with ultra low on-resistance and superior switching charactestics. Process simplification also translates into improved manufacturing reproducibility. This device is particularly suitable for high current, low voltage switching application where efficiency is crucial. CONNECTION DIAGRAM (TOP VIEW) APPLICATIONS BUCK CONVERTERS IN HIGH PERFORMACE TELECOM AND VRMs DC-DC CONVERTERS ■ ABSOLUTE MAXIMUM RATINGS Symb ol Parameter V DS V DGR VGS Drain-source Voltage (VGS = 0) Drain- gate Voltage (R GS = 20 kΩ) Gate-source Voltage I D (* * ) ID I DM (•) Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 o C Drain Current (pulsed) P tot T st g Tj o T otal Dissipation at Tc = 25 o C Derating F actor Storage Temperature Max. Operating Junction T emperature (•) Pulse width limited by safe operating area November 1999 Value Unit 30 30 ± 20 V V V 160 113 640 A A A 160 1.07 -65 to 175 W W /o C o C 175 o C ( **) Limited only maximum junction temperature allowed by PowerSO-10 1/8 STV160NF03L THERMAL DATA R thj -case R thj -amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature F or Soldering Purpose Max Max o 0.9375 50 300 o C/W C/W o C ELECTRICAL CHARACTERISTICS (TJ = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA Min. V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Typ. Max. 30 Unit V T c = 25 oC V GS = ± 15 V 1 10 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Con ditions V GS(th) Gate Threshold Voltage V DS = V GS ID = 250 µA T c = 25 C R DS(on) Static Drain-source On Resistance ID = ID = ID = ID = ID = ID = I D(o n) On State Drain Current V GS V GS V GS V GS V GS V GS = = = = = = o 10V 8V 4.5V 10V 8V 4.5V 80 80 40 80 80 40 A A A A A A Min. Typ. Max. Unit 1 1.7 2.5 V 1.9 2.0 4.0 2.8 3.8 6.7 6.4 7.8 12.8 mΩ mΩ mΩ mΩ mΩ mΩ o T j = 175 C Tj = 175 oC o Tj = 175 C 160 V DS > ID(o n) x R DS(on )ma x V GS = 10 V A DYNAMIC Symbo l g f s (∗) Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Gate resistance V DS = 15 V f = 1 MHz C iss C os s C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 15 V f = 1 MHz C iss C os s C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 0 V Rg 2/8 Parameter f = 1 MHz I D = 80 A Min. Typ. Max. Unit 210 S V GS = 0 0.9 Ω V GS = 0 4900 2950 565 pF pF pF 7200 13000 4220 pF pF pF V GS = 0 STV160NF03L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 15 V I D = 40 A R G = 4.7 Ω V GS = 10 V (Resistive Load, see fig. 3) 23 350 ns ns Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 16 V 103 38 9 nC nC nC I D = 160 A V GS = 10 V SWITCHING OFF Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 15 V I D = 40 A V GS = 10 V R G =4.7 Ω (Resistive Load, see fig. 3) 105 120 ns ns t d(of f) tr (Voff) tf tc Turn-off Delay T ime Off-voltage Rise T ime Fall T ime Cross-over Time V clamp = 16 V I D = 80 A V GS = 10 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 85 46 335 404 ns ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 160 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 80 A di/dt = 100 A/µs V DD = 15 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 160 640 A A 1.5 V 100 ns 0.25 µC 5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STV160NF03L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STV160NF03L Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Basic Schematic For Motherboard VRM Whith Synchronous Rectification Basic Schematic Mosfet Switch Used In Secondary Side Of a Foward Convert 5/8 STV160NF03L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STV160NF03L PowerSO-10 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 3.35 3.65 0.132 0.144 A1 0.00 0.10 0.000 0.004 B 0.40 0.60 0.016 0.024 c 0.35 0.55 0.013 0.022 D 9.40 9.60 0.370 0.378 D1 7.40 7.60 0.291 0.300 E 9.30 9.50 0.366 0.374 E1 7.20 7.40 0.283 0.291 E2 7.20 7.60 0.283 0.300 E3 6.10 6.35 0.240 0.250 E4 5.90 6.10 0.232 e 1.27 0.240 0.050 F 1.25 1.35 0.049 0.053 H 13.80 14.40 0.543 0.567 1.80 0.047 h 0.50 L 0.002 1.20 q 1.70 α 0 0.071 0.067 o o 8 B 0.10 A B 10 = E4 = = = E1 = E3 = E2 = E = = = H 6 = = 1 5 e 0.25 B SEATING PLANE DETAIL ”A” A C M Q h D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL ”A” α 0068039-C 7/8 STV160NF03L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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