STMICROELECTRONICS STB80NF55L-06T4

STB80NF55L-06

N - CHANNEL 55V - 0.005 Ω - 80A D2PAK
STripFET POWER MOSFET
TYPE
V DSS
R DS( on )
ID
STB80NF55L-06
55 V
< 0.0065 Ω
80 A
■
■
■
■
TYPICAL RDS(on) = 0.005 Ω
LOW THRESHOLD DRIVE
LOGIC LEVEL DEVICE
ADD SUFFIX ”T4” FOR ORDERING IN TAPE
& REEL
3
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique ”Single Feature
Size” strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore
a
remarkable
manufacturing
reproducibility.
1
D2PAK
TO-263
(Suffix ”T4”)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symb ol
V DS
V DGR
VGS
Value
Unit
Drain-source Voltage (VGS = 0)
Parameter
55
V
Drain- gate Voltage (R GS = 20 kΩ)
55
V
± 20
V
80
A
Drain Current (continuous) at Tc = 100 o C
57
A
Drain Current (pulsed)
320
A
G ate-source Voltage
ID
Drain Current (continuous) at Tc = 25 oC
ID
I DM (•)
P tot
E AS ( 1 )
T st g
Tj
o
T otal Dissipation at Tc = 25 C
210
W
Derating Factor
1.4
W /o C
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
October 1999
1
J
-65 to 175
o
C
175
o
C
( 1) starting Tj = 25 oC, ID =40A , VDD = 30V
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STB80NF55L-06
THERMAL DATA
R thj -case
R thj -amb
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Maximum Lead Temperature F or Soldering Purpose
o
0.71
62.5
300
o
C/W
C/W
o
C
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
55
Unit
V
T c =125 oC
V GS = ± 20 V
1
10
µA
µA
± 100
nA
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10 V
V GS = 5 V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
Typ.
Max.
Unit
1
1.6
2.5
V
ID = 40 A
I D = 40 A
0.005 0.0065
0.0055 0.008
80
Ω
Ω
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/8
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D =18 A
V GS = 0
Min.
Typ.
Max.
Unit
20
S
7600
990
270
pF
pF
pF
STB80NF55L-06
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Delay T ime
Rise Time
V DD = 27 V
I D = 40 A
R G = 4.7 Ω
V GS = 4.5 V
(Resistive Load, see fig. 3)
75
300
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 44 V ID = 80 A V GS = 5 V
97
25
46
100
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbo l
Parameter
Test Con ditions
Min.
t d(of f)
tf
Turn-off Delay T ime
Fall T ime
V DD = 27 V
I D = 40 A
V GS = 4.5 V
R G = 4.7 Ω
(Resistive Load, see fig. 3)
210
160
ns
ns
t d(of f)
tf
tc
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Vclamp = 44 V
I D = 80 A
V GS = 4.5 V
R G = 4.7 Ω
(Induct ive Load, see fig. 5)
90
230
350
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 80 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 80 A
di/dt = 100 A/µs
T j = 150 o C
V DD = 25 V
(see test circuit, fig. 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
80
320
A
A
1.5
V
75
ns
190
nC
5.1
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
STB80NF55L-06
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STB80NF55L-06
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STB80NF55L-06
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STB80NF55L-06
TO-263 (D2PAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
A1
2.49
2.69
0.098
0.106
B
0.7
0.93
0.027
0.036
B2
1.14
1.7
0.044
0.067
C
0.45
0.6
0.017
0.023
C2
1.21
1.36
0.047
0.053
D
8.95
9.35
0.352
0.368
E
10
10.4
0.393
0.409
G
4.88
5.28
0.192
0.208
L
15
15.85
0.590
0.624
L2
1.27
1.4
0.050
0.055
L3
1.4
1.75
0.055
0.068
D
C2
A2
A
C
DETAIL”A”
DETAIL ”A”
A1
B2
E
B
G
L2
L
L3
P011P6/E
7/8
STB80NF55L-06
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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