STV7697B ® Scan Driver for Plasma Display Panels Main Features ■ 64-output PDP Scan Driver ■ 170V Absolute Maximum Rating ■ 5V Supply for Logic ■ -200/750 mA Peak Output Current ■ 1 A Source / Sink Output Diode ■ 64-bit Shift Register (8 MHz) ■ Blank Control ■ Complementary Output Control ■ BCD Technology ■ 100 Pin-TQFP Package TQFP100 (14 x 14 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7697B Description The STV7697B is a scan driver for plasma display panels (PDP) implemented in ST’s proprietary BCD (Bi-polar CMOS DMOS) technology. Using a 64-bit cascadable 8-MHz shift register, it drives 64 highcurrent and high-voltage outputs. By connecting several STV7697B devices in series, any vertical pixel definition can be performed. The STV7697B is supplied with separate 160V power output and 5 V logic supplies. All command inputs are CMOS compatible. The STV7697B package is a 100-pin TQFP. October 2003 1/18 STV7697B Table of Contents Chapter 1 1.1 Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pinout Diagrams ............................................................................................................... 3 Chapter 2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Chapter 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Absolute Maximum Ratings ................................................................................................ 9 3.2 Thermal Data ...................................................................................................................... 9 3.3 Supply Characteristics ....................................................................................................... 10 3.4 Power Output Characteristics ........................................................................................... 10 3.5 SIN and SOUT Characteristics ......................................................................................... 11 3.6 Input (CLR, CLK, STB, BLK, POL, SIN/SOUT, and F/R) Characteristics ......................... 11 3.7 AC Timing Requirements ................................................................................................... 11 3.8 AC Timing Characteristics .................................................................................................. 12 Chapter 4 Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Chapter 5 Package Mechanical Data Chapter 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2/18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 STV7697B Pin Allocation and Descriptions 1 Pin Allocation and Descriptions 1.1 Pinout Diagram VPP2 VPP2 NC* OUT64 79 78 76 77 VSSP2 NC* 80 VSSP2 F/R 84 81 SOUT 85 VSSLOG CLK 86 82 STB 87 83 BLK VCC 88 POL 90 89 91 VSSLOG 93 CLR VSSP1 94 SIN NC* VSSP1 96 92 VPP1 97 95 OUT1 VPP1 98 OUT2 99 100 Figure 1: STV7697B (TQFP100) OUT3 1 75 OUT4 2 74 OUT62 OUT5 3 73 OUT61 OUT6 4 72 OUT60 OUT7 5 71 OUT59 OUT8 6 70 OUT58 OUT9 7 69 OUT57 OUT10 8 68 OUT56 OUT11 9 67 OUT55 OUT12 10 66 OUT54 OUT13 11 65 OUT53 OUT14 12 64 OUT52 OUT15 13 63 OUT51 OUT16 14 OUT17 TQFP100 (Top View) OUT63 43 44 45 46 47 48 49 50 NC* VSSSUB VSSP2 VSSP2 NC* OUT36 OUT37 OUT38 VPP1 NC VSSP1 VPP2 OUT39 42 OUT40 51 41 52 25 VPP2 24 OUT27 40 OUT41 OUT26 OUT35 OUT42 53 39 54 23 OUT34 22 OUT25 38 OUT24 OUT32 OUT33 OUT43 37 55 36 21 35 OUT23 VPP1 OUT44 OUT31 OUT45 56 34 57 20 33 19 OUT22 32 OUT46 OUT21 31 OUT47 58 VSSP1 59 18 30 17 OUT20 VSSP1 OUT19 29 OUT48 NC* 60 28 16 OUT30 OUT18 27 OUT49 26 61 OUT29 OUT50 15 OUT28 62 *NC: Not Connected 3/18 Pin Allocation and Descriptions STV7697B Table 1: Supply Pins Pin No. Pin Name Pin Description 88 VCC 5V Logic Supply 34 VPP1 High Voltage Supply for Power Outputs 35 VPP1 High Voltage Supply for Power Outputs 41 VPP2 High Voltage Supply for Power Outputs 42 VPP2 High Voltage Supply for Power Outputs 78 VPP2 High Voltage Supply for Power Outputs 79 VPP2 High Voltage Supply for Power Outputs 97 VPP1 High Voltage Supply for Power Outputs 98 VPP1 High Voltage Supply for Power Outputs 83 VSSLOG Logic Ground 93 VSSLOG Logic Ground 30 VSSP1 Ground for Power Outputs 31 VSSP1 Ground for Power Outputs 32 VSSP1 Ground for Power Outputs 45 VSSP2 Ground for Power Outputs 46 VSSP2 Ground for Power Outputs 81 VSSP2 Ground for Power Outputs 82 VSSP2 Ground for Power Outputs 94 VSSP1 Ground for Power Outputs 95 VSSP1 Ground for Power Outputs 44 VSSSUB Substrate Ground Table 2: Shift Register and Input Pins Pin No. Pin Name 85 SOUT 86 CLK Clock for Shift Register Data 87 STB Latch for Shift Register Data (Strobe Input) 89 BLK Blanking Control for Power Outputs 90 POL Polarity Selection 91 SIN Shift Register Data Input 92 CLR Clear for Shift Register Data 84 F/R Forward/Reserve modes for selecting Shift Register 4/18 Pin Description Shift Register Data Output STV7697B Pin Allocation and Descriptions Table 3: Power Output Pins Pin No. Pin Name 99 OUT1 100 Pin Description Pin No. Pin Name Pin Description Power Output 1 38 OUT33 Power Output 33 OUT2 Power Output 2 39 OUT34 Power Output 34 1 OUT3 Power Output 3 40 OUT35 Power Output 35 2 OUT4 Power Output 4 48 OUT36 Power Output 36 3 OUT5 Power Output 5 49 OUT37 Power Output 37 4 OUT6 Power Output 6 50 OUT38 Power Output 38 5 OUT7 Power Output 7 51 OUT39 Power Output 39 6 OUT8 Power Output 8 52 OUT40 Power Output 40 7 OUT9 Power Output 9 53 OUT41 Power Output 41 8 OUT10 Power Output 10 54 OUT42 Power Output 42 9 OUT11 Power Output 11 55 OUT43 Power Output 43 10 OUT12 Power Output 12 56 OUT44 Power Output 44 11 OUT13 Power Output 13 57 OUT45 Power Output 45 12 OUT14 Power Output 14 58 OUT46 Power Output 46 13 OUT15 Power Output 15 59 OUT47 Power Output 47 14 OUT16 Power Output 16 60 OUT48 Power Output 48 15 OUT17 Power Output 17 61 OUT49 Power Output 49 16 OUT18 Power Output 18 62 OUT50 Power Output 50 17 OUT19 Power Output 19 63 OUT51 Power Output 51 18 OUT20 Power Output 20 64 OUT52 Power Output 52 19 OUT21 Power Output 21 65 OUT53 Power Output 53 20 OUT22 Power Output 22 66 OUT54 Power Output 54 21 OUT23 Power Output 23 67 OUT55 Power Output 55 22 OUT24 Power Output 24 68 OUT56 Power Output 56 23 OUT25 Power Output 25 69 OUT57 Power Output 57 24 OUT26 Power Output 26 70 OUT58 Power Output 58 25 OUT27 Power Output 27 71 OUT59 Power Output 59 26 OUT28 Power Output 28 72 OUT60 Power Output 60 27 OUT29 Power Output 29 73 OUT61 Power Output 61 28 OUT30 Power Output 30 74 OUT62 Power Output 62 36 OUT31 Power Output 31 75 OUT63 Power Output 63 37 OUT32 Power Output 32 76 OUT64 Power Output 64 5/18 Pin Allocation and Descriptions STV7697B Table 4: Miscellaneous Pins Pin No. Pin Name 29 NC Not connected 33 NC Not connected 43 NC Not connected 47 NC Not connected 77 NC Not connected 80 NC Not connected 96 NC Not connected 6/18 Pin Description STV7697B 2 Circuit Description Circuit Description Figure 2: STV7697B Block Diagram CLR CLK F/R 64-bit Shift Register SIN (SOUT) P1 S1 P64 SOUT S64 VSSSUB Latch STB Q1 Q2 Q63 Q64 VSSLOG BLK VCC POL VSSP1 VSSP2 --- --- STV7697B VSSP1 VPP1 VSSP2 VPP1 VPP2 VPP2 OUT64 OUT1 The STV7697B includes all the necessary logic and power circuits to drive the rows of electrodes of a plasma display panel (PDP). The state of the displayed line is loaded into the shift register. Data is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade several drivers to perform any vertical resolution (Table 5). Inputs CLK, STB, SIN and SOUT are Schmitt trigger inputs. Table 5: Shift Register Truth Table F/R CLK SIN SOUT Comments H Rise In Out Forward Shift H L or H In Out Steady L Rise Out In Reverse Shift L L or H Out In Steady The forward / reverse (F/R) input is used to select the direction of the shift register where data input/ output status is set according to the selected direction. In Reverse mode (F/R = low), data is input on the SOUT pin and output on the SIN pin. The maximum frequency of the shift clock is 8 MHz. The clear signal (CLR) resets the shift register data to 0 when it is pulled to a high level. Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the latch input (STB) is at low level. 7/18 Circuit Description STV7697B All the data are kept memorized in the latch stage when the strobe input (STB) is pulled high. The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the POL input signal (Table 6). Sustain current must not be sunk in the power output to VPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Table 6: Power Output Truth Table Pn* CLR STB BLK POL Driver Output X X X H H All H Forced to High X X X H L All L Forced to Low H L L L L H Copy Data L L L L L L Copy Data H L L L H L Copy Inverted Data L L L L H H Copy Inverted Data X X H L L Qn Data Latched X X H L H Qn Inverted Data Latched X H L L L L All Low X H L L H H All High Comments *Pn is the parallel output of the shift register (n = 1 to 64). Pn takes the value of serial input (SIN) after “n” shift clock periods. 8/18 STV7697B Electrical Characteristics 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Symbol Parameter Value Units VCC Logic Supply −0.3, +7 V VPP Driver Supply −0.3, +170 V VIN Logic Input Voltage −0.3, VCC +0.3 V VOUT Logic Output Voltage −0.3, VCC + 0.3 V VPOUT Driver Output Voltage (Scanning mode) −0.3, VPP V IPOUT Driver Output Current (See Note 1 and Note 3) −250, +800 mA IDOUT Diode Output Current (See Note 2 and Note 3) ±1.2 A IL Latch-up Susceptibility ±200 mA TJMAX Junction Temperature +125 °C TOPER Operating Temperature −20, +85 °C TSTG Storage Temperature −50, +150 °C Note:1. Through one power output. 2. Through one power output with VPP = VSSP (See Figure 4.) 3. These parameters are measured during ST’s internal qualification which includes temperature characterization on standard batches and on corners batches of the process. These parameters are not tested on the parts. 3.2 Thermal Data Symbol Value Units Maximum Operating Junction 125 °C RthJA Junction-ambient Thermal Resistance (See Note 1) 40 °C/W POPER Operating Power Dissipation (TOPER = 25° C) 2 W TJOPER Parameter Note:1. TQFP soldered on 4-layer printed circuit board. 9/18 Electrical Characteristics 3.3 STV7697B Supply Characteristics (VCC = 5 V, VPP = 160 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, TAMB = 25°C and fCLK = 8 MHz, unless otherwise specified) Symbol Parameter VCC Logic Supply Voltage ICCH Logic Supply Current (all inputs high) ICCL Logic Supply Current VPP Power Output Supply Voltage IPPH Power Output Supply Current (steady outputs) 3.4 Test Conditions Min. Typ. Max. Units 4.5 5 5.5 V 100 µA fCLK = 8 MHz, SIN =1010 5.8 15 mA 160 V 100 µA Max. Units Power Output Characteristics Symbol VPOUTH IPOUTH-peak VPOUTL IPOUTL-peak Parameter Test Conditions Min. Typ. 5 10 3 5 V mA Power Output High Level (voltage drop versus VPP, VPP=90V) IPOUTH = - 10 mA IPOUTH = - 40 mA Power Output Peak Current (See Note 1) VPP =130V -200 Power Output Low Level IPOUTL = 200 mA 2.6 Power Output Peak Current (See Note 2) VPOUTL = 30V VCC = 5V 650 VDOUTH1 Output Diode High Level (See Note 3 and Note 4) IDOUTH = +400 mA VDOUTL1 Output Diode Low Level (See Note 3 and Note 4) IDOUTL = - 400 mA VDOUTH2 Output Diode High Level (See Note 3) IDOUTH = +1000 mA VDOUTL2 Output Diode Low Level (See Note 3) IDOUTL = - 1000 mA 2 -2.5 -2 V mA 3 -1.3 3.5 -3.5 5 V V 5 V V Note:1. These parameters are measured during ST’s internal qualification which includes temperature characterization on standard batches and on corners batches of the process. These parameters are not tested on the parts. 2. Peak current: pulse mode 720 Hz, 200ns pulse width, VCC=5 V. 3. Compatible with power dissipation (see Figure 4: Test Configuration). 4. The typical value increases when more than one output is activated. 10/18 STV7697B 3.5 Electrical Characteristics SIN and SOUT Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Units VOH Logic Output High Level IOH = -1 mA 4.4 4.7 4.8 V VOL Logic Output Low Level IOL = 1 mA 0.05 0.1 0.25 V Input (CLR, CLK, STB, BLK, POL, SIN/SOUT, and F/R) Characteristics 3.6 Symbol Parameter Test Conditions VIH Input High Level VIL Input Low Level IIH High Level Input Current VIH = VCC IIL Low Level Input Current Pins CLR, CLK, SIN/SOUT, STB, F/R, BLK and POL VIL = 0 V 3.7 Min. Typ. Max. 0.8 VCC Units V 0.2VCC V -10 10 µA -10 10 µA AC Timing Requirements VCC = 4.5 V to 5.5 V, TAMB = -20 to +85°C, max. leading/trailing edge for input signals (tr, tf) = 10 ns Symbol tCLK Parameter Min. Typ. Max. Units Data Clock Period 125 ns tWHCLK Duration of clock (CLK) pulse at high level 30 ns tWLCLK Duration of clock (CLK) pulse at low level 30 ns tSDAT Set-up Time of data input before clock (low to high) transition 10 ns tHDAT Hold Time of data input after clock (low to high) transition 10 ns tSFR F/R Set-up time before low to high transition 100 ns tDSTB Minimum Delay to latch STB after clock (low to high) transition 10 ns tSSTB Set-up Time STB before clock (low to high) transition 10 ns tSTB Strobe STB Pulse Duration 30 ns tBLK Blanking (BLK) Pulse Duration 100 ns tPOL Polarity (POL) Pulse Duration 100 ns 11/18 Electrical Characteristics 3.8 STV7697B AC Timing Characteristics (VCC = 5V, VPP = 90V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25oC, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V and CL = 10pF, unless otherwise specified) Symbol Parameter Min. Typ. Max. Units tCLK Data Clock Period tRDAT Logical Data Output Rise Time 20 40 ns tFDAT Logical Data Output Fall Time 15 30 ns tPHL1 Delay of logic data output (high to low transition) after clock (CLK) transition 45 70 ns tPLH1 Delay of logic data output (low to high transition) after clock (CLK) transition 50 75 ns tPHL2 Delay of power output change (high to low transition) after clock (CLK) transition 135 200 ns tPLH2 Delay of power output change (low to high transition) after clock (CLK) transition 100 170 ns tPHL3 Delay of power output change (high to low transition) after Latch (STB) transition 120 190 ns tPLH3 Delay of power output change (low to high transition) after Latch (STB) transition 90 160 ns tPHL4 Delay of power output change (high to low transition) to Blank (BLK) or Polarity (POL) transition 110 180 ns tPLH4 Delay of power output change (low to high transition) to Blank (BLK) or Polarity (POL) transition 80 150 ns tROUT Power Output Rise Time (See Note 2) 40 80 ns tFOUT Power Output Fall Time (See Note 2) 130 200 ns 125 ns Note:1. See Figure 4: Test Configuration. 2. One output among 64, loading capacitor COUT = 200 pF, other outputs at low level. 12/18 STV7697B Electrical Characteristics Figure 3: AC Characteristics Waveform 13/18 Electrical Characteristics STV7697B Figure 4: Test Configuration VPP=VSSP VPP=VSSP VDOUTH IDOUTH VDOUTL VSSP VSSP Output sinking current as positive value, sourcing current as negative value. 14/18 IDOUTL STV7697B 4 Input/Output Schematic Diagrams Input/Output Schematic Diagrams Figure 5: F/R, BLK, CLR and POL Inputs Figure 7: SIN and SOUT Inputs VCC VCC SIN, SOUT F/R, BLK, CLR, POL VSSLOG VSSLOG VSSLOG VSSLOG VSSLOG Figure 6: CLK and STB Inputs Figure 8: Power Outputs VCC VPP CLK, STB OUTi VV SSLOG SSSUB VV SSLOG SSLOG VSSP 15/18 Package Mechanical Data 5 STV7697B Package Mechanical Data Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 16/18 Millimeters Min. 0.05 1.35 0.17 0.09 0.45 Typ. 1.40 0.22 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 Inches Max. Min. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.75 0.018 0° (Min.), 7° (Max.) Typ. 0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 STV7697B 6 Revision History Revision History Table 7: Summary of Modifications Version Date Description 0.1 2 August 2002 First issue. 0.2 23 Sept. 2002 Modification of Pinout description. 0.3 20 March 2003 Modification of Pinouts. Update of Figure 2: STV7697B Block Diagram, Figure 3: AC Characteristics Waveform, Figure 5: F/R, BLK, CLR and POL Inputs, Figure 7: SIN and SOUT Inputs and Figure 8: Power Outputs. Update of Electrical Characteristic values. 0.4 18 June 2003 0.5 05 August 2003 0.6 10 September 2003 Updated parameter values in Power Output Characteristics on page 10 and AC Timing Characteristics on page 12. 0.7 23 September 2003 Updated and corrected data in Section 3.5, Section 3.6, Section 3.7 and Section 3.8. Datasheet status changed to “Preliminary Data”. Removed all references to STV7697BD package. Changed value of IDOUT to 1.2 A. Included values for tPHL3, tPLH3, tPHL4 and tPLH4. Updated Figure 7 and Figure 8. 17/18 Revision History STV7697B Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 18/18