STV8164 ® +5 V, +5 V and Adjustable Triple-Voltage Regulator with Disable and Reset Functions FEATURES ■ Input Voltage range between 7V and 18V, limited to VOUT + 6.5V ■ Maximum Available Output Currents greater than 0.8 A ■ Fixed Precision Output 1 voltage of 5 V ± 2% (at 10 mA) ■ Fixed Precision Output 2 voltage of 5 V ± 2% (at 10 mA) ■ Programmable Output 3 voltage: 2.5 to 16 V ± 2% ■ Output 1 with Reset facility ■ Outputs 2 and 3 can be disabled by digital input ■ Short Circuit Protection on each output ■ Thermal Protection ■ Low Dropout Voltages Clipwatt11 (Plastic Package) DESCRIPTION The STV8164 is a monolithic triple positive voltage regulator designed to provide two fixed precision output voltages of 5 V and an adjustable voltage for currents up to 0.6 A. The adjustable value of the third output can be fixed from 2.5 V to 16 V. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Order Code: STV8164 Short-circuit and thermal protections are included in all versions. Outputs 2 and 3 can be disabled by a digital input. 11 10 9 8 7 6 5 4 3 2 1 September 2003 PROGRAM DISABLE INPUT3 OUTPUT3 INPUT2 GROUND OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET 1/11 STV8164 TABLE OF CONTENTS Chapter 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Chapter 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Absolute Maximum Ratings ................................................................................................ 4 2.2 Thermal Data ...................................................................................................................... 4 2.3 Electrical Characteristics ...................................................................................................... 4 Chapter 3 3.1 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Currents versus Maximum Power Limitation ........................................................................ 6 Chapter 4 APPLICATION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Chapter 5 PACKAGE MECHANICAL DATA Chapter 6 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 STV8164 1 GENERAL INFORMATION GENERAL INFORMATION Figure 1: STV8164 Block Diagram DELAY CAPACITOR 2 1 RESET 3 OUTPUT1 5 OUTPUT2 8 OUTPUT3 11 PROGRAM Reference INPUT1 4 Regulator 1 Protections INPUT2 7 INPUT3 9 Regulator 2 Regulator 3 DISABLE 10 6 GROUND 3/11 ELECTRICAL CHARACTERISTICS STV8164 2 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings Symbol Parameter Value Unit VIN DC Input Voltage at pins INPUT1, INPUT2 and INPUT3 20 V VDIS Disable Input Voltage at pin DISABLE 20 V VRST Output Voltage at pin RESET 20 V IOUTPUT Pt Output Currents Internally Limited Power Dissipation Internally Limited TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 0 to +150 °C Value Unit 3 °C/W 2.2 Thermal Data Symbol Parameter RthJC Thermal Resistance (Junction-to-Case) RthJA Thermal Resistance (Junction-to-Ambient) ≥101 °C/W Maximum Recommended Junction Temperature 140 °C 0 to +70 °C TJ TOPER Operating Free Air Temperature Range 1. Depending on heat sink conditions. 2.3 Electrical Characteristics TAMB = 25° C, VIN1 = 7 V, VIN2 = 7 V and VIN3 = 10 V, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit VOUT1 Output Voltage IOUT1 = 10 mA 4.90 5.00 5.10 V VOUT2 Output Voltage IOUT2 = 10 mA 4.90 5.00 5.10 V VOUT3 Output Voltage IOUT3 = 10 mA 2.5 16 V VOUT1 Output Voltage 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 4.80 5.20 V VOUT2 Output Voltage 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 4.80 5.20 V VIO1 Dropout Voltage IOUT1 = 0.6 A 1 1.4 V VIO2 Dropout Voltage IOUT2 = 0.6 A 1 1.4 V VIO3 Dropout Voltage IOUT3 = 0.6 A 1 1.4 V 4/11 STV8164 Symbol ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min. Typ. Max. Unit VOUT1LI Line Regulation 7 V < VIN2 < 12 V, IOUT2 = 200 mA 50 mV VOUT2LI Line Regulation 7 V < VIN2 < 12 V, IOUT2 = 200 mA 50 mV VOUT3LI Line Regulation 10 V < VIN3 < 15 V, IOUT3 = 200 mA, VOUT3 = 8 V 80 mV VOUT1LO Load Regulation 5 mA < IO1 < 600 mA 100 mV VOUT2LO Load Regulation 5 mA < IOUT2 < 600 mA 100 mV VOUT3LO Load Regulation 5 mA < IOUT3 < 600 mA, VOUT3 = 8 V 160 mV Quiescent Current IOUT1 = 10 mA Outputs 2 and 3 disabled 2.2 3.0 mA Reset Threshold Voltage K = VOUT1 K-0.4 K-0.25 K-0.10 V Reset Threshold Hysteresis See circuit description. 30 75 120 mV tRD Reset Pulse Delay CE = 100 nF See circuit description. VRL Saturation Voltage in Reset Condition IRESET = 5 mA 0.4 V IRH Leakage Current in Normal Condition, at RESET pin VRESET = 10 V 10 µA IQ VO1RST VRTH 25 ms TJ = 0 to 125°C KOUT1 KOUT2 KOUT3 Output Voltage Thermal Drift ∆V OUT ⋅ 10 K OUT = -------------------------------∆T ⋅ V OUT IOUT1SC Short Circuit Output Current VIN1 = 7 V 0.8 1.3 1.8 A IOUT2SC Short Circuit Output Current VIN2 = 7 V 0.8 1.3 1.8 A IOUT3SC Short Circuit Output Current VIN3 = VOUT3 + 2V 0.8 1.3 1.8 A VPROG Input Voltage at PROGRAM pin IPROG Input Current at PROGRAM pin VDISH Voltage High Level at DISABLE pin (Outputs 2 and 3 active) VDISL Voltage Low Level at DISABLE pin (Outputs 2 and 3 disabled) 6 100 ppm/°C 2 V 5 2 µA V 0.8 V 2 µA IDIS Bias Current at DISABLE pin TJSD Junction Temperature for Thermal Shutdown 150 °C TSDH Thermal Shutdown Temperature Hysteresis 15 °C 0 V < VDISABLE < 7 V -100 5/11 CIRCUIT DESCRIPTION 3 STV8164 CIRCUIT DESCRIPTION The STV8164 is a triple-voltage regulator with Reset and Disable functions. The three regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second and third regulators will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.0 V. The adjustable voltage of pin OUTPUT3 is defined by output bridge resistors (R1 and R2). The values of these resistors are calculated to obtain, with the targeted value for pin OUTPUT3, the VPROG voltage (2.0 V) on the median point connected to pin PROGRAM. IMPORTANT: In all applications, all three inputs must be polarized. If Outputs 2 or 3 are not used, the corresponding inputs must be connected to Input 1. The Disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1-0.25 V (4.75 V Typ.), the "a" comparator (Figure 2) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VOUT1-0.175 V (4.825 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 3. C e × 2.5V t R D = -------------------------10µA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). 3.1 Currents versus Maximum Power Limitation The currents provided by the three outputs can reach 1.6 A. However, the power dissipation in the STV8164 must be established so as not to activate the automatic thermal shutdown (TJ = 150° C). It is recommended not to have all three currents at their maximum value simultaneously. For example, if TAMB(MAX.) = 70° C, the maximum power dissipation in the STV8164 will be (with RthJA = 12 °C/W): 140°C – 70° C ----------------------------------- = 5.8W 12°C ⁄ W This means that the following conditions apply to input voltages and currents: (VIN1 - 5 V) x IIO1 + (VIN2 - 5 V) x IIO2 + (VIN3 - VOUT3) x IIO3 < 5.8 W 6/11 STV8164 CIRCUIT DESCRIPTION Figure 2: Reset Diagram 10 µA VREF 3 OUTPUT1 + a - - b 1 RESET + 2 REG Ce VREF 0.6V VREF = 2.5 V Figure 3: Internal Reset Voltage VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 Power On tRD tRD Power Off 7/11 APPLICATION DIAGRAM 4 STV8164 APPLICATION DIAGRAM Figure 4: STV8164 Typical Application C1 to C6 = 10 µF Ce 1 RESET 0.1 µF 2 DELAY CAPACITOR R1 + R2 V O3 = V PROG × ---------------------R1 VPROG = 2.0 V VIN1 4 INPUT1 OUTPUT1 3 VOUT1 VIN2 7 INPUT2 OUTPUT2 5 VOUT2 VIN3 9 INPUT3 OUTPUT3 8 VOUT3 C1 C2 C3 GROUND DISABLE PROGRAM 11 6 10 C4 C5 C6 R2 R1 8/11 STV8164 5 PACKAGE MECHANICAL DATA PACKAGE MECHANICAL DATA Figure 5: 11-Pin Plastic Clipwatt Package H3 C A D L B L1 L2 H1 E G F G1 M1 M mm Inches Dim. Min. Typ. Max. Min. Typ. Max. A 3.20 0.126 B 1.05 0.041 C 0.15 D 0.006 1.50 E 0.49 F 0.80 G 1.57 0.059 0.55 1.70 0.019 0.91 0.031 1.83 0.062 0.002 0.036 0.067 H1 12.00 0.480 H2 18.60 0.732 H3 19.85 L L2 0.781 17.90 L1 0.700 14.45 10.70 0.072 11.00 0.569 11.20 0.421 0.433 L3 5.50 0.217 M 2.54 0.100 M1 2.54 0.441 0.100 Number of Pins N 11 9/11 REVISION HISTORY 6 STV8164 REVISION HISTORY Revision Main Changes Date 1.0 First Edition 1.1 New edition. Pin name changed from DISABLE to DISABLE. Reset Threshold values updated. Update of Quiescent Current value in Chapter 2.3: Electrical Characteristics on page 4. 8 January 2002 1.2 Update of reset voltage characteristics. Update of IQ and VO1RST values in Chapter 2.3: Electrical Characteristics on page 4. 31 January 2002 1.3 Modification of Short Circuit Output Current values in Section 2.3: Electrical Characteristics. 21 May 2002 1.4 Output voltages and current further specified on Title page 12 June 2002 10/11 20 June 2001 STV8164 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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