INFINEON TLE42754G

Data Sheet, Rev. 1.0, May 2008
TLE42754
L o w D r o p o u t Li n e a r F i x e d Vo l t a g e R e g u l a t o r
Automotive Power
Low Dropout Linear Fixed Voltage Regulator
1
TLE42754
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Voltage 5 V ± 2%
Ouput Current up to 450 mA
Very low Current Consumption
Power-on and Undervoltage Reset with Programmable Delay Time
Reset Low Down to VQ = 1 V
Very Low Dropout Voltage
Output Current Limitation
Reverse Polarity Protection
Overtemperature Protection
Suitable for Use in Automotive Electronics
Wide Temperature Range from -40 °C up to 150 °C
Input Voltage Range from -42 V to 45 V
Green Product (RoHS compliant)
AEC Qualified
PG-TO252-5
Description
The TLE42754 is a monolithic integrated low-dropout voltage
regulator in a 5-pin TO-package, especially designed for automotive
applications. An input voltage up to 42 V is regulated to an output
voltage of 5.0 V. The component is able to drive loads up to
450 mA. It is short-circuit proof by the implemented current limitation
and has an integrated overtemperature shutdown. A reset signal is
generated for an output voltage VQ,rt of typically 4.65 V. The power-on
reset delay time can be programmed by the external delay capacitor.
PG-TO263-5
Dimensioning Information on External Components
An input capacitor CI is recommended for compensation of line
influences. An output capacitor CQ is necessary for the stability of the
control loop.
Type
Package
Marking
TLE42754D
PG-TO252-5
TLE42754D
TLE42754G
PG-TO263-5
TLE42754G
Data Sheet
2
Rev. 1.0, 2008-05-29
TLE42754
Overview
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
•
•
•
Overload
Overtemperature
Reverse polarity
Data Sheet
3
Rev. 1.0, 2008-05-29
TLE42754
Block Diagram
2
Block Diagram
TLE42754
I
Protection
Circuits
Reset
Generator
Bandgap
Reference
GND
Figure 1
Data Sheet
Q
RO
D
Block Diagram
4
Rev. 1.0, 2008-05-29
TLE42754
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLE42754D (PG-TO252-5) and TLE42754G (PG-TO263-5)
P-TO252-5 (D-PAK)
P-TO263-5 (D²-PAK)
GND
1
5
Ι RO
Ι
D Q
AEP02580
GND Q
D
RO
IEP02528
Figure 2
Pin Configuration (top view)
3.2
Pin Definitions and Functions TLE42754D (PG-TO252-5) and TLE42754G (PGTO263-5)
Pin
Symbol
Function
1
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2
RO
Reset Output
open collector output; external pull-up resistor to a positive potential required;
leave open if the reset function is not needed
3
GND
TLE42754G (PG-TO263-5) only: Ground
internally connected to tab
4
D
Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 7
TAB
GND
Ground
connect to heatsink area
Data Sheet
5
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Conditions
Input
4.1.1
Voltage
VI
-42
45
V
–
Voltage
VQ
-0.3
7
V
–
VRO
-0.3
25
V
–
VD
-0.3
7
V
–
Tj
Tstg
-40
150
°C
–
-50
150
°C
–
VESD,HBM
-2
2
kV
Human Body
Model (HBM)2)
VESD,CDM
-500
500
V
Charge Device
Model (CDM)3)
-750
750
V
Charge Device
Model (CDM)3) at
corner pins
Output
4.1.2
Reset Output
4.1.3
Voltage
Reset Delay
4.1.4
Voltage
Temperature
4.1.5
Junction Temperature
4.1.6
Storage Temperature
ESD Absorption
4.1.7
ESD Absorption
4.1.8
4.1.9
1) Not subject to production test, specified by design.
2) ESD HBM Test according JEDEC JESD22-A114
3) ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
6
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4.2
Pos.
Functional Range
Parameter
4.2.1
Input Voltage
4.2.2
Output Capacitor’s Requirements
for Stability
4.2.3
Junction Temperature
Symbol
VI
CQ
ESR(CQ)
Tj
Limit Values
Unit
Conditions
Min.
Max.
5.5
42
V
–
22
–
µF
–1)
–
3
Ω
–2)
-40
150
°C
–
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
7
Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Value
Min.
Typ.
Unit
Conditions
Max.
TLE42754D (PG-TO252-5)
4.3.4
Junction to Case1)
RthJC
RthJA
–
3.7
–
K/W
–
–
27
–
K/W
2)
4.3.6
–
110
–
K/W
footprint only3)
4.3.7
–
57
–
K/W
300 mm2 heatsink area
on PCB3)
4.3.8
–
42
–
K/W
600 mm2 heatsink area
on PCB3)
–
3.7
–
K/W
–
–
27
–
K/W
2)
4.3.11
–
70
–
K/W
footprint only3)
4.3.12
–
42
–
K/W
300 mm2 heatsink area
on PCB3)
4.3.13
–
33
–
K/W
600 mm2 heatsink area
on PCB3)
4.3.5
Junction to Ambient
1)
TLE42754G (PG-TO263-5)
4.3.9
4.3.10
Junction to Case1)
1)
Junction to Ambient
RthJC
RthJA
1) not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
8
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” on Page 7 have to be maintained. For details see also the typical performance graph “Output Capacitor
Series Resistor ESR(CQ) versus Output Current IQ” on Page 12. As the output capacitor also has to buffer
load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the
component’s terminals.
A protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown
in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at input voltages above VI = 28 V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
The TLE42754 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal
protection circuit is not operating during reverse polarity conditions.
Supply
II
I
Q
Regulated
Output Voltage
IQ
Saturation Control
Current Limitation
C
CI
Temperature
Shutdown
BlockDiagram_VoltageRegulator.vsd
Figure 3
Data Sheet
Bandgap
Reference
ESR
}
CQ
LOAD
GND
Voltage Regulator
9
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.1.1
Output Voltage
VQ
4.9
5.0
5.1
V
1 mA < IQ < 450 mA
9 V < VI < 28 V
5.1.2
Output Voltage
VQ
4.9
5.0
5.1
V
1 mA < IQ < 400 mA
6 V < VI < 28 V
5.1.3
Output Voltage
VQ
4.9
5.0
5.1
V
1 mA < IQ < 200 mA
6 V < VI < 40 V
5.1.4
Output Current Limitation
5.1.5
Load Regulation
steady-state
IQ,max
∆VQ,load
450
–
1100
mA
-30
-15
–
mV
VQ = 4.8V
IQ = 5 mA to
400 mA
5.1.6
Line Regulation
steady-state
∆VQ,line
–
5
15
mV
5.1.7
Dropout Voltage1)
Vdr
–
250
500
mV
Vdr = VI - VQ
VI = 8 V
VI = 8 V to 32 V
IQ = 5 mA
IQ = 300 mA
5.1.8
Power Supply Ripple Rejection2)
PSRR
–
60
–
dB
fripple = 100 Hz
Vripple = 0.5 Vpp
5.1.9
Temperature Output Voltage Drift
dVQ/dT
–
0.5
–
mV/K
–
5.1.10
Overtemperature Shutdown
Threshold
Tj,sd
151
–
200
°C
Tj increasing2)
5.1.11
Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh
–
20
–
°C
Tj decreasing2)
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
2) not subject to production test, specified by design
Data Sheet
10
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Typical Performance Characteristics Voltage Regulator
Output Voltage VQ versus
Junction Temperature Tj
Output Current IQ versus
Input Voltage VI
01_VQ_T J.VSD
5,20
02_IQ_VI.VSD
1000
T j = -40 °C
900
5,10
800
T j = 150 °C
700
IQ,max [mA]
5,00
V Q [V]
T j = 25 °C
4,90
V I = 13.5 V
I Q = 50 mA
4,80
600
500
400
300
200
4,70
100
4,60
0
-40
0
40
80
120
160
0
10
Power Supply Ripple Rejection PSRR versus
ripple frequency fr)
T j = 25 °C
T j = 150 °C
7
∆V Q [mV]
PSRR [dB]
6
60
50
40
20
10
0
0,01
I Q = 10 mA
C Q = 22 µF
5
T j = 25 °C
4
3
T j = -40 °C
ceramic
V I = 13.5 V
V ripple = 0.5 Vpp
2
1
0
0,1
1
10
100
1000
0
f [kHz]
Data Sheet
T j = 150 °C
8
70
30
50
04_DVQ_DVI.VSD
9
T j = -40 °C
80
40
Line Regulation ∆VQ,line versus
Input Voltage Change ∆VI)
03_PSRR_FR.VSD
90
30
V I [V]
T j [°C]
100
20
10
20
30
40
V I [V]
11
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Load Regulation ∆VQ,load versus
Output Current Change ∆IQ
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
05_DVQ_DIQ.VSD
0
VI = 8 V
-5
C Q = 22 µF
T j = -40..150 °C
100
ESR(C Q) [Ω ]
T j = -40 °C
∆V Q [mV]
06_ESR_IQ.VSD
1000
T j = 25 °C
-10
T j = 150 °C
-15
10
0,1
-25
0,01
100
200
300
400
Stable
Region
0
500
I Q [mA]
V I = 6..28 V
1
-20
0
Unstable
Region
100
200
300
400
500
I Q [mA]
Dropout Voltage Vdr versus
Junction Temperature Tj
07_VDR_TJ.VSD
500
I Q = 400 mA
450
400
I Q = 300 mA
V DR[mV]
350
300
250
200
I Q = 100 mA
150
100
I Q = 10 mA
50
0
-40
0
40
80
120
160
T j [°C]
Data Sheet
12
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.2
Current Consumption
Electrical Characteristics Current Consumption
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
–
150
200
Unit
Conditions
5.2.1
Current Consumption
Iq = II - IQ
Iq
µA
5.2.2
–
150
220
µA
5.2.3
5.2.4
–
–
5
15
10
25
mA
mA
IQ = 1 mA
Tj = 25 °C
IQ = 1 mA
Tj = 85 °C
IQ = 250 mA
IQ = 400 mA
Data Sheet
13
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Typical Performance Characteristics Current Copnsumption
Current Consumption Iq versus
Output Current IQ (IQ low)
Current Consumption Iq versus
Output Current IQ
08_IQ_IQ_IQLOW.VSD
7
09_IQ_IQ.VSD
30
V I = 13.5 V
V I = 13.5 V
T j = 150 °C
6
T j = 150 °C
25
5
4
3
I q [mA]
I q [mA]
20
T j = 25 °C
15
T j = 25 °C
10
2
5
1
0
0
0
50
100
150
0
200
100
200
300
400
500
I Q [mA]
I Q [mA]
Current Consumption Iq versus
Input Voltage VI
10_IQ_VI.VSD
60
50
I q [mA]
40
30
R LOAD = 12.5 Ω
20
10
R LOAD = 500 Ω
0
0
10
20
30
40
V I [V]
Data Sheet
14
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.3
Reset Function
The reset function provides several features:
Output Undervoltage Reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used
to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame
from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from
“low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D
charged by the delay capacitor charge current ID,ch starting from VD = 0 V.
If the application needs a power-on reset delay time trd different from the value given in Item 5.3.6, the delay
capacitor’s value can be derived from the specified values in Item 5.3.6 and the desired power-on delay time:
t rd, new
C D = ---------------- × 47nF
t rd
with
•
•
•
CD: capacitance of the delay capacitor to be chosen
trd,new: desired power-on reset delay time
trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset Reaction Time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset
reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay
capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
t rr = t rd, int + t rr, d
with
•
•
•
trr: reset reaction time
trr,int: internal reset reaction time
trr,d: reset discharge
Reset Output Pull-Up Resistor RRO:
The Reset Output RO is an open collector output requiring an external pull-up resistor to a voltage VIO, e.g. VQ. In
Table “Electrical Characteristics Reset Function” on Page 18 a minimum value for the external resistor RRO
is given for the case it is connected to VQ or to a voltage VIO < VQ. If the pull-up resistor shall be connected to a
voltage VIO > VQ, use the following formula:
5kΩ
R RO = ----------- × V IO
VQ
Data Sheet
15
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Supply
I
Q
Int.
Supply
Control
VDD
CQ
RO
ID,ch
Reset
I RO
VDST
VRT
RRO
MicroController
IDR,dsch
GND
D
BlockDiagram_Reset.vsd
GND
CD
Figure 4
Data Sheet
Block Diagram Reset Function
16
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
VI
t
t < trr,total
VQ
VRT
1V
t
t rd
VD
V DU
V DRL
t
VRO
V RO,low
t rd
trr,total
trd
t rr,total
t rd
t rr,total
1V
t
Thermal
Shutdown
Figure 5
Data Sheet
Input
Voltage Dip
Undervoltage
Spike at
output
Overload
T i mi n g Di a g ra m_ Re se t. vs
Timing Diagram Reset
17
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Electrical Characteristics Reset Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
VRT
4.5
4.65
4.8
V
VQ decreasing
Output Undervoltage Reset
5.3.1
Output Undervoltage Reset
Switching Thresholds
Reset Output RO
5.3.2
Reset Output Low Voltage
VRO,low
–
0.2
0.4
V
1 V ≤ VQ ≤ VRT ;
IRO = 0.2 mA
5.3.3
Reset Output
Sink Current Capability
IRO,max
0.2
–
–
mA
1 V ≤ VQ ≤ VRT ;
VRO = 5 V
5.3.4
Reset Output
Leakage Current
IRO,leak
–
0
10
µA
VRO = 5 V
5.3.5
Reset Output External
Pull-up Resistor to VQ
RRO
5
–
–
kΩ
1 V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
trd
VDU
10
16
22
ms
CD = 47 nF
–
1.8
–
V
–
Reset Delay Timing
5.3.6
Power On Reset Delay Time
5.3.7
Upper Delay
Switching Threshold
5.3.8
Lower Delay
Switching Threshold
VDRL
–
0.65
–
V
–
5.3.9
Delay Capacitor
Charge Current
ID,ch
–
5.5
–
µA
VD = 1 V
5.3.10
Delay Capacitor
Reset Discharge Current
ID,dch
–
100
–
mA
VD = 1 V
5.3.11
Delay Capacitor
Discharge Time
trr,d
–
0.5
1
µs
Calculated Value:
trr,d = CD*(VDU VDRL)/ ID,dch
CD = 47 nF
5.3.12
Internal Reset Reaction Time
–
4
7
µs
CD = 0 nF1)
5.3.13
Reset Reaction Time
trr,int
trr,total
–
4.5
8
µs
Calculated Value:
trr,total = trr,int + trr,d
CD = 47 nF
1) parameter not subject to production test; specified by design
Data Sheet
18
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Typical Performance Characteristics
Power On Reset Delay Time trd versus
Junction Temperature Tj
Undervoltage Reset Switching Threshold
VRT versus Tj
11_VRT_TJ.VSD
5
12_TRD_TJ.VSD
20
C D = 47 nF
18
4,9
16
14
4,8
t rd [ms]
V RT [V]
12
4,7
10
8
4,6
6
4
4,5
2
4,4
0
-40
0
40
80
120
160
-40
0
Power On Reset DelayTime trd versus
Capacitance CD
160
14_T RRINT_TJ.VSD
3,5
80
3
T j = -40 °C
T j = 25 °C
2,5
T j = 150 °C
t rr,int [µs]
60
t rd [ms]
120
Internal Reset Reaction Time trr,int versus Junction
Temperature Tj
13_TRD_CD.VSD
70
80
T j [°C]
T j [°C]
90
40
50
40
2
1,5
30
1
20
0,5
10
0
0
50
100
150
200
0
250
-40
C D [nF]
Data Sheet
0
40
80
120
160
T j [°C]
19
Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Delay Capacitor Discharge Time trr,d versus
Junction Temperature Tj
15_TRRD_TJ.VSD
0,6
C D = 47 nF
0,5
t rr,d [µs]
0,4
0,3
0,2
0,1
0
-40
0
40
80
120
160
T j [°C]
Data Sheet
20
Rev. 1.0, 2008-05-29
TLE42754
Package Outlines
6
Package Outlines
6.5 +0.15
-0.05
A
1)
2.3 +0.05
-0.10
0.9 +0.20
-0.01
0...0.15
0.5 +0.08
-0.04
5 x 0.6 ±0.1
1.14
4.56
0.5 +0.08
-0.04
0.51 MIN.
0.15 MAX.
per side
B
(5)
0.8 ±0.15
(4.24) 1 ±0.1
9.98 ±0.5
6.22 -0.2
5.7 MAX.
0.1 B
0.25
M
A B
1) Includes mold flashes on each side.
All metal surfaces tin plated, except area of cut.
Figure 6
Data Sheet
PG-TO252-5
21
Rev. 1.0, 2008-05-29
TLE42754
Package Outlines
4.4
10 ±0.2
1.27 ±0.1
A
8.5 1)
B
0.05
2.4
0.1
2.7 ±0.3
4.7 ±0.5
7.55 1)
9.25 ±0.2
(15)
1±0.3
0...0.3
0...0.15
5 x 0.8 ±0.1
0.5 ±0.1
4 x 1.7
0.25
M
A B
8˚ MAX.
1) Typical
Metal surface min. X = 7.25, Y = 6.9
All metal surfaces tin plated, except area of cut.
Figure 7
0.1 B
GPT09113
PG-TO263-5
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
22
Dimensions in mm
Rev. 1.0, 2008-05-29
TLE42754
Revision History
7
Revision History
Version
Date
Changes
1.0
2008-05-29
final data sheet
Data Sheet
23
Rev. 1.0, 2008-05-29
Edition 2008-05-29
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
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information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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