STSJ2NM60 N-CHANNEL 600V - 2.8Ω - 2A PowerSO-8 Zener-Protected MDmesh™ POWER MOSFET ■ ■ ■ ■ ■ ■ TYPE VDSS RDS(on) ID STSJ2NM60 600 V < 3.2 Ω 2A TYPICAL RDS(on) = 2.8 Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTORING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar completition’s products. APPLICATIONS The MDmesh™ family is very suitable for increase the power density of high voltage converters allowing system miniaturization and higher efficiencies. PowerSO-8 INTERNAL SCHEMATIC DIAGRAM DRAIN CONTACT ALSO ON THE BACKSIDE ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID IDM (2) PTOT PTOT Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ± 30 V Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TA = 25°C (1) Drain Current (continuous) at TC = 100°C 2 0.37 1.26 A A A Drain Current (pulsed) 8 A Total Dissipation at TC = 25°C Total Dissipation at TA = 25°C (1) 70 3 W W 0.02 W/°C 15 V/ns – 65 to 150 °C Derating Factor (1) dv/dt (3) Tstg Tj August 2002 Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature 1/8 STSJ2NM60 THERMAL DATA Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case Max 1.78 °C/W 42 °C/W 150 °C – 65 to 150 °C Thermal Resistance Junction-ambient Max (1) Max. Operating Junction Temperature Storage Temperature ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 600 Unit Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±5 µA Max. Unit ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 1 A Min. 3 Typ. 4 5 V 2.8 3.2 Ω Typ. Max. Unit DYNAMIC Symbol gfs (4) 2/8 Parameter Test Conditions Min. Forward Transconductance VDS > ID(on) x RDS(on)max, ID = 2 A 1.4 S Ciss Input Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 160 pF Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 67 pF 4 pF 3.5 Ω STSJ2NM60 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. Typ. Max. Unit VDD = 300 V, ID = 1 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) 13 ns 8 ns VDD = 480 V, ID = 2 A, VGS = 10 V 6 1.8 3.3 8.4 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-Over Time Test Conditions Min. 12 25 30 VDD = 480 V, ID = 2 A, RG = 4.7Ω, VGS = 10 V (see test circuit, Figure 3) ns ns ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 2 A ISDM (2) Source-drain Current (pulsed) 8 A VSD (4) Forward On Voltage ISD = 2 A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 516 516 2 ns nC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 808 890 2.2 ns nC A ISD trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. Parameter Test Conditions Min. Typ. When mounted on 1inch² FR4 Board, 2oz of Cu, t ≤ 10 sec. Pulse width limited by safe operating area ISD<3.3A, di/dt<400A/µs, VDD<V(BR)DSS , TJ<TJMAX Pulsed: Pulse duration = 400 µs, duty cycle 1.5 % GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8 STSJ2NM60 Output Characteristics Transconductance Gate Charge vs Gate-source Voltage 4/8 Transfer Characteristics Static Drain-source On Resistance Capacitance Variations STSJ2NM60 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs. Temperature 5/8 STSJ2NM60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STSJ2NM60 PowerSO-8™ MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.25 a2 MAX. 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 5.0 0.188 0.196 6.2 0.228 c1 45° (typ.) D 4.8 E 5.8 0.244 e 1.27 0.050 e3 3.81 0.150 e4 2.79 0.110 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8° (max.) 7/8 STSJ2NM60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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