TDA7266D 5W+5W DUAL BRIDGE AMPLIFIER PRELIMINARY DATA ■ ■ ■ ■ WIDE SUPPLY VOLTAGE RANGE (3.5 - 12V) OUTPUT POWER 5+5W @THD = 10%, R L = 8Ω, VCC = 9.5V TECHNOLOGY BI20II SINGLE SUPPLY MINIMUM EXTERNAL COMPONENTS – NO SVR CAPACITOR – NO BOOTSTRAP – NO BOUCHEROT CELLS – INTERNALLY FIXED GAIN PowerSO20 Slug Down ORDERING NUMBER: TDA7266D ■ STAND-BY & MUTE FUNCTIONS ■ SHORT CIRCUIT PROTECTION ■ THERMAL OVERLOAD PROTECTION designed for LCD TV/Monitor, PC Motherboard, TV and Portable Audio applications. DESCRIPTION The TDA7266D is a dual bridge amplifier specially TEST AND APPLICATION CIRCUIT VCC +5V JP1 R1 47K R2 47K C3 0.22µF IN1 S-GND ST-BY 6 7 + 2 OUT1+ 5 OUT1- 19 OUT2+ 16 OUT2- C2 100nF C7 100nF 13 R3 10K 9 C4 10µF Vref C5 0.22µF IN2 MUTE C1 470µF 15 14 R4 10K 8 + + - C6 1µF 1 10 11 PW-GND 20 + D02AU1407 May 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/13 TDA7266D ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vs Supply Voltage 20 V IO Output Peak Current (internally limited) 1.5 A Ptot Total Power Dissipation (Tamb = 70°C 25 W Top Operating Temperature 0 to 70 °C -40 to 150 °C Value Unit Tstg, Tj Storage and Junction Temperature THERMAL DATA Symbol Parameter Rth j-case Thermal Resistance Junction-case 2.1 °C/W Rth j-amb Thermal Resistance Junction-ambient (on recomended PCB) note1 15 °C/W Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer. PIN CONNECTION PW GND 1 20 PW GND OUT1+ 2 19 OUT2+ N.C. 3 18 N.C. N.C. 4 17 N.C. OUT1- 5 16 OUT2- VCC 6 15 VCC IN1 7 14 IN2- MUTE 8 13 SGND ST BY 9 12 N.C. 10 11 PW GND PW GND D02AU1408 2/13 TDA7266D ELECTRICAL CHARACTERISTCS (Refer to test circuit) VCC = 9.5V, RL = 8Ω, f = 1KHz, Tamb = 25°C unless otherwise specified) Symbol VCC Iq Parameter Test Condition Supply Range Typ. Max. Unit 3.5 9.5 12 V 50 60 mA 120 mV Total Quiescent Current VOS Output Offset Voltage PO Output Power THD 10% Total Harmonic Distortion PO = 1W THD Min. 4.3 5 0.05 PO = 0.1W to 2W f = 100Hz to 15KHz SVR CT AMUTE Supply Voltage Rejection 46 60 dB Mute Attenuation 60 80 dB 150 °C 25 26 Voltage Gain Matching Ri Input Resistance VTMUTE Mute Threshold eN % Crosstalk Closed Loop Voltage Gain IST-BY 1 dB GV VTST-BY % 56 Thermal Threshold ∆GV 0.2 40 Tw f = 100Hz, VR =0.5V W dB 0.5 dB 25 30 for VCC > 6.4V; Vo = -30dB 2.3 2.9 4.1 V for VCC < 6.4V; Vo = -30dB VCC/2 -1 VCC/2 -0.75 VCC/2 -0.5 V 0.8 1.3 1.8 V 100 µA St-by Threshold St-by Current V6 = GND Total Output Voltage 27 A Curve 150 KΩ µV 3/13 TDA7266D APPLICATIVE SUGGESTIONS STAND-BY AND MUTE FUNCTIONS (A) Microprocessor Application In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right Stby and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2). At first St-by signal (from µP) goes high and the voltage across the St-by terminal (Pin 9) starts to increase exponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs. When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C1, C3) start to charge. It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers. A delay of 100-200ms between St-by and mute signals is suitable for a proper operation. Figure 1. Microprocessor Application VCC C1 0.22µF IN1 6 7 + 2 C5 470µF OUT1+ 5 OUT1- 19 OUT2+ 16 OUT2- 15 - ST-BY R1 10K 9 C2 10µF S-GND µP 13 Vref C3 0.22µF IN2 MUTE R2 10K 14 + + - 8 C4 1µF 1 10 PW-GND 11 - 20 + D02AU1409 4/13 C6 100nF TDA7266D Figure 2. Microprocessor Driving Signals +VS(V) +18 VIN (mV) VST-BY pin 9 1.8 1.3 0.8 VMUTE pin 8 4.1 2.9 2.3 Iq (mA) VOUT (V) OFF ST-BY PLAY MUTE MUTE ST-BY OFF D02AU1411 B) Low Cost Application In low cost applications where the mP is not present, the suggested circuit is shown in fig.3. The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage divider. The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by and mute threshold exceeding, avoiding "Popping" problems. So to avoid any popping or clicking sond, it is important to clock: a Correct Sequence: At turn-ON, the Stand-by must be removed at first, then the Mute must be released after a delay of about 100-200ms. On the contrary at turn-OFF the Mute must be activated as first and then the Stand-by. With the values suggested in the Application circuit the right operation is guaranteed. b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see the above limits) a wrong external voltage causes uncertain commutations for the two functions we suggest to use the following values: Mute for Vcc>6.4V : VT = 2.3V Mute for Vcc<6.4V : VT = Vcc/2 - 1 Stand-by : VT = 0.8V 5/13 TDA7266D Figure 3. Stand-alone low-cost Application VCC C3 0.22µF R1 47K + IN1 ST-BY R2 47K 6 7 2 C1 470µF OUT1+ 5 OUT1- 19 OUT2+ 16 OUT2- 15 C2 100nF C7 100nF 9 C4 10µF S-GND 13 Vref C5 0.22µF 14 IN2 + + - MUTE 8 1 10 PW-GND 11 - 20 + D02AU1410 PCB Layout and External Components: Regarding the PCB layout care must be taken for three main subjects: c) Signal and Power Gnd separation d) Dissipating Copper Area e) Filter Capacitors positioning )Signal and Power Gnd separation: c To the Signal GND must be referred the Audio Input Signals, the Mute and Stand-by Voltages and the device PIN.13. This Gnd path must be as clean as possible in order to improve the device THD+Noise and to avoid spurious oscillations across the speakers. The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed by large amount of current, this path is also used in this device to dissipate the heating generated (no needs of external heatsinker). Referring to the typical application circuit, the separation between the two GND paths must be obtained connecting them separately (star routing) to the bulk Electrolithic capacitor C1 (470µF). Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Protection Threshold and the Package thermal Characteristics. 6/13 TDA7266D d Dissipating Copper Area: Dissipated Power: The max dissipated power happens for a THD near 1% and is given by the formula: 2 V CC P dmax ( W ) = 2 ⋅ ------------- + I q V CC 2 Rl π -----2 This gives for: Vcc = 9.5V, Rl = 8Ω ,Iq = 50mA a dissipated power of Pd = 5W. Thermal Protection: The thermal protection threshold is placed at a junction temperature of 150°C. Package Thermal Characteristics: The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via holes (see picture) is about 15°C/W. This means that with the above mentioned max dissipated Power (Pd=5W) we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer environments where a 50°C ambient is specified as maximum The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances, this in order to avoid the thermal Protection Intervention. The max. dissipated power must be not in excess of 5W , this at turns gives the following operating supply voltages: Load (Ohm) Supply Voltage (V) 4 6.5 6 8.5 8 9.5 16 14 e Filter Capacitors Positioning: The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the output Audio signals. Package Informations: You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available on web. Here we want to focalize the attention only on the the Dissipating elements and ground layer. 7/13 TDA7266D Considering the dissipated power involved in the TDA7266D application that is in the range of 5W, as explained in a previous section, we suggest via holes ( see fig. 4). Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is chosen accordingly to the desired performance (in our demonstration board we use 15 vias). In fig.4 is shown as an example the footprint to be used to create the vias. Figure 4. The above metioned mounting solution is enough to dissipate the power involved In the most part of the application using the TDA7266D. If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board. Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate 8/13 TDA7266D Figure 6. Distortion vs Frequency Figure 9. Stand-By attenuation vs Vpin 9 THD(%) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 Vcc = 9.5 V Rl = 8 ohm 1 Pout = 100mW 0.1 Pout = 2W 0.010 100 1k 10k 20k Attenuation (dB) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Vpin.7 (V) frequency (Hz) Figure 10. Quiescent Current vs Supply Voltage Figure 7. Gain vs Frequency Iq (mA) Level(dBr) 70 5.0000 4.0000 65 Vcc = 9.5V Rl = 8 ohm Pout = 1W 3.0000 60 2.0000 55 1.0000 0.0 50 -1.000 45 -2.000 40 -3.000 35 -4.000 30 -5.000 10 100 1k 10k 3 100k 4 5 frequency (Hz) 6 7 8 9 10 11 12 Vsupply(V) Figure 11. Total Power Dissipation & Efficiency vs Pout Figure 8. Mute Attenuation vs Vpin.8 Attenuation (dB) 10 Pd(W) 6 70 Eff(%) 0 -10 5 60 4 50 -20 -30 -40 -50 Vcc= 9.5V Rl = 8 ohm 3 -60 -70 40 f=1KHZ 2 Channels 2 30 -80 -90 -100 1 1 1.5 2 2.5 3 3.5 Vpin.6(V) 4 4.5 20 5 0 10 0 1 2 3 4 5 2 X Pout (W) 9/13 TDA7266D Figure 12. THD+N vs Output Power Figure 13. THD+N vs Output Power THD(%) 10 THD(%) 5 10 5 Vcc=9.5V 2 2 Rl=8ohm 1 f=1KHz 1 Vcc=12V Rl=16 ohm f = 1KHz 0.5 0.5 0.2 0.1 0.2 0.05 0.1 0.02 100m 200m 300m 500m700m 1 Pout(W) 2 3 Figure 14. PC Board Component Layout 10/13 4 56 0.01 100m 200m 300m 500m 700m 1 Pout(W) 2 3 4 5 TDA7266D Figure 15. Evaluation Board Top Layer Layout Figure 16. Evaluation Board Bottom Layer Layout 11/13 TDA7266D DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 D (1) 15.8 16 0.622 0.630 0.386 D1 9.4 9.8 0.370 E 13.9 14.5 0.547 e 1.27 e3 E1 (1) 0.570 0.450 11.1 E2 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 h L 0.626 1.1 0.8 JEDEC MO-166 0.043 1.1 N Weight: 1.9gr 0.050 11.43 10.9 OUTLINE AND MECHANICAL DATA MAX. 0.031 0.043 8˚ (typ.) S 8˚ (max.) T 10 0.394 PowerSO20 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 0056635 12/13 TDA7266D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 13/13