STMICROELECTRONICS TDA7437

TDA7437

DIGITALLY CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER
- FOUR STEREO, ONE MONO INPUT, AND
ONE DIFFERENTIAL INPUT
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
FULLY
PROGRAMMABLE
LOUDNESS
FUNCTION
VOLUME CONTROL IN 1dB STEPS INCLUDING GAIN UP TO 16dB
ZERO CROSSING MUTE, SOFT MUTE AND
DIRECT MUTE
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1dB STEPS FOR
BALANCE AND FADER FACILITIES
PAUSE
DETECTOR
PROGRAMMABLE
THRESHOLD
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS
PQFP44 and TQFP44
ORDERING NUMBERS: TDA7437 (PQFP44)
TDA7437T (TQFP44)
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are implemented.
The soft Mute function can be activated in two
ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 28 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
DESCRIPTION
The audioprocessor TDA7437 is an upgrade of
the TDA731X audioprocessor family.
OUT_LF
PAUSE
DGND
SDA
SCL
CREF
ADDR
DVDD
AVDD
AGND
TREB-L
PIN CONNECTION
44 43 42 41 40 39 38 37 36 35 34
TREB_R
1
33
OUT_RF
IN_R
2
32
OUT_LR
MUXOUT_R
3
31
MID_RI
LOUD_R
4
30
MID_RO
DIFFGND_R
5
29
OUT_RR
DIFF_R
6
28
SMEXT
STEREO4_R
7
27
BASS_RO
STEREO1_R
8
26
BASS_RI
STEREO2_R
9
25
BASS_LO
STEREO3_R
10
24
BASS_LI
MONO
11
23
MID_LO
MID_LI
MUXOUT_L
IN_L
CSM
STEREO3_L
STEREO2_L
STEREO1_L
STEREO4_L
DIFF_L
LOUD_L
December 1999
DIFFGND_L
12 13 14 15 16 17 18 19 20 21 22
D96AU435A
1/23
TDA7437
ABSOLUTE MAXIMUM RATINGS
Symbol
AVDD, DVDD
Parameter
Value
Operating Supply Voltage
Unit
10.5
V
Tamb
Operating Ambient Temperature
-40 to 85
°C
Tstg
Storage Temperature Range
-55 to 150
°C
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction-pins
Max.
Value
Unit
150
°C/W
QUICK REFERENCE DATA
Symbol
AVDD, DVDD
Parameter
Supply Voltage (AVDD and DVDD must be at the same potential)
Typ.
Max.
Unit
6
9
10.2
V
VCL
Max. input signal handling
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio
111
dB
SC
Channel Separation f = 1KHz
95
dB
Input Gain 1dB step
2.1
2.6
Vrms
0.8
%
0
15
Volume Control 1dB step
-63
16
dB
Treble Control 2dB step
-14
+14
dB
dB
Bass Control 2dB step
-14
+14
dB
Middle Control 2dB step
-14
+14
dB
Fader and Balance Control 1dB step
-79
0
dB
0
20
dB
Loudness Control 1dB step
Mute Attenuation
2/23
Min.
100
dB
2 x 4.7µF
5 x 470nF
2 x 4.7µF
AVDD
DVDD
DIFFINRGND
DIFFINR
STEREOIN4R
STEREOIN3R
STEREOIN2R
STEREOIN1R
MONO
DIFFINLGND
DIFFINL
STEREOIN4L
STEREOIN3L
STEREOIN2L
STEREOIN1L
ANGND
MULTIPLEXER
22µF
CREF
SUPPLY
2.2µF
INGAIN
INGAIN
MUXOUT_L
MUXOUT_R
4 x 470nF
47nF 5.6nF
LOUD(R)
TREBLE
VOLUME
+ LOUDN
MIDDLE
MIN(L)
IN_L
IN_R
BASS
MOUT
(R)
22nF
2.7K
100nF
BOUT(R)
BASS
18nF 100nF
5.6K
MIN(R)
MIDDLE
CSM
47nF
47nF
SPKR
ATT
S-MUTE
SPKR
ATT
SPKR
ATT
SPKR
ATT
S-MUTE
MUTE CONTROL
SOFT, ZERO
BIN(L)
100nF
BOUT(L)
I2C BUS DECODER + LATCHES
MOUT(L)
TREBLE
TREBLE(L)
VOLUME
+ LOUDN
LOUD(L)
TREBLE(R)
5.6K
18nF 100nF
BIN(R)
2.7K
22nF
SMEXT
5.6nF
PAUSE
2.2µF 47nF
D95AU249B
FRout
RRout
DIGGND
SDA
SCL
ADDR
RLout
FLout
TDA7437
BLOCK DIAGRAM
3/23
TDA7437
ELECTRICAL CHARACTERISTICS (AVDD, DVDD = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C;
all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
130
Unit
INPUT SELECTOR (MONO AND STEREO INPUTS)
RI
VCL
Input Resistance
pin 7 to 11 and 15 to 18
70
100
Clipping Level
d ≤ 0.3%
2.1
2.6
95
SI
Input Separation
80
RL
Output Load Resistance
2
KΩ
VRMS
dB
KΩ
GI MIN
Minimum Input Gain
-0.75
0
+0.75
dB
GI MAX
Maximum Input Gain
14
15
16
dB
Gstep
Step Resolution
0.5
1.0
1.5
dB
Ea
Set Error
-1.0
0
1.0
dB
VDC
DC Steps
0.5
10
Adiacent Gain Steps
GIMIN to GIMAX
3
mV
mV
DIFFERENTIAL INPUT (Pin 5, 6, 13, 14)
RI
CMRR
d
e IN
GDIFF
Input Resistance
Input selector BIT D4 = 0 (0dB)
10
15
20
KΩ
Input selector BIT D4 = 1(-6dB)
14
20
26
KΩ
45
Common Mode Rejection Ratio
VCM = 1VRMS ;
Distortion
VI = 1VRMS
f =1KHz
70
Input Noise
20Hz to 20KHz; Flat; D6 = 0
Differential Gain
D4 = 0
-1
0
1
dB
D4 = 1
-7
-6
-5
dB
0.01
dB
0.08
%
µV
5
VOLUME CONTROL
31
44
57
KΩ
GMAX
Maximum Gain
15
16
17
dB
AMAX
Maximum Attenuation
61
63.75
66.5
dB
Step Resolution Coarse Atten.
0.5
1.0
1.5
dB
G = 16 to -20dB
-1.0
0
1.0
dB
G = -20 to -63dB
-2.75
2.75
dB
2
dB
Adjacent Gain Steps
-5
+5
mV
Adjacent Attenuation Steps
-3
RI
ASTEPC
EA
Et
VDC
Input Resistance
Attenuation Set Error
Pin 2 and 20
Tracking Error
DC Steps
+3
mV
0.5
5
mV
35
50
65
KΩ
From 0dB to AMAX
LOUDNESS CONTROL (Pin 4, 12)
RI
Internal Resistor
Loud = On
AMAX
Maximum Attenuation
19
20
21
dB
Astep
Step Resolution
0.5
1
1.5
dB
ZERO CROSSING MUTE
V TH
Zero Crossing Threshold
(note 1)
WIN = 11
30
mV
WIN = 10
60
mV
WIN = 01
110
mV
220
mV
WIN = 00
AMUTE
VDC
4/23
Mute Attenuation
DC Step
80
0dB to Mute
100
0.1
dB
3
mV
TDA7437
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
50
65
CCSM = 22nF; 0 to -20dB; I = IMAX
0.8
1.5
2.0
ms
CCSM = 22nF; 0 to -20dB; I = IMIN
25
45
60
ms
VCSM = 0V; I = IMAX
20
40
60
µA
SOFT MUTE
AMUTE
Mute Attenuation
TDON
ON Delay Time
TDOFF
OFF Current
VCSM = 0V; I = IMIN
R INT
Pullup Resistor (pin 28)
VSMH
(pin 28) Level High
(pin 28) Level Low
VSML
BASS CONTROL
(note 2)
dB
2
µA
100
KΩ
3.5
V
Soft Mute Active
±11.5
±14
1
V
±16
dB
Crange
Control Range
Astep
Step Resolution
1
2
3
dB
Internal Feedback Resistance
31
44
57
KΩ
±11.5
±14
±16
dB
Rg
MIDDLE CONTROL
Crange
Control Range
Astep
Step Resolution
Rg
Internal Feedback Resistance
1
2
3
dB
17.5
25
32.5
KΩ
±13
±14
±15
dB
1
2
3
dB
1.5
dB
1.5
dB
3
mV
TREBLE CONTROL
C RANGE
Astep
Control Range
Step Resolution
SPEAKER ATTENUATORS
C RANGE
Astep
Control Range
Step Resolution
79
AV = 0 to -40dB
0.5
1
80
100
Output Mute Attenuation
Data Word = 1111XXXX
EA
Attenuation Set Error
AV = 0 to -40dB
VDC
DC Steps
Adjacent Attenuation Steps
AMUTE
0.1
dB
dB
AUDIO OUTPUT
Vclip
Clipping Level
RL
Output Load Resistance
d = 0.3%
2.1
2
2.6
Vrms
RO
Output Impedance
50
90
140
Ω
VDC
DC Voltage Level
3.5
3.8
4.1
V
KΩ
5/23
TDA7437
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
PAUSE DETECTOR
V TH
Pause Threshold
IDELAY
Pull-Up Current
VTHP
Pause Threshold
WIN = 11
30
mV
WIN = 10
60
mV
WIN = 01
110
mV
WIN = 00
220
15
25
mV
35
3.0
µA
V
GENERAL
VCC
ICC
PSRR
eNO
Et
S/N
Supply Voltage
6
9
10.2
V
7
10
13
mA
70
90
dB
µV
Supply Current
Power Supply Rejection Ratio
f = 1KHz
Output Noise
Output Muted (B = 20 to 20kHz flat)
4
All Gains 0dB
(B= 200 to 20kHz flat)
6
15
µV
AV = 0 to -20dB
0
1
dB
AV = -20 to -60dB
0
2
dB
Total Tracking Error
All Gains = 0dB; VO = 2.1Vrms
Signal to Noise Ratio
SC
Channel Separation L - R
d
Distortion
111
80
VIN =1V all gain = 0dB
dB
95
0.01
dB
0.08
%
1
V
5
µA
0.4
V
BUS INPUTS
V IL
Input Low Voltage
VlN
Input High Voltage
IlN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Acknowledge
IO = 1.6mA
3
V
-5
0.1
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
Note 2: Internall pullup resistor to Vs/2; ”LOW” = softmute active
Note: The ANGND and DIGGND layout wires must be kept separated. A 50Ω resistor is recommended to be put as far as possible
from the device.
The CLD - and CDR - can be shortcircuited in applications providing 3 wires CD signal
L+
CD
∼RL- =
L+
LR-
R+
R+
D00AU1125
CLD - = DIFFINLGND
CDR - = DIFFINRGND
6/23
TDA7437
TDA7437
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7437 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 3: Data Validity on the I2CBUS
Figure 4: Timing Diagram of I2CBUS
2
Figure 5: Acknowledge on the I CBUS
7/23
TDA7437
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
read (=1)/write (=0) transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
MSB
A R/W ACK X
X
DATA 1 to DATA n
LSB
X
I
MSB
A3 A2 A1 A0 ACK
LSB
DATA
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
ADDRpin open
A= 0
ADDRpin close to Vs A = 1
AUTO INCREMENT
If bit I in the subaddress byte is set to ”1”, the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)
MSB
LSB
X
X
X
I
A2
A1
A0
0
0
0
0
Input Selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker Attenuator LF
0
1
0
1
Speaker Attenuator LR
0
1
1
0
Speaker Attenuator RF
0
1
1
1
Speaker Attenuator RR
1
0
0
0
Input Gain Middle
1
0
0
1
Mute
TRANSMITTED DATA
Send Mode
MSB
X
LSB
X
X
X
X
SM
ZM
P
P = Pause (Active low)
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
8/23
FUNCTION
A3
ACK P
TDA7437
DATA BYTE SPECIFICATION
Input Selector
MSB
D7
X
LSB
D6
X
D5
D4
FUNCTION
D3
D2
D1
D0
1
0
0
0
DIFFERENTIAL
1
0
0
1
STEREO 1
1
0
1
0
STEREO 2
1
0
1
1
STEREO 3
1
1
0
0
STEREO 4
1
1
0
1
MONO
0
X
X
X
DC CONNECT (1)
X
X
0
0
HALF-DIFF 0dB (*)
0
1
HALF-DIFF -6dB (*)
1
0
FULL-DIFF 0dB (**)
1
1
FULL-DIFF -6dB (**)
(*) Selected when using a 3 wires differential source (pins 5 and 13 shorted)
(**) Selected when using 4 wires differential source
(1) OUTR-INR (OUTL-INR) short circuited internally (no need external connection)
Loudness
MSB
D7
D6
0
0
1
1
0
1
0
1
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
LSB
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FUNCTION
LOUDNESS STEP
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
16dB
17dB
18dB
19dB
20dB
LOUDNESS OFF
FINE VOLUME
0dB
-0.25dB
-0.5dB
-0.75dB
9/23
TDA7437
Mute
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
0
0
0
0
0
FUNCTION
D0
1
Soft Mute On
0
1
Soft Mute with fast slope
1
1
Soft Mute with slow slope
1
Zero Mute
1
Direct Mute
1
Reset
0
0
0
Zerocross window (220mV)
0
1
0
Zerocross window (110mV)
1
0
0
Zerocross window (60mV)
1
1
0
Zerocross window (30mV)
0
Nonsymmetrical Bass
1
Symmetrical Bass
Volume
MSB
D7
LSB
D6
D5
D4
D3
FUNCTION
D2
D1
D0
1
0
0
0
0dB
1
0
0
1
-1dB
1
0
1
0
-2dB
1
0
1
1
-3dB
1
1
0
0
-4dB
1
1
0
1
-5dB
1
1
1
0
-6dB
1
1
1
1
-7dB
1
1
0
0
0
0
16dB
1
0
0
0
1
8dB
1
0
0
1
0
0dB
1
0
0
1
1
-8dB
1
0
1
0
0
-16dB
1
0
1
0
1
-24dB
1
0
1
1
0
-32dB
1
0
1
1
1
-40dB
1
1
0
0
0
-48dB
1
1
0
0
1
0
X
X
X
X
10/23
-56dB
X
X
X
MUTE
TDA7437
Speaker
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1.25dB step
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
1
1
1
1
-72dB
X
X
X
MUTE
11/23
TDA7437
Bass Treble
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
FUNCTION
TREBLE STEP
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
BASS STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
126B
1
0
0
0
14dB
12/23
TDA7437
Input Stage Gain Middle
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
FUNCTION
IN-GAIN STEP
0
0
0
0
0dB
0
0
0
1
1dB
0
0
1
0
2dB
0
0
1
1
3dB
0
1
0
0
4dB
0
1
0
1
5dB
0
1
1
0
6dB
0
1
1
1
7dB
1
0
0
0
8dB
1
0
0
1
9dB
1
0
1
0
10dB
1
0
1
1
11dB
1
1
0
0
12dB
1
1
0
1
13dB
1
1
1
0
14dB
1
1
1
1
15dB
MIDDLE STEP
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
126B
1
0
0
0
14dB
13/23
TDA7437
MUTE & PAUSE FEATURES
The TDA7437 provides three types of mute, controlled via I2C bus (see pag. 10, MUTE BYTE register).
SOFT MUTE
Bit D0=1 → Soft Mute ON
Bit D0=0 →Soft Mute OFF
It allows an automatic soft muting and unmuting
of the signal.
The time constant is fixed by an external capacitor Csm inserted between pin Csm and ground.
Once fixed the external capacitor, two different
slopes (time constant) are selectable by programmation of bit D1.
Bit D1=0 → fast slope (I=Imax)
Bit D1=1 → slow slope (I=Imin)
The soft mute generates a gradual signal decreasing avoiding big click noise of an immediate
high attenuation, without necessity to program a
sequence of decreasing volume levels. A response example is reported in Fig.12 (mute) and
Fig.13 (unmute). The final attenuation obtained
with soft mute ON is 60dB typical.
The used reference parameter is the delay time
taken to reach 20dB attenuation (no matter what
the signal level is).
Using a capacitor Csm=22nF this delay is:
d = 1. 8ms when selected Fast slope mode (bit D1=0)
d = 25 ms when selected Slow slope mode (bit D1=1
In application, the soft mute ON programmation
should be followed by programmation of DIRECT
MUTE ON (see later) in order to achieve a final
100dB attenuation.
Beside the I2C bus programmation, the Soft Mute
ON can be generated in a fast way by forcing a
LOW level at pin SMEXT (TTL Level compatible).
This approach is recommended for fast RDS AF
switching.
The Soft Mute status can be detected via I2C
bus, reading the Transmitted Byte, bit SM (see
data sheet pag. 8).
read bit SM = 1 soft mute status ON
read bit SM = 0 soft mute status OFF
DIRECT MUTE
bit D3 = 1 Direct mute ON
bit D3 = 0 Direct nute OFF
The direct mute bit forces an internal immediate
signal connection to ground.
It is located just before the Volume/Loudness
stage, and gives a typical 100dB attenuation.
SPEAKERS MUTE
14/23
An additional direct mute function is included in
the speakers attenuators stage.
The four output LF, RF, LR, RR can be separately
muted by setting the speaker attenuator byte to
the value 01111111 binary.
Typical attenuation level 100dB. This mute is useful for fader and balance functions. It should not
be applied for system mute/unmute, because it
can generate noise due to the offset of previous
stages (bass / treble).
ZEROCROSSING MUTE
bit D2=1 D4=0 zero crossing mute ON
bit D2=0 D4=0 zero crossing mute OFF
The mute activation/deactivation is delayed until
the signal waveform crosses the DC zero level
(Vref level).
The detection works separately for the left and
the right channels (see Figg. 14, 15). Four different windows threshold are software selectable by
two dedicated bits.
bit D6 bit D5 WINDOW
0
0 Vref DC +/-220mV
0
1 Vref DC +/-110mV
1
0 Vref DC +/-60mV
1
1 Vref DC +/-30mV
The zero crossing mute activation/deactivation
starts when the AC signal level falls inside the selected window (internal comparator).
The ZEROCROSS Mute (and Pause) detector is
always active. It can be disabled, if the feature is
not used, by forcing the bit D4=1 Zero crossing
and Pause detector reset.
In this way the internal comparator logic is
stopped, eliminating its switching noise.
The zero cross mute status is detected reading
the Transmitted Byte bit ZM.
bit ZM = 1 zero cross mute status ON
bit ZM = 0 zero cross mute status OFF
PAUSE FUNCTION
On chip is implemented a pause detector block.
It uses the same 4 windows threshold selectable
for the zero crossing mute, bit D6,D5 byte MUTE
(see above). The detector can be put in OFF by
forcing bit D4=1, otherwise it is active.
The Pause detector info is available at PAUSE
pin. A capacitor must be connected between
PAUSE pin and Ground.
When the incoming signal is detected to be outside the selected window, the external capacitor
is discharged. When the signal is inside the window, the capacitor is integrating up (see Figg.16
and 17).
TDA7437
a)by reading directly the Pause pin level.
The ON/OFF voltage threshold is 3.0V typical.
Pause OFF = level low (< 3.0V)
Pause ON = level high ( ; 3.0V)
b)by reading via I2C bus the Transmitted Byte, bit P
P = 0 pause active.
P = 1 no pause detected.
The external capacitor value fixes the time constant.
The pull up current is 25uV typical
With input signal
Vin = 1Vrm --; Vdc pin pause = 15mV
Vin = 0Vrms --; Vdc pin pause = 5.62V
For example choosing Cpause = 100nF the
charge up constant is about 22ms. Instead with
Cpause = 15nF the charge up constant is about
360us.
The Pause detection is useful in applications like
RDS, to perform noiseless tuning frequeny jumps
avoiding to mute the signal.
NO SYMMETRICAL BASS CUT RESPONSE
bit D7=0 No symmetrical
bit D7=1 Symmetrical
The Bass stage has the option to generate an
unsymmetrical response, for cut mode settings
(bass level from -2db to - 14dB)
For example using a T-type band pass externa
The feature is useful for human ear equalization
in noisy enviroments like cars etc.
See examples in Fig. 18 (symmetrical response)
and Fig. 19 (unsymmetrical response).
TRANSMITTED DATA (SEND MODE)
bit P = 0
bit P = 1
Pause active
No pause detected
bit ZM = 1
bit ZM = 0
Zero cross mute ON
Zero cross mute OFF
bit SM = 1
bit SM = 0
Soft mute ON
Soft mute OFF
bit ST = 1
bit ST = 0
Stereo signal detected (input MPX)
Mono signal detected (input MPX)
The TDA7437 allows the reading of four info bits.
The type (Stereo/Mono) of received broadcasting
signal is easily checked and displayed by using
the ST bit.
The P bit check is useful in tuning jumps without
signal muting.
The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON,
MUTE byte) and not when the signal level has
reached the 60 dB final attenuation.
TDA7437 I2C BUS PROTOCOL
The protocol is standard I2C, using subaddress
byte plus data bytes (see pagg.8 to 13).
The optional Autoincrement mode allows to refresh all the bytes registers with transmission of a
single subaddress, reducing drastically the total
transmission time.
Without autoincrement, subaddress bit I = 0, to
refresh all the bytes registers (10), it is necessary
to transmit 10 times the chip address, the subaddress and the data byte.
Working with a 100Kb/s clock speed the total time
would be :
[(9*3+2)*10]bits*10us=2.9ms
Instead using autoincrement mode, subaddress
bit I=1, the total time will be:
(9*12+2)*10us=1.1ms.
The autoincrement mode is useful also to refresh
partially the data. For example to refresh the 4
speakers attenuators it is possible to program the
subaddress Spkr LF (code XX010100), followed
by the data byte of SPKR LF, LR, RF, RR in sequence.
Note:
that the autoincrement mode has a module 16
counter, whereas the total used register bytes are
10.
It is not correct to refresh all the 10 bytes starting
from a subaddress different than XX010000.
For example using subaddress XX010010 (volume) the registers from Volume to Mute (see
pag. 8) are correctly updated but the next two
transmitted bytes instead to refer to the wanted
Input selector and Loudness are discharged. (the
solution in this case is to send two separated pattern in autoinc mode, the first composed by address, subaddress XX010010, 8 data bytes, and
the second composed by address, subaddress
XX010000, 2 data bytes).
With autoincrement disabled, the protocol allows
the transmission in sequence of N data bytes of a
specific register, without necessity to resend each
time the address and subaddress bytes.
This feature can be implemented, for example, if
a gradual Volume change has to be performed
(the MCU has not to send the STOP condition,
keeping active the TDA7437 communication).
15/23
TDA7437
WARNING
The TDA7437 always needs to receive a STOP
condition, before beginning a new START condition. The device doesn’t recognize a START condition if a previously active communication was
not ended by a STOP condition.
I2C BUS READ MODE
The TDA7437 gives to the master a 1 byte
”TRANSMITTED INFO” via I2C bus in read
mode. The read mode is Master activated by
sending the chip address with LSB set to 1, followed by acknowledge bit.
The TDA7437 recognizes the request. At the following master generated clocks bits, the
TDA7437 issues the TRANSMITTED INFO byte
on the SDA data bus line (MSB transmitted first).
At the nineth clock bit the MCU master can:
- acknowledge the reception, starting in this
way the transmission of another byte from
the TDA7437.
- no acknowledge, stopping the read mode
communication.
LOUDNESS STAGE
The previous SGS-THOMSON audioprocessors
were implementing a fixed loudness response,
only ON/OFF sw programmable.
No possibility to change the loud boost rate at a
certain volume level.
The TDA7437 implements a fully programmable
loudness control in 20 steps of 1dB.
It allows a customized loudness response for
each application.
The external network connected to the loudness
pins LOUD_L and LOUD_R fixes the type of loudness response
1) Simple Capacitor
The loudness effect is only a boost of low frequencies. (see Fig.20)
2)Second order Loudness (boost of low and
high frequencies).
3)Second order decreased type Loudness
(lower boost of low and high frequencies).
4)Second order modified type Loudness (higher
boost of low and high frequencies).
BASS & MID FILTERS
Several bass filter types can be implemented.
Normally it is used the basic T-type Bandpass Filter.
Starting from the filter component values (R1 internal and R2, C1, C2 external), the centre frequency Fc, the gain Av at max bass boost and
the filter Q factor are computed as follows:
16/23
Fc =
Av =
1
2 ⋅ Π ⋅ √
(R1 ⋅ R2 ⋅ C1 ⋅ C2)

R2⋅ C2 + R2 ⋅ C1 + R1 ⋅ C1
R2 ⋅ C1 + R2 ⋅ C2
Q=

√
(R1 ⋅ R2 ⋅ C1 ⋅ C2)

R2 ⋅ C1 + R2 ⋅ C2
Viceversa fixed Fc, Av, and R1 (internal typ.+/30%), the external component values are:
C1 =
C2 =
R2 =
Av − 1
2 ⋅ Π ⋅ R1 ⋅ Q
Q ⋅ Q ⋅ C1
Av − 1 − Q ⋅ Q
Av − 1 − Q ⋅ Q
2 ⋅ Π ⋅ C1 ⋅ Fc ⋅ (Av − 1) ⋅ Q
TREBLE STAGE
The Treble stage is a simple high pass filter which
time constant is fixed by internal resistor (50Kohm
typ) and an external capacitor connected between
pins TREB_R/TREB_L and Ground.
IN-OUT PINS
The multiplexer output is available at OUT_R and
OUT_L pins for optional connection of external
graphic equalizer (TDA7316/TDA7317), surround
chip (TDA7346) etc. The signal is fed in again at
pins IN_L and IN-R. In case of application without
external devices the pins OUT_L/OUT_R and
IN_L/IN_R can be left unconnected if bit D3 byte
input selector is forced = 0 (DC connect) instead if
bit D3 is kept = 1 an external decoupling capacitor
must be provided between OUTR/INR and
OUTL/INR necessary to avoid signal DC jumps,
generating ”Clicking” output noise.
The input impedance of the next volume stage is
44Kohm typical (minimum 31Kohm). A capacitor
no lower than 1µF should be used.
INPUT SELECTOR
The multiplexer selector can choose one of the
following inputs:
- a differential CD stereo input.
- a mono input.
- four stereo input
The signal fed to the input pins must be decoupled via series capacitors. The minimum allowed
value depends on the correspondent input impedance. For the CD diff input (Zi=10Kohm worst
case ) a Cin=4.7uF is recommended.
TDA7437
Figure 8: Power on Time Constant vs Cref
Capacitor CREF =4.7µF
V
(1V/div)
Figure 9: Power on Time Constant vs Cref
Capacitor CREF =10µF
V
(1V/div)
D95AU380
2
OUT LF
1
CREF
BWL
0.5s/DIV
2
OUT LF
1
CREF
TIME
Figure 10: Power on Time Constant vs Cref Capacitor CREF =22µF
D95AU381
BWL
0.5s/DIV
TIME
Figure 12: Soft Mute ON
D95AU382
V
(1V)
SOFT MUTE=ON SLOPE=FAST Vout=500mVrms
V
D95AU384
Main Menu
2
OUT LF
Pin Csm
1
CREF
BWL
1s/DIV
TIME
V
Figure 11: SVRR vs. Frequency
D95AU383
SVRR
(dB)
-40
Chan 2
1ms 0.2V
Vout
-50
Chan 3
1ms 2V
µF
22
4.7µF
-60
µF
10
47µF
CH1 9V DC
SOFT MUTE
-70
CH1
CH2
CH3
CH4
x
0.5V10
~
TIME
20mV10x ~
x
0.2V10
=
x
20mV10
= T/div 1ms
-80
VS=8V
Ripple=0.2VRMS
AV=-15dB
-90
-100
10
100
1K
10K
Freq(Hz)
17/23
TDA7437
Figure 14: Zero Crossing Mute ON
Figure 13: Soft Mute OFF
ZERO CROSSING MUTE = ON
D95AU389
V
Panel
STATUS
Memory
x Chan 1
0.5ms 0.2V
LEFT
x Chan 2
0.5ms 0.2V
Save
PANEL
SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms
V
Recall
Auxiliary
Setups
Memory
Card
D95AU387
Main Menu
X-Y mode
Persistance
mode
TIME
CH2 528mV DC
RIGHT
Return
Pin Csm
Figure 15: Zero Crossing Mute OFF
V
ZERO CROSSING MUTE = OFF
D95AU390
V
Vout
Chan 2
1ms 0.2V
Main Menu
LEFT
x Chan 2
0.2ms 1V
RIGHT
x Chan 1
0.2ms 0.5V
Chan 1
1ms 2V
Multi Zoom
off
CH1 9V DC
TIME
SOFT MUTE
2ms
Figure 16: Pause Detector
CH1 2.7V DC
TIME
Figure 17: Pause Detector
PAUSE DETECTOR ZCW=160mV Cpause=100nF
PAUSE DETECTOR ZCW=160mV Cpause=100nF
D95AU391
V
Vout
D95AU392
Vout
Main Menu
Main Menu
Chan 1
20ms 0.2V
Chan 2
20ms 2V
CH2 4.12V DC
18/23
TIME
Chan 2
20ms 2V
Chan 3
20ms 0.2V
CH2 4.08V DC
CH1
BWL CH2
CH3
CH4
20mV10x ~
x
0.2V 10
=
x
20mV10
~
x
5mV 10
~ T/div 20ms
TDA7437
Figure 19: Non_Sym _Bass
Figure 18: Sym _Bass
D95AU393
(dB)
ATT
(dB)
D95AU394
10
10
5
5
0
0
-5
-5
-10
-15
-10
-20
-15
10
100
1K
10K
Freq(Hz)
-25
10
100
1K
10K
Freq(Hz)
Figure 20: Loudness
ATT
(dB)
D98AU887
18
16
14
12
10
8
6
4
2
0
10
100
1K
10K
Freq(Hz)
19/23
TDA7437
TEST BOARD DIAGRAM
GND VCC
CON1
C17
22µF
R4
2.7K
C18
100nF
TRR
IN_R
C21
2.2µF
C22 4.7nF
CON4
O_R
LOUDR
44
43
42
ADDR
DVDD
AGND
TRL
C20 5.6nF
AVDD
JP2 JP1
C19
5.6nF
41
C11
18nF
C8
100nF
C10
22nF
MIDRI
40
R3
5.6K
MIDRO
31
C7
100nF
BASSRO
30
C16 22µF
BASSRI
27
CREF
26
39
1
2
24
3
23
4
22
20
C23 4.7µF
DIFG_R
C24 4.7µF
DIFF_R
C25 470nF
ST4_R
C26 470nF
ST1_R
C27 470nF
ST2_R
C28 470nF
ST3_R
C29 470nF
MONO
DIFG_R
DIFF_R
ST4_R
ST1_R
ST2_R
ST3_R
MONO
LOUDR
BASSLO
BASSLI
MIDLO
MIDLI
21
6
38
28
7
37
8
36
9
C5 100nF
C4 22nF
C3 18nF
O_L
SCL
11
33
12
13
14
DIFF_R
15
ST4_R
16
ST1_R
17
ST2_R
19
18
ST3_R
CSM
35
PAUSE
29
32
R1
2.7K
CON2
SCL
JP3
SMEX
SMEX
SDA
SDA
DGND
DGND
R5
50
C14
34
R2
5.6K
C2
2.2µF
10
DIFG_R
C6 100nF
I_L
5
C30 4.7nF
CON5
25
OUTLF
RF
LR
OUTRR
CON3
LF
C13
RF
C12
LR
C9
RR
DIFG_L
GND
C31 4.7µF
DIFF_L
C32 4.7µF
C1
2.2nF
C15
10µF
ST4_L
C33 470nF
ST1_L
C34 470nF
ST2_L
C35 470nF
D98AU882
ST3_L
C36 470nF
20/23
TDA7437
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
1.60
A1
0.05
A2
1.35
B
0.30
C
0.09
0.063
0.15
0.002
1.40
1.45
0.053
0.055
0.057
0.37
0.45
0.012
0.014
0.018
0.20
0.004
0.006
0.008
D
12.00
0.472
D1
10.00
0.394
D3
8.00
0.315
e
0.80
0.031
E
12.00
0.472
E1
10.00
0.394
E3
8.00
0.315
L
0.45
0.60
0.75
OUTLINE AND
MECHANICAL DATA
MAX.
0.018
0.024
L1
1.00
K
0°(min.), 3.5°(typ.), 7°(max.)
0.030
0.039
TQFP44 (10 x 10)
D
D1
A
A2
A1
33
23
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
21/23
TDA7437
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.45
A1
0.25
A2
1.95
B
0.096
0.010
2.10
0.077
0.30
0.45
0.012
0.018
c
0.13
0.23
0.005
0.009
D
12.95
13.20
13.45
0.51
0.52
0.53
D1
9.90
10.00
10.10
0.390
0.394
0.398
2.00
0.079
D3
8.00
0.315
e
0.80
0.031
0.083
E
12.95
13.20
13.45
0.510
0.520
0.530
E1
9.90
10.00
10.10
0.390
0.394
0.398
E3
8.00
L
0.65
L1
OUTLINE AND
MECHANICAL DATA
MAX.
0.80
0.315
0.95
0.026
1.60
K
0.031
0.037
0.063
PQFP44 (10 x 10)
0°(min.), 7°(max.)
D
D1
A
D3
A2
A1
23
33
22
34
0.10mm
.004
44
B
E
E1
B
E3
Seating Plane
12
11
1
C
L
L1
e
K
PQFP44
22/23
TDA7437
Purchase of I2C Components of STMicrolectronics,
conveys a license under the Philips I2C Patent
2
Rights to use these components in an I C system, provided that the system conforms to the I 2C
Standard Specifications as defined by Philips.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
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23/23