STMICROELECTRONICS TDA7310

TDA7310

SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER:
- 4 STEREO INPUTS
- ONE DIFFERENTIAL STEREO INPUT FOR
REMOTE SOURCES
SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTION TO DIFFERENT SOURCES
INPUT AND OUTPUT FOR EXTERNAL
EQUALIZER OR NOISE REDUCTION SYSTEM
VOLUME CONTROL IN 1.25dB STEPS
LOUDNESS FUNCTION
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS
SELECTABLE CHIP ADDRESS DEDICATED
PIN
PQFP44 (10 x 10)
ORDERING NUMBER: TDA7310
DESCRIPTION
The TDA7310 is a volume, tone (bass and treble)
and fader (front/rear) processor for high quality audio
applications in car radio and Hi-Fi systems.
Loudness and selectable input gain are provided.
The control of all fuctions is accomplished by serial
bus microprocessor interface.
The AC signal setting is obtained by resistor networks
andswitches combined with operationalamplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and DC stepping are obtained.
PIN CONNECTION (Top view)
November 1999
1/15
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA7310
TEST CIRCUIT
THERMAL DATA
Symbol
R th j-pins
Description
Thermal Resistance Junction-pins
Value
Unit
85
°C/W
max
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Operating Supply Voltage
T amb
Ambient Temperature
Tstg
Storage Temperature Range
Value
Unit
10.2
V
-40 to 85
°C
-55 to +150
°C
QUICK REFERENCE DATA
Symbol
Min.
Typ.
Max.
VS
Supply Voltage
Parameter
6
9
10
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
%
S/N
Signal to Noise Ratio
106
dB
SC
Channel Separation f = 1KHz
103
Volume Control
1.25dB step
Bass and Treble Control
2dB step
Fader and Balance Control
Input Gain
6.25dB step
Mute Attenuation
2/15
1.25dB step
Unit
V
Vrms
dB
-78.75
0
dB
-14
+14
dB
-38.75
0
dB
0
18.75
dB
100
dB
RIGHT
INPUTS
CD
LEFT
INPUTS
R5
L5
L3
L4
C3
C4
10µF
21
R2
R1
C10
C11
4x
2.2µF
20
R3
C9
8
VCC
24
19
R4
18
17
16
25
C8
4.7µF
C7
C6
SGND
4.7µF
C5
27
L2
C2
26
28
4x
2.2µF
C1
L1
AGND
9
C12
SUPPLY
22µF
CREF
7
R1
R2
R3
R4
R5
L5
L4
L3
L2
L1
OUT(R)
15
C13 2.2µF
IN(R)
14
29
30
INPUT
SELECTOR
+ GAIN
IN(L)
OUT(L)
C14 2.2µF
39
C15
100nF
LOUD(R)
VOL
+ LOUD
VOL
+ LOUD
40
38
LOUD SW
BASS
RB
31
TREBLE(L)
TREBLE
10
BIN(L)
C22
2.7nF
35
5.6K
13
TREBLE
100nF
BIN(R)
C18
R1
100nF
BOUT(R)
C17
36
RB
BASS
C21
2.7nF
TREBLE(R)
SERIAL BUS DECODER + LATCHES
32
BOUT(L)
C20
R2
100nF
5.6K
C19
LOUD(L)
100nF
C16
100nF
MUTE
SPKR
ATT
D94AU170
MUTE
SPKR
ATT
50K
MUTE
SPKR
ATT
MUTE
SPKR
ATT
41
43
3
4
5
6
37
42
2
+VCC
BUS
OUT
RIGHT REAR
OUT
RIGHT FRONT
DIGGND
SDA
SEN
SCL
ADDR
OUT
LEFT REAR
OUT
LEFT FRONT
TDA7310
BLOCK DIAGRAM
3/15
TDA7310
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, GV=0dB, f = 1KHz
unless otherwise specified) (refer to the test circuit)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
6
9
10
V
IS
Supply Current
4
8
11
mA
Ripple Rejection
60
85
SVR
dB
INPUT SELECTORS
R II
V CL
CMRR
Input Resistance
Input 1, 2, 3, 4
50
KΩ
Differential Input
10
KΩ
2.5
Vrms
65
dB
100
dB
Clipping Level
2
Common Mode Rejection
Differential Input
INS
Input Separation (2)
RL
80
Output Load resistance
2
GINmin
Min. Input Gain
-1
GINmax
Max. Input Gain
GSTEP
Step Resolution
eIN
Input Noise
VDC
DC Steps
KΩ
0
1
18.75
G = 18.75dB
dB
dB
6.25
dB
2
µV
adjacent gain steps
4
mV
G = 18.75 to Mute
4
mV
Input Resistance
33
kΩ
Control Range
75
dB
VOLUME CONTROL
R IN
C RANGE
AVMIN
Min. Attenuation
AVMAX
Max. Attenuation
ASTEP
Step Resolution
EA
Attenuation Set Error
ET
Tracking Error
VDC
DC Steps
-1
0
1
75
1.25
AV = 0 to -20dB
AV = -20 to -60dB
-1.25
-3
0
dB
1.25
2
2
adjacent attenuation steps
From 0dB to AVmax
dB
dB
dB
dB
dB
0.1
0.5
mV
mV
Control Range
37.5
dB
Step Resolution
1.25
SPEAKER ATTENUATORS
Attenuation set error
Output Mute Attenuation
DC Steps
dB
1.5
80
adjacent att. steps
from 0 to mute
dB
100
dB
0
1
mV
mV
+14
dB
BASS CONTROL (1)
Control Range
4/15
Step Resolution
2
dB
RB
Internal Feedback Resistance
50
KΩ
VDC
DC Steps
0.1
mV
adjacent control steps
TDA7310
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
TREBLE CONTROL (1)
Control Range
Step Resolution
VDC
DC Steps
adjacent control steps
+14
dB
2
dB
0.1
mV
2.5
Vrms
AUDIO OUTPUTS
Clipping Level
d = 0.3%
Output Load Resistance
2
KΩ
Output Load Capacitance
Output resistance
DC Voltage Level
4.2
10
nF
75
120
Ω
4.5
4.8
V
2.5
5
15
µV
µV
GENERAL
e NO
S/N
d
Sc
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB
Signal to Noise Ratio
all gains = 0dB; VO = 1Vrms
106
dB
Distortion
VIN = 1Vrms
0.01
%
Channel Separation left/right
Total Tracking error
80
AV = 0 to -20dB
-20 to -60 dB
103
0
0
dB
1
2
dB
dB
1
V
BUS INPUTS
V IL
Input Low Voltage
VIH
Input High Voltage
VO
Output Voltage SDA
Acknowledge
3
V
IO = 1.6mA
0.4
V
1
V
+5
µA
LOUDNESS SWITCH
V IL
Input Low Voltage
VIH
Input High Voltage
3
IIN
Input Current
-5
DC Step
ON ← → OFF position
V
0.1
mV
Loudness OFF = pin38 Open;
Loudness ON = pin 38 Closed to GND
ADDRESS PIN (Internal 50KΩ pull down resistor)
V IL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
1
VCC -1V
V
V
µA
Notes:
(1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2µF capacitor.
5/15
TDA7310
APPLICATION SUGGESTION (see to Test circuit)
Component
Recc. Value
Purpose
C1 to C4,
C8 to C11
2.2µF
THD optimization at low
frequencies
Worse THD at very low
frequencies
C5, C7
C6
4.7µF
10µF
CMRR optimization
differential input
Worse CMRR for ratio not equal to 1⁄2
C12
22µF
C REF • SVR optimization
< -66 dB
Better SVR at low
frequencies
Worse SVR at low
frequencies
C13, C14
2.2µF
Decoupling Input-Output
if external equalizer is
not used
C15, C16
100nF
Loudness characteristic
C17, C18
R1
C!9, C20
R2
100nF
5.6kΩ
100nF
5.6kΩ
Bass Filter
(standard T - type)
cut freq. = 100Hz
C21
C22
2.7nF
Treble Filter
Higher cut frequency
Lower cut frequency
Figure 1: Loudness versus Volume Attenuation
6/15
Smaller than Recc. Value
Larger than
Figure 2: Loudnessversus Frequency
(CLOUD = 100nF)
TDA7310
Figure 3: Loudness versus External Capacitors
Figure 4: Noise vs. Volume/Gain Settings
LOUDNESS
VS = 9V
Volume = -40dB
All other control flat
Cin = 2.2µF
Figure 5: Signal to Noise Ratio vs. Volume
Setting
Figure 6: Distortion vs. Load Resistance
7/15
TDA7310
Figure 7 : Channel Separation (L → R) vs.
Frequency
Figure 8 : Input Separation (L1 → L2, L3, L4) vs.
Frequency
Figure 9 : Supply Voltage Rejection vs.
Frequency
Figure 10: Output Clipping Level vs. Supply
Voltage
8/15
TDA7310
Figure 11: Quiescent Current vs. Supply Voltage
Figure 12: Supply Current vs. Temperature
Figure 13: Bass Resistance vs. Temperature
Figure 14: Typical Tone Response (with the ext.
components indicated in the test
circuit)
9/15
TDA7310
APPLICATION INFORMATION (continued)
SERIAL BUS INTERFACE
S-BUS Interface and I2CBUS Compability
Data transmission from microprocessor to the
TDA7310 and viceversa takes place thru the 3wire S-BUS interface, consisting of the three lines
SDA, SCL, SEN. If SDA and SEN inputs are
short-circuited together, then the TDA7310 appears as a standard I 2CBUS slave.
According to I2CBUS specification the S-BUS
lines are connected to a positive supply voltage
via pull-up resistors.
Data Validity
As shown in fig. 15, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Figure 15: Data Validity on the I2CBUS
Figure 16: Timing Diagram of S-BUS and I2CBUS
Start and Stop Conditions
I2CBUS:
as shown in fig. 16 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
S-bus:
the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line
(1 → 0 / 0 → 1)wile the SCL line is at the HIGH
level.
The SDA line is only allowed to change during the
time the SCL line is low (points 2, 3, 4, 5). after
the start information (point 1) the SEN line returns
to the HIGH level and remains uncharged for all
the time the transmission is performed.
Byte Fornat
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on
Figure 17: Acknowledge on the I2CBUS
10/15
the SDA line during the acknowledge clock pulse
(see fig. 17). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock.
TDA7310
APPLICATION INFORMATION (continued)
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7310
address (the 8th bit of the byte must be 0). The
TDA7310 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7310 ADDRESS
S
MSB
first byte
1
0
0
0
LSB
1
0
A
MSB
LSB
0 ACK
DATA
MSB
LSB
DATA
ACK
ACK P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION
Chip address
1
MSB
0
0
0
1
0
A
0
LSB
A = LOGIC LEVEL ON PIN ADDR
DATA BYTES
MSB
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
B2
0
1
0
1
0
1
1
B1
B1
B1
B1
B1
G1
0
1
B0
B0
B0
B0
B0
G0
C3
C3
A2
A2
A2
A2
A2
S2
C2
C2
A1
A1
A1
A1
A1
S1
C1
C1
LSB
A0
A0
A0
A0
A0
S0
C0
C0
FUNCTION
Volume control
Speaker ATT LR
Speaker ATT RR
Speaker ATT LF
Speaker ATT RF
Audio switch
Bass control
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
STATUS AFTER POWER ON RESET
Volume
speaker
audio Switch
bass
treble
gain
-77.5dB
-37.5dB
Stereo 5
+2dB
+2dB
0dB
11/15
TDA7310
SOFTWARE SPECIFICATION (continued)
DATA BYTES (detailed description)
Volume
MSB
0
0
LSB
0
0
B2
B1
B0
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2
A1
A0
FUNCTION
Volume 1.25dB steps
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
Volume 10dB steps
0
-10
-20
-30
-40
-50
-60
-70
For example a volume of -45dB is given by:
0 0 1 0 0 1 0 0
Speaker Attenuators
MSB
1
1
1
1
LSB
0
0
1
1
0
1
0
1
B1
B1
B1
B1
B0
B0
B0
B0
0
0
1
1
0
1
0
1
1
1
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
-10
-20
-30
1
For example attenuation of 25dB on speaker RF is given by:
1 0 1 1 0 1 0 0
12/15
FUNCTION
Speaker LF
Speaker RF
Speaker LR
Speaker RR
1
1
Mute
TDA7310
Audio Switch
MSB
0
LSB
1
0
G1
G0
S1
S0
Audio Switch
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Stereo 1
Stereo 2
Stereo 3
Stereo 4
Stereo 5
Not allowed
Not allowed
Not allowed
+18.75dB
+12.5dB
+6.25dB
0dB
0
1
0
1
0
0
1
1
FUNCTION
S2
For example to select the stereo 2 input with a gain of +12.5dB the 8bit string is:
0 1 0 0 1 0 0 1
Bass and Treble
0
0
1
1
1
1
0
1
C3
C3
C2
C2
C1
C1
C0
C0
Bass
Treble
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-14
-12
-10
-8
-6
-4
-2
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
2
4
6
8
10
12
14
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string:
0 1 1 0 0 0 1 0
Purchase of I2C Components from STMicroelectronics, conveys a license under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I 2C
Standard Specifications as defined by Philips.
13/15
TDA7310
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.45
A1
0.25
A2
1.95
B
0.096
0.010
2.10
0.077
0.30
0.45
0.012
0.018
c
0.13
0.23
0.005
0.009
D
12.95
13.20
13.45
0.51
0.52
0.53
D1
9.90
10.00
10.10
0.390
0.394
0.398
2.00
0.079
D3
8.00
0.315
e
0.80
0.031
0.083
E
12.95
13.20
13.45
0.510
0.520
0.530
E1
9.90
10.00
10.10
0.390
0.394
0.398
E3
8.00
L
0.65
L1
OUTLINE AND
MECHANICAL DATA
MAX.
0.80
0.315
0.95
0.026
1.60
K
0.031
0.037
0.063
PQFP44 (10 x 10)
0°(min.), 7°(max.)
D
D1
A
D3
A2
A1
23
33
22
34
0.10mm
.004
44
B
E
E1
B
E3
Seating Plane
12
11
1
C
L
L1
e
K
PQFP44
14/15
TDA7310
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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