STMICROELECTRONICS TDA7318

TDA7318

DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
INPUT MULTIPLEXER:
- 4 STEREO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTION TO DIFFERENT SOURCES
INPUT AND OUTPUT FOR EXTERNAL
EQUALIZER OR NOISE REDUCTION SYSTEM
VOLUME CONTROL IN 1.25dB STEPS
TREBLE AND BASS CONTROL
FOUR SPEAKER ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1.25dB STEPS FOR BALANCE AND
FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SERIALI2CBUS
DESCRIPTION
The TDA7318 is a volume, tone (bass and treble)
balance (Left/Right) and fader (front/rear) processor
for quality audio applications in car radio and Hi-Fi
systems.
DIP28
SO28
ORDERING NUMBERS:
TDA7318
TDA7318D
Selectable input gain is provided. Control is accomplished by serial I2C bus microprocessor interface.
The AC signal setting is obtained by resistor networks
andswitches combined with operationalamplifiers.
Thanks to the used BIPOLAR/CMOS Tecnology,
Low Distortion, Low Noise and Low DC stepping are
obtained.
PIN CONNECTION (Top view)
November 1999
1/14
TDA7318
TEST CIRCUIT
THERMAL DATA
Symbol
R th j-pins
Description
Thermal Resistance Junction-pins
SO28
DIP28
Unit
85
65
°C/W
max
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Operating Supply Voltage
T amb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Value
Unit
10.2
V
-40 to 85
°C
-55 to +150
°C
QUICK REFERENCE DATA
Symbol
Min.
Typ.
Max.
VS
Supply Voltage
Parameter
6
9
10
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio
106
SC
Channel Separation f = 1KHz
103
Volume Control
1.25dB step
Bass and Treble Control
2db step
Fader and Balance Control
Input Gain
6.25dB step
Mute Attenuation
2/14
1.25dB step
Unit
V
Vrms
0.1
%
dB
dB
-78.75
0
dB
-14
+14
dB
-38.75
0
dB
0
18.75
dB
100
dB
RIGHT
INPUTS
LEFT
INPUTS
4x
2.2µF
R1
R3
C6
C8
R4
C5
R2
L4
C4
C7
L3
C3
VCC
2
11
10
9
8
12
13
14
C2
L2
15
4x
2.2µF
C1
L1
AGND
3
SUPPLY
R1
R2
R3
R4
L4
L3
L2
L1
16
17
22µF
C9
C10 2.2µF
6
IN(R)
7
OUT(R)
CREF
1
INPUT
SELECTOR
+ GAIN
IN(L)
OUT(L)
C11 2.2µF
VOL
VOL
100nF
C13
100nF
C12
R1
BIN(R)
20
RB
BASS
5.6K
100nF
C15
BIN(L)
TREBLE(L)
TREBLE
4
C17
2.7nF
5
2.7nF
C16
TREBLE(R)
TREBLE
I 2C BUS DECODER + LATCHES
BASS
RB
18
R2
BOUT(R)
21
19
100nF
C14
BOUT(L)
5.6K
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
MUTE
SPKR
ATT
D95AU265
22
24
26
27
28
23
25
BUS
OUT
RIGHT REAR
OUT
RIGHT FRONT
DIGGND
SDA
SCL
OUT
LEFT REAR
OUT
LEFT FRONT
TDA7318
BLOCK DIAGRAM
3/14
TDA7318
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ,
RG = 600Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
6
9
10
V
IS
Supply Current
4
8
11
mA
Ripple Rejection
60
85
SVR
dB
INPUT SELECTORS
R II
Input Resistance
35
50
V CL
Clipping Level
Input 1, 2, 3, 4
2
2.5
Vrms
SIN
Input Separation (2)
80
100
dB
RL
Output Load resistance
pin 7, 17
70
2
KΩ
KΩ
GINmin
Min. Input Gain
-1
0
1
dB
GINmax
Max. Input Gain
17
18.75
20
dB
GSTEP
Step Resolution
5
6.25
7.5
eIN
Input Noise
VDC
DC Steps
G = 18.75dB
adjacent gain steps
4
G = 18.75 to Mute
4
dB
µV
2
20
mV
mV
VOLUME CONTROL
R IV
C RANGE
Input Resistance
20
33
50
kΩ
Control Range
70
75
80
dB
dB
AVMIN
Min. Attenuation
-1
0
1
AVMAX
Max. Attenuation
70
75
80
dB
ASTEP
Step Resolution
0.5
1.25
1.75
dB
-1.25
-3
0
1.25
2
dB
dB
EA
Attenuation Set Error
ET
Tracking Error
VDC
DC Steps
Av = 0 to -20dB
Av = -20 to -60dB
adjacent attenuation steps
From 0dB to Av max
0
0.5
2
dB
3
7.5
mV
mV
SPEAKER ATTENUATORS
Crange
Control Range
35
37.5
40
dB
SSTEP
Step Resolution
0.5
1.25
1.75
dB
1.5
dB
80
100
EA
AMUTE
VDC
Attenuation set error
Output Mute Attenuation
DC Steps
adjacent att. steps
from 0 to mute
dB
0
1
3
10
mV
mV
dB
BASS CONTROL (1)
Gb
BSTEP
RB
Control Range
+12
+14
+16
Step Resolution
Max. Boost/cut
1
2
3
dB
Internal Feedback Resistance
34
44
58
KΩ
+13
+14
+15
dB
1
2
3
dB
TREBLE CONTROL (1)
Gt
TSTEP
4/14
Control Range
Step Resolution
Max. Boost/cut
TDA7318
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
2
2.5
Max.
Unit
AUDIO OUTPUTS
VOCL
Clipping Level
RL
Output Load Resistance
CL
Output Load Capacitance
d = 0.3%
Vrms
2
KΩ
10
nF
ROUT
Output resistance
30
75
120
Ω
VOUT
DC Voltage Level
4.2
4.5
4.8
V
2.5
5
15
µV
µV
GENERAL
e NO
Output Noise
BW = 20-20KHz, flat
output muted
all gains = 0dB
3
µV
Signal to Noise Ratio
all gains = 0dB; VO = 1Vrms
106
dB
Distortion
AV = 0, VIN = 1Vrms
AV = -20dB VIN = 1Vrms
V IN = 0.3Vrms
0.01
0.09
0.04
A curve all gains = 0dB
S/N
d
Sc
Channel Separation left/right
Total Tracking error
80
AV = 0 to -20dB
-20 to -60 dB
0.1
0.3
%
%
%
1
2
dB
dB
1
V
103
0
0
dB
BUS INPUTS
V IL
Input Low Voltage
VIH
Input High Voltage
3
IIN
Input Current
-5
VO
Output Voltage SDA
Acknowledge
IO = 1.6mA
V
+5
µA
0.4
V
Notes:
(1) Bass and Treble response see attached diagram (fig.19). The center frequency and quality of the resonance behaviour can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network
(2) The selected input is grounded thru the 2.2µF capacitor.
Figure 1: Noise vs. Volume/Gain Settings
Figure 2: Signal to Noise Ratio vs. Volume
Setting
5/14
TDA7318
Figure 3: Distortion & Noise vs. Frequency
Figure 4: Distortion & Noise vs. Frequency
Figure 5: Distortion vs. Load Resistance
Figure 6: Channel Separation (L → R) vs.
Frequency
Figure 7: Input Separation (L1 → L2, L3, L4) vs.
Frequency
Figure 8: Supply Voltage Rejection vs.
Frequency
6/14
TDA7318
Figure 9: Output Clipping Level vs. Supply
Voltage
Figure 10: Quiescent Current vs. Supply Voltage
Figure 11: Supply Current vs. Temperature
Figure 12: Bass Resistance vs. Temperature
Figure 13: Typical Tone Response (with the ext.
components indicated in the test
circuit)
7/14
TDA7318
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7318 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 14, the data on the SDA line
must be stable during the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Start and Stop Conditions
As shown in fig.15 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 14: Data Validity on the I2CBUS
Figure 15: Timing Diagram of I2CBUS
Figure 16: Acknowledge on the I2CBUS
8/14
knowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 16). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can generate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
TDA7318
address (the 8th bit of the byte must be 0). The
TDA7318 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7318
TDA7318 ADDRESS
S
MSB
first byte
1
0
0
0
LSB
1
0
0
MSB
LSB
DATA
0 ACK
MSB
LSB
DATA
ACK
ACK P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION
Chip address
1
MSB
0
0
0
1
0
0
0
LSB
DATA BYTES
MSB
0
1
1
1
1
0
0
0
LSB
0
1
1
0
0
1
1
1
B2
0
1
0
1
0
1
1
B1
B1
B1
B1
B1
G1
0
1
B0
B0
B0
B0
B0
G0
C3
C3
A2
A2
A2
A2
A2
S2
C2
C2
A1
A1
A1
A1
A1
S1
C1
C1
A0
A0
A0
A0
A0
S0
C0
C0
FUNCTION
Volume control
Speaker ATT LR
Speaker ATT RR
Speaker ATT LF
Speaker ATT RF
Audio switch
Bass control
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 6.25dB steps
9/14
TDA7318
SOFTWARE SPECIFICATION (continued)
DATA BYTES (detailed description)
Volume
MSB
0
0
LSB
0
0
B2
B1
B0
B2
B1
B0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A2
A1
A0
FUNCTION
Volume 1.25dB steps
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
Volume 10dB steps
0
-10
-20
-30
-40
-50
-60
-70
For example a volume of -45dB is given by:
0 0 1 0 0 1 0 0
Speaker Attenuators
MSB
1
1
1
1
LSB
0
0
1
1
0
1
0
1
B1
B1
B1
B1
B0
B0
B0
B0
0
0
1
1
0
1
0
1
1
1
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.5
-3.75
-5
-6.25
-7.5
-8.75
0
-10
-20
-30
1
For example attenuation of 25dB on speaker RF is given by:
1 0 1 1 0 1 0 0
10/14
FUNCTION
Speaker LF
Speaker RF
Speaker LR
Speaker RR
1
1
Mute
TDA7318
Audio Switch
MSB
0
LSB
1
0
G1
G0
S1
S0
Audio Switch
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Stereo 1
Stereo 2
Stereo 3
Stereo 4
Not allowed
Not allowed
Not allowed
Not allowed
+18.75dB
+12.5dB
+6.25dB
0dB
0
1
0
1
0
0
1
1
FUNCTION
S2
For example to select the stereo 2 input with a gain of +12.5dB the 8bit string is:
0 1 0 0 1 0 0 1
Bass and Treble
0
0
1
1
1
1
0
1
C3
C3
C2
C2
0
0
0
0
1
1
1
1
C1
C1
0
0
1
1
0
0
1
1
C0
C0
0
1
0
1
0
1
0
1
Bass
Treble
-14
-12
-10
-8
-6
-4
-2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
2
4
6
8
10
12
14
C3 = Sign
For example Bass at -10dB is obtained by the following 8 bit string:
0 1 1 0 0 0 1 0
11/14
TDA7318
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
c1
0.020
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
12/14
OUTLINE AND
MECHANICAL DATA
8 ° (max.)
SO28
TDA7318
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
a1
0.63
0.025
b
0.45
0.018
b1
0.23
b2
0.31
D
E
0.012
0.009
1.27
0.050
37.34
15.2
16.68
1.470
0.598
0.657
e
2.54
0.100
e3
33.02
1.300
F
MAX.
OUTLINE AND
MECHANICAL DATA
14.1
0.555
I
4.445
0.175
L
3.3
0.130
DIP28
13/14
TDA7318
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
2
2
2
Purchase of I C Components of STMicrolectronics, conveys a license under the Philips I C Patent Rights to use these components in an I C
system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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