TDA7449 TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR INPUT MULTIPLEXER - 2 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT TREBLE, AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION The TDA7449 is a volume tone (bass and treble) balance (Left/Right) processor for quality audio applications in TV systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. DIP20 ORDERING NUMBER: TDA7449 The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. BLOCK DIAGRAM MUXOUTL TREBLE(L) 10 L-IN1 16 BIN(L) BOUT(L) 15 8 14 RB 100K L-IN2 9 100K R-IN1 VOLUME G SPKR ATT LEFT BASS 2 I CBUS DECODER + LATCHES 20 18 100K R-IN2 6 100K 5 19 0/30dB 2dB STEP 7 TREBLE VOLUME G TREBLE SPKR ATT RIGHT BASS 4 LOUT SCL SDA DIG_GND ROUT VREF 2 SUPPLY INPUT MULTIPLEXER + GAIN RB 11 MUXOUTR April 1999 17 TREBLE(R) 12 13 BIN(R) BOUT(R) 3 VS AGND 1 CREF D98AU847A 1/17 TDA7449 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value 10.5 V Tamb Operating Ambient Temperature -10 to 85 °C Tstg Storage Temperature Range -55 to 150 °C VS Operating Supply Voltage Unit PIN CONNECTION CREF 1 20 SDA VS 2 19 SCL PGND 3 18 DIG_GND ROUT 4 17 TREBLE(R) LOUT 5 16 TREBLE(L) R_IN2 6 15 BIN(L) R_IN1 7 14 BOUT(L) L_IN1 8 13 BOUT(R) L_IN2 9 12 BIN(R) 10 11 MUXOUT(R) MUXOUT(L) D98AU848 THERMAL DATA Symbol R th j-pin Parameter Thermal Resistance Junction-pins Value Unit 150 °C/W QUICK REFERENCE DATA Symbol Parameter Min. Typ. Max. 9 10.2 VS Supply Voltage 6 VCL Max. input signal handling 2 Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 SC Channel Separation f = 1KHz Volume Control Treble Control (1dB step) (2dB step) 0.1 % dB 90 dB 0 30 dB -47 0 dB dB -14 +14 Bass Control (2dB step) -14 +14 dB Balance Control -79 0 dB Mute Attenuation 2/17 V Vrms THD Input Gain in (2dB step) Unit 1dB step 100 dB TDA7449 ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω, all controls flat (G = 0dB), unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 6 9 10.2 60 7 90 mA dB THD = 0.3% 2 100 2.5 KΩ Vrms The selected input is grounded through a 2.2µ capacitor 80 100 dB -1 0 30 2 1 dB dB dB 45 45 0.5 47 47 1 49 49 1.5 dB dB dB -1.0 -1.5 0 0 0 1.0 1.5 1 dB dB dB 2 3 80 0 0 0.5 100 dB mV mV dB +12.0 1 +14.0 2 +16.0 3 dB dB 18.75 25 31.25 KΩ +13.0 1 +14.0 2 +15.0 3 dB dB SUPPLY VS Supply Voltage IS SVR Supply Current Ripple Rejection V INPUT STAGE R IN V CL Input Resistance Clipping Level SIN Input Separation Ginmin Ginman Gstep Minimum Input Gain Maximum Input Gain Step Resolution VOLUME CONTROL C RANGE AVMAX ASTEP Control Range Max. Attenuation Step Resolution EA Attenuation Set Error ET Tracking Error VDC DC Step Amute Mute Attenuation AV = 0 to -24dB AV = -24 to -47dB AV = 0 to -24dB AV = -24 to -47dB adjacent attenuation steps from 0dB to AV max BASS CONTROL (1) Gb BSTEP RB Control Range Step Resolution Max. Boost/cut Internal Feedback Resistance TREBLE CONTROL (1) Gt TSTEP Control Range Step Resolution Max. Boost/cut SPEAKER ATTENUATORS C RANGE Control Range SSTEP EA Step Resolution Attenuation Set Error VDC Amute DC Step Mute Attenuation 76 AV = 0 to -20dB AV = -20 to -56dB dB 0.5 -1.5 -2 1 0 0 1.5 1.5 2 dB dB dB 0 100 3 80 mV dB adjacent attenuation steps NOTE1: 1) The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device. 2) BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry. 3/17 TDA7449 ELECTRICAL CHARACTERISTICS (continued.) Symbol Parameter Test Condition Min. Typ. 2.1 2 10 2.6 Max. Unit AUDIO OUTPUTS VCLIP RL RO Clipping Level Output Load Resistance Output Impedance VDC DC Voltage Level d = 0.3% VRMS KΩ 70 Ω V 5 15 µV 0 0 106 1 2 dB dB dB 40 3.8 GENERAL ENO Output Noise All gains = 0dB; BW = 20Hz to 20KHz flat Et Total Tracking Error S/N Signal to Noise Ratio AV = 0 to -24dB AV = -24 to -47dB All gains 0dB; VO = 1VRMS ; SC d Channel Separation Left/Right Distortion AV = 0; V I = 1VRMS ; 80 100 0.01 0.08 dB % BUS INPUT V IL VIH IIN VO 4/17 Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 VIN = 0.4V IO = 1.6mA 3 -5 0.4 5 0.8 V V µA V TDA7449 P.C.Board TEST CIRCUIT R2 2K C9 5.6nF 150nF J5 IN1L C7 MUXOUTL J3 TREBLE(L) 10 RCA 1 2 J4 3 4 5 330nF 16 C8 BIN(L) BOUT(L) 15 14 GND IN1L GND IN2L GND CON3 C3 0.47µF L-IN2 RB 8 OUT_L 100K 5 LOUT 9 C4 0.47µF 100K VOLUME G TREBLE OUT_ R SPKR ATT LEFT BASS J2 RCA 0/30dB 2dB STEP J1 3 4 IN2R GND IN1R GND R-IN2 18 DIG_GND 19 SCL 20 SDA VOLUME G TREBLE BASS SPKR ATT RIGHT C2 0.47µF 4 CON4 1 2 3 J6 4 ROUT 100K SUPPLY MOUTL GND RB 11 MUXOUTR 17 TREBLE(R) MOUTR 13 BOUT(R) C5 2 C13 100nF R3 30 C12 22µF AGND 1 VS 12 BIN(R) 3 J10 4 4 7 INPUT MULTIPLEXER + GAIN 2 3 CON4 100K 3 1 2 VREF CON J5 JP1 JUMPER 6 C1 0.47µF R-IN1 I2CBUS DECODER + LATCHES 1 CON4 +9 V 2 J9 OUT_L L-IN1 IN1R 1 J8 OUT_R +V8 1 +9V GND 2 J7 CON2 CREF C6 GND C10 5.6nF 150nF R1 330nF 2K C11 10µF D98AU849A 5/17 TDA7449 APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7449 audioprocessor provides 2 bands tones control. ternal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: FC = AV = Bass, Stages 2 ⋅ π ⋅√ Ri, R2, C1, C2 R2 C2 + R2 C1 + Ri C1 Q= The Bass cell has an internal resistor Ri = 25KΩ typical. Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.1 refers to basic T Type Bandpass Filter starting from the filter component values (R1 inFigure 1. Ri internal IN OUT C1 C2 R2 D95AU313 Figure 2: THD vs. frequency 6/17 1 R2 C1 + R2 C2 √ Ri R2 + C1 C2 R2 C1 + R2 C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: C1 = AV − 1 2 ⋅ π ⋅ Ri ⋅ Q R2 = C2 = Q2 ⋅ C1 (AV − 1) Q2 AV − 1 − Q2 2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. CREF The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. Figure 3: THD vs. RLOAD TDA7449 Figure 4: Channel separation vs. frequency Figure 5: Bass response Ri = 25kΩ C1 = 150nF C2 = 330nF R2 = 2kΩ Figure 6: Treble response 7/17 TDA7449 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7449 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 8/17 knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. TDA7449 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7449 CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X DATA 1 to DATA n LSB X X B DATA MSB ACK LSB DATA ACK P D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment EXAMPLES No Incremental Bus The TDA7449 receives a start condition, the cor- CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 rect chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. 0 0 MSB ACK X DATA LSB X X MSB 0 D3 D2 D1 D0 ACK LSB DATA ACK P D96AU421 Incremental Bus The TDA7449 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 SUBADDRESS from ”XXX1000” to ”XXX1111” of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. 0 0 MSB ACK X DATA 1 to DATA n LSB X X 1 D3 D2 D1 D0 ACK MSB LSB DATA ACK P D96AU422 9/17 TDA7449 POWER ON RESET CONDITION INPUT SELECTION IN2 INPUT GAIN 28dB VOLUME MUTE BASS 2dB TREBLE 2dB SPEAKER MUTE DATA BYTES Address = 88 HEX (ADDR:OPEN). FUNCTION SELECTION: First byte (subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X B 0 0 0 0 INPUT SELECT X X X B 0 0 0 1 INPUT GAIN X X X B 0 0 1 0 VOLUME X X X B 0 0 1 1 NOT ALLOWED X X X B 0 1 0 0 BASS X X X B 0 1 0 1 TREBLE X X X B 0 1 1 0 SPEAKER ATTENUATE ”R” X X X B 0 1 1 1 SPEAKER ATTENUATE ”L” B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON’T CARE INPUT SELECTION MSB LSB INPUT MULTIPLEXER D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 0 0 NOT ALLOWED X X X X X X 0 1 NOT ALLOWED X X X X X X 1 0 IN2 X X X X X X 1 1 IN1 10/17 TDA7449 DATA BYTES (continued) INPUT GAIN SELECTION MSB D7 D6 D5 D4 LSB INPUT GAIN D3 D2 D1 D0 2dB STEPS 0 0 0 0 0dB 0 0 0 1 2dB 0 0 1 0 4dB 0 0 1 1 6dB 0 1 0 0 8dB 0 1 0 1 10dB 0 1 1 0 12dB 0 1 1 1 14dB 1 0 0 0 16dB 1 0 0 1 18dB 1 0 1 0 20dB 1 0 1 1 22dB 1 1 0 0 24dB 1 1 0 1 26dB 1 1 1 0 28dB 1 1 1 1 30dB LSB VOLUME 1dB STEPS GAIN = 0 to 30dB VOLUME SELECTION MSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 X 1 1 1 -40dB X X X MUTE VOLUME = 0 to 47dB/MUTE 11/17 TDA7449 DATA BYTES (continued) BASS SELECTION MSB D7 D6 D5 D4 LSB BASS D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB LSB TREBLE D3 D2 D1 D0 2dB STEPS 0 0 0 0 -14dB 0 0 0 1 -12dB 0 0 1 0 -10dB 0 0 1 1 -8dB 0 1 0 0 -6dB 0 1 0 1 -4dB 0 1 1 0 -2dB 0 1 1 1 0dB 1 1 1 1 0dB 1 1 1 0 2dB 1 1 0 1 4dB 1 1 0 0 6dB 1 0 1 1 8dB 1 0 1 0 10dB 1 0 0 1 12dB 1 0 0 0 14dB TREBLE SELECTION MSB D7 12/17 D6 D5 D4 TDA7449 DATA BYTES (continued) SPEAKER ATTENUATE SELECTION MSB D7 D6 D5 D4 D3 LSB SPEAKER ATTENUATION D2 D1 D0 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 1 1 1 X X X MUTE SPEAKER ATTENUATION = 0 to -79dB/MUTE PIN: 1 PINS: 4, 5 VS VS VS 20K 24 ROUT LOUT CREF 20µA 20K D96AU430 D96AU434 13/17 TDA7449 PINS: 6,7,8,9 PINS: 10,11 VS VS VS 20µA 20µA MUXOUT IN 100K GND VREF D96AU425 PINS: 12, 15 D96AU491 PINS: 13, 14 VS VS 20µA 20µA 44K 25K BOUT(L) BIN(L) BIN(R) D98AU850 PINS: 16, 17 BOUT(R) D96AU429 PIN: 19 VS 20µA 20µA SCL TREBLE(L) TREBLE(R) 50K D96AU433 D96AU424 14/17 TDA7449 PIN: 20 20µA SDA D96AU423 15/17 TDA7449 mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L OUTLINE AND MECHANICAL DATA 3.3 0.130 DIP20 Z 16/17 1.34 0.053 TDA7449 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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