STMICROELECTRONICS TDA7342N

TDA7342
Digitally controlled audio processor
Features
■
Input multiplexer
– Two stereo and one mono inputs
– One quasi differential input
– Selectable input gain for optimal adaptation
to different sources
■
Fully programmable loudness function
■
Volume control in 0.3dB steps including gain
up to 20dB
■
Zero crossing mute, soft mute and direct mute
■
Bass and treble control
■
Four speaker attenuators
– Four independent speakers control in
1.25dB steps for balance and fader facilities
– Independent mute function
■
All functions programmable via serial I2C bus
Description
The audioprocessor TDA7342 is an upgrade of
the TDA731X audioprocessor family.
LQFP32
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are
implemented. The soft Mute function can be
activated in two ways:
1.
Via serial bus (Mute byte, bit D0)
2.
Directly on pin 21 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
Order codes
Part number
Package
Packing
TDA7342N
LQFP32
Tube
TDA7342NTR
LQFP32
Tape and reel
November 2006
Rev 2
1/20
www.st.com
1
Contents
TDA7342
Contents
1
2
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
3
4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
TDA7342
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Speaker attenuators (LF, LR, RF, RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
TDA7342
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
4/20
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connections (Top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LQFP32 Mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TDA7342
Block diagram and pin descriptions
1
Block diagram and pin descriptions
1.1
Block diagram
Figure 1.
Block diagram
C13 47nF
C1
LEFT
INPUTS
L1
L2
13
IN(L)
LOUD(L)
16
15
9
21
C18
100nF
BIN(L)
18
C19 2.7nF
TREBLE(L)
32
17
SPKR
ATT
25
12
MUTE
L2
ZERO
CROSS +
MUTE
M
L3
SM
R2
4.7K
L1
C2
C6
OUT(L)
BOUT(L)
C17 100nF
C11
11
LOUD+
VOL
BASS
TREBLE
SPKR
ATT
L3
23
MUTE
CD
CD GND
10
28
INPUT
SELECTOR
+ GAIN
C3
C7
SOFT
MUTE
SERIAL BUS DECODER + LATCHES
27
26
RIGHT
INPUTS
C4
5
R3
M
8
M
R2
6
R1
7
ZERO
CROSS +
MUTE
R2
LOUD+
VOL
BASS
MUTE
TREBLE
SCL
SDA
BUS
DIGGND
22
SUPPLY
MUTE
30
31
VS
OUT
RIGHT FRONT
SPKR
ATT
R1
C5
29
3
2
4
14
CREF
OUT(R)
IN(R)
LOUD(R)
CSM
C12
47nF
10μF C9
C10
20
19
CSM
47nF
OUT
RIGHT REAR
1
BOUT(R)
C14
100nF
R1
BIN(R)
TREBLE(R)
D94AU104B
C15
100nF
C16
2.7nF
4.7K
Pin description
OUT LF
DIG GND
SDA
SCL
CREF
GND
VS
TR L
Pin connections (Top view)
32 31 30 29 28 27 26 25
TR R
1
24
OUT RF
IN R
2
23
OUT LR
OUT R
3
22
OUT RR
LOUD R
4
21
SM
IN R3
5
20
BOUT R
IN R2
6
19
BIN R
IN R1
7
18
BOUT L
MONO
8
17
BIN L
OUT L
IN L
CSM
IN L1
IN L2
IN L3
9 10 11 12 13 14 15 16
LOUD L
Figure 2.
CD GND
1.2
OUT
LEFT REAR
SPKR
ATT
R3
24
C8
MONO INPUT
OUT
LEFT FRONT
D94AU105A
5/20
Electrical specifications
TDA7342
2
Electrical specifications
2.1
Absolute maximum ratings
Table 1.
Absolute maximum ratings
Symbol
VS
Parameter
Operating supply voltage
Value
Unit
10.5
V
Tamb
Operating ambient temperature
-40 to 85
°C
Tstg
Storage temperature range
-55 to 150
°C
Value
Unit
150
°C/W
Table 2.
Thermal data
Symbol
Rth j-amb
Table 3.
Parameter
Thermal resistance junction-pins
Quick reference data
Symbol
Parameter
Min.
Typ.
Max.
Unit
6
9
10.2
V
2.1
2.6
VS
Supply voltage
VCL
Max. input signal handling
THD
Total harmonic distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to noise ratio
106
dB
SC
Channel separation
100
dB
Volume control 0.3dB step
0.08
%
-59.7
20
dB
Treble control 2dB step
-14
+14
dB
Bass control 2dB step
-10
+18
dB
-38.75
0
dB
0
11.25
dB
Fader and balance control 1.25dB step
Input gain 3.75dB step
Mute attenuation
Table 4.
Vrms
100
dB
Electrical characteristics
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer
to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
70
100
130
KΩ
2.1
2.6
VRMS
100
dB
Input selector
RI
VCL
6/20
Input resistance
Clipping level
d ≤ 0.3%
SI
Input separation
80
RL
Output load resistance
2
KΩ
GI MIN
Minimum input gain
-0.75
0
0.75
dB
GI MAX
Maximum input gain
10.25 11.25 12.25
dB
TDA7342
Electrical specifications
Table 4.
Electrical characteristics (continued)
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer
to the test circuit, unless otherwise specified.)
Symbol
Gstep
eN
VDC
Parameter
Test condition
Step resolution
Input noise
Min.
Typ.
Max.
Unit
2.75
3.75
4.75
dB
20Hz to 20 KHz unweighted
2.3
Adjacent gain steps
1.5
μV
10
mV
DC Steps
GIINto GIMAX
3
mV
Differential input (IN 3)
Input selector BIT D6 = 0
(0dB)
10
15
20
KΩ
Input selector BIT D6 = 1(6dB)
14
20
30
KΩ
Common mode rejection
ratio
VCM = 1VRMS; f =1KHz
48
75
dB
f = 10KHz
45
70
dB
d
Distortion
VI= 1VRMS
eIN
Input noise
20Hz to 20KHz; Flat; D6 = 0
RI
CMRR
GDIFF
Input resistance
0.01
0.08
%
μV
5
D6 = 0
-1
0
1
dB
D6 = 1
-7
-6
-5
dB
Differential gain
Volume control
RI
Input resistance
35
50
GMAX
Maximum gain
18.75
20
21.25
dB
AMAX
Maximum attenuation
57.7
59.7
62.7
dB
ASTEPC
Step resolution coarse
attenuation
0.5
1.25
2.0
dB
ASTEPF
Step resolution fine
attenuation
0.11
0.31
0.51
dB
G = 20 to -20dB
-1.25
0
1.25
dB
EA
Attenuation set error
G = -20 to -58dB
-3
2
dB
Et
Tracking error
2
dB
0
3
mV
0.5
5
mV
35
50
65
KΩ
Adjacent attenuation Steps
VDC
-3
KΩ
DC Steps
From 0dB to AMAX
Loudness control
RI
Internal resistor
Loud = On
AMAX
Maximum attenuation
17.5
18.75
20.0
dB
Astep
Step resolution
0.5
1.25
2.0
dB
Zero crossing mute
7/20
Electrical specifications
Table 4.
Electrical characteristics (continued)
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer
to the test circuit, unless otherwise specified.)
Symbol
VTH
AMUTE
VDC
TDA7342
Parameter
Zero crossing threshold
(1)
Test condition
Typ.
Max.
Unit
WIN = 11
20
mV
WIN = 10
40
mV
WIN = 01
80
mV
WIN = 00
160
mV
100
dB
Mute attenuation
DC Step
Min.
80
0dB to Mute
0
3
mV
Soft mute
AMUTE
TDON
Mute attenuation
ON Delay time
TDOFF
OFF current
VTHSM
Soft mute threshold
45
60
CCSM = 22nF; 0 to -20dB; I =
IMAX
0.7
1
1.7
ms
CCSM = 22nF; 0 to -20dB; I =
IMIN
20
35
55
ms
VCSM= 0V; I = IMAX
25
50
75
μA
VCSM= 0V; I = IMIN
RINT
Pull-up resistor (pin 21)
VSMH
(pin 21) Level high
VSML
(pin 21) Level low
(2)
dB
μA
1
1.5
2.5
3.5
V
35
50
65
KΩ
3.5
V
Soft mute active
1
V
Bass control
BBOOST
Max bass boost
15
18
20
dB
-8.5
-10
-11.5
dB
BCUT
Max bass cut
Astep
Step Resolution
1
2
3
dB
Internal Feedback
Resistance
45
65
85
KΩ
±13
±14
±15
dB
1
2
3
dB
Control range
35
37.5
40
dB
Step resolution
0.5
1.25
2.00
dB
80
100
Rg
Treble control
CRANGE
Astep
Control Range
Step Resolution
Speaker attenuators
CRANGE
Astep
AMUTE
8/20
Output mute attenuation
EA
Attenuation set error
VDC
DC Steps
Data word = XXX11111
Adjacent attenuation steps
0
dB
1.25
dB
3
mV
TDA7342
Electrical specifications
Table 4.
Electrical characteristics (continued)
(VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer
to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test condition
Min.
Typ.
2.1
2.6
Max.
Unit
Audio output
Vclip
Clipping Level
RL
Output Load Resistance
RO
Output Impedance
VDC
DC Voltage Level
d = 0.3%
Vrms
2
KΩ
30
100
Ω
3.5
3.8
4.1
V
General
VCC
Supply Voltage
6
9
10.2
V
ICC
Supply Current
5
10
15
mA
60
80
dB
B = 20 to 20kHz "A"
weighted
65
dB
Output muted (B = 20 to
20kHz flat)
2.5
μV
All gains 0dB (B = 20 to
20kHz flat)
5
15
μV
AV= 0 to -20dB
0
1
dB
AV= -20 to -60dB
0
2
dB
f = 1KHz
PSRR
eNO
Et
Power Supply Rejection
Ratio
Output Noise
Total Tracking Error
S/N
Signal to Noise Ratio
SC
Channel Separation
d
Distortion
All Gains = 0dB; VO= 1Vrms
80
VIN =1V
106
dB
100
dB
0.01
0.08
%
1
V
Bus inputs
VIL
Input Low Voltage
VlN
Input High Voltage
IlN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Acknowledge
IO= 1.6mA
3
V
-5
0.4
5
μA
0.8
V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
2. Internal pull-up resistor to Vs/2; LOW = softmute active
9/20
I2C Bus interface
3
TDA7342
I2C Bus interface
Data transmission from the microprocessor to the TDA7342 and vice versa takes place
through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pullup resistors to the positive supply voltage must be externally connected).
3.1
Data validity
As shown in fig. 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
3.2
Start and stop conditions
As shown in fig. 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
A STOP condition must be sent before each START condition.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by
an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see
fig. 6). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this
clock pulse.
The audioprocessor which has been addressed has to generate an acknowledgment after
the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer.
3.5
Transmission without acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a
simpler transmission: simply it waits one clock without checking the slave acknowledging,
and sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
10/20
TDA7342
I2C Bus interface
Figure 3.
Data validity on the I2C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 4.
CHANGE
DATA
ALLOWED
D99AU1031
Timing diagram of I2C BUS
SCL
I2CBUS
SDA
D99AU1032
START
Figure 5.
STOP
Acknowledge on the I2C BUS
SCL
1
2
3
7
8
9
SDA
MSB
START
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
11/20
Software specification
TDA7342
4
Software specification
4.1
Interface protocol
The interface protocol comprises:
●
A start condition (s)
●
A chip address byte, (the LSB bit determines read/write transmission)
●
A subaddress byte.
●
A sequence of data (N-bytes + acknowledge)
●
A stop condition (P)
Figure 6.
Interface protocol
CHIP ADDRESS
LSB
MSB
S
1
SUBADDRESS
0
0
0
1
0
0
DATA 1 ... DATA n
MSB
R/W
ACK
X
LSB
X
X
I
A3 A 2 A1 A 0
MSB
LSB
ACK
DATA
ACK
P
D05AU1575
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
Max clock speed 500kbits/s
4.2
Auto increment
If bit I in the subaddress byte is set to "1", the auto increment of the subaddress is enabled
Table 5.
Subaddress (receive mode)
MSB
X
12/20
LSB
X
X
I
Function
A3
A2
A1
A0
0
0
0
0
Input selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, treble
0
1
0
0
Speaker attenuator LF
0
1
0
1
Speaker attenuator LR
0
1
1
0
Speaker attenuator RF
0
1
1
1
Speaker attenuator RR
1
0
0
0
Mute
TDA7342
4.3
Software specification
Transmitted data
Table 6.
Send mode
MSB
LSB
X
X
X
X
X
SM
ZM
X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
4.4
Data byte specification
X = not relevant; set to "1" during testing
Table 7.
Input selector
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
not used
0
1
0
0
1
IN 2
0
1
0
1
0
IN 1
0
1
0
1
1
AM mono
0
1
1
0
0
not used
0
1
1
0
1
not used
0
1
1
1
0
not allowed
0
1
1
1
1
not allowed
0
1
0
0
11.25dB gain
0
1
0
1
7.5dB gain
0
1
1
0
3.75dB gain
0
1
1
1
0dB gain
0
0dB differential input gain
(IN3)
1
-6dB differential input
gain (IN3)
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
13/20
Software specification
Table 8.
TDA7342
Loudness
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0dB
X
X
X
0
0
0
0
1
-1.25dB
X
X
X
0
0
0
1
0
-2.5dB
X
X
X
0
0
0
1
1
-3.75dB
X
X
X
0
0
1
0
0
-5dB
X
X
X
0
0
1
0
1
-6.25dB
X
X
X
0
0
1
1
0
-7.5dB
X
X
X
0
0
1
1
1
-8.75dB
X
X
X
0
1
0
0
0
-10dB
X
X
X
0
1
0
0
1
-11.25dB
X
X
X
0
1
0
1
0
-12.5dB
X
X
X
0
1
0
1
1
-13.75dB
X
X
X
0
1
1
0
0
-15dB
X
X
X
0
1
1
0
1
-16.25dB
X
X
X
0
1
1
1
0
-17.5dB
X
X
X
0
1
1
1
1
-18.75dB
X
X
X
1
D3
D2
D1
D0
Loudness OFF (1)
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
NOTE 1: If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat
frequency response. D0 to D3 determine the attenuation level.
Table 9.
Mute
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
1
D0
1
Soft mute on
0
1
Soft mute with fast slope (I = IMAX)
1
1
Soft mute with slow slope (I = IMIN)
Direct mute
0
1
Zero crossing mute on
0
0
Zero crossing mute off
(delayed until the next zerocrossing)
1
14/20
D1
Zero crossing mute and pause detector
reset
0
0
160mV ZC Window threshold (WIN = 00)
0
1
80mV ZC Window threshold (WIN = 01)
TDA7342
Software specification
Table 9.
Mute
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
1
0
40mV ZC Window threshold (WIN = 10)
1
1
20mV ZC Window threshold (WIN = 11)
0
Non symmetrical bass cut (note 4)
1
Symmetrical bass cut
An additional direct mute function is included in the speaker attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Table 10.
Speaker attenuators (LF, LR, RF, RR)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
1.25dB step
X
X
X
0
0
0
0dB
X
X
X
0
0
1
-1.25dB
X
X
X
0
1
0
-2.5dB
X
X
X
0
1
1
-3.75dB
X
X
X
1
0
0
-5dB
X
X
X
1
0
1
-6.25dB
X
X
X
1
1
0
-7.5dB
X
X
X
1
1
1
-8.75dB
10dB step
X
X
X
0
0
0dB
X
X
X
0
1
-10dB
X
X
X
1
0
-20dB
X
X
X
1
1
-30dB
X
X
X
1
1
1
1
1
Speaker mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 11.
Bass/Treble
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
Treble step
0
0
0
0
-14dB
0
0
0
1
-12dB
15/20
Software specification
Table 11.
TDA7342
Bass/Treble (continued)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
Bass steps
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
-0dB
1
1
1
1
-0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
0
0
0
1
146B
0
0
0
0
18dB
For example 12dB Treble and -8dB Bass give the following data byte: 0 0 1 1 1 0 0 1
16/20
TDA7342
Software specification
Table 12.
Volume
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
0.31db fine attenuation steps
0
0
0db
0
1
-0.31db
1
0
-0.62db
1
1
-0.94db
1.25db coarse attenuation steps
0
0
0
0db
0
0
1
-1.25db
0
1
0
-2.5db
0
1
1
-3.75db
1
0
0
-5db
1
0
1
-6.25db
1
1
0
-7.5db
1
1
1
-8.75db
10db gain / attenuation steps
0
0
0
20db
0
0
1
10db
0
1
0
0db
0
1
1
-10db
1
0
0
-20db
1
0
1
-30db
1
1
0
-40db
1
1
1
-50db
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1
Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
NB.
Purchase of I2C Components of STMicrolectronics, conveys a
license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms
to the I2C Standard Specifications as defined by Philips.
17/20
Package information
5
TDA7342
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 7.
LQFP32 Mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
MAX.
1.600
0.0630
0.150 0.0020
0.0059
A1
0.050
A2
1.350
1.400
1.450 0.0531 0.0551 0.0571
b
0.300
0.370
0.450 0.0118 0.0146 0.0177
c
0.090
D
8.800
9.000
9.200 0.3465 0.3543 0.3622
D1
6.800
7.000
7.200 0.2677 0.2756 0.2835
D3
0.200 0.0035
5.600
0.2205
8.800
9.000
9.200 0.3465 0.3543 0.3622
E1
6.800
7.000
7.200 0.2677 0.2756 0.2835
5.600
e
0.800
L
0.450
0.600
L1
1.000
K
3.500
ccc
Weight: 0.20gr
0.0079
E
E3
OUTLINE AND
MECHANICAL DATA
0.2205
0.0315
0.750 0.0177 0.0236 0.0295
0.0394
7.000
0.1378 0.2756
0.100
0.0039
LQFP32 (7 x 7 x 1.40mm)
0060661 D
18/20
TDA7342
6
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
24-Jan-2006
1
Initial release.
20-Nov-2006
2
Update package information, layout changes, text modifications.
19/20
TDA7342
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
20/20