STMICROELECTRONICS TSA1001IF

TSA1001
10-BIT, 25MSPS, 35mW A/D CONVERTER
■ 10-bit A/D converter in deep submicron
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CMOS technology
Ultra low power consumption: 35mW @
25Msps (10mW @ 5Msps)
Single supply voltage: 2.5V
Input range: 2Vpp differential
25Msps sampling frequency
ENOB=9.7 @ Nyquist
SFDR typically up to 72dB @ Nyquist
Built-in reference voltage with external bias
capability
STMicroelectronics 8, 10, 12 and 14-bits ADC
pinout compatibility
ORDER CODE
Temperature
Range
Part Number
Conditioning
Marking
TSA1001CF
0°C to +70°C
TQFP48
Tray
SA1001C
TSA1001CFT
0°C to +70°C
TQFP48
Tape & Reel
SA1001C
TSA1001IF
-40°C to +85°C
TQFP48
Tray
SA1001I
TSA1001IFT
-40°C to +85°C
TQFP48
Tape & Reel
SA1001I
EVAL1001/AA
Evaluation board
PIN CONNECTIONS (top view)
GNDB
VCCB
DR
NC
44 43
VCCB
45
NC
47 46
NC
DFSB
48
OEB
AVCC
index
corner
AVCC
AGND
DESCRIPTION
42
41
40
39
38
37
IPOL
1
36 NC
VREFP
2
35 NC
VREFM
3
34 NC
AGND
4
33 D0 (LSB)
VIN
5
32 D1
AGND
6
VINB
7
AGND
8
29 D4
INCM
9
28 D5
AGND
10
27 D6
AVCC
11
26 D7
AVCC
12
31 D2
TSA1001
30 D3
25 D8
18 19
20
21
22
23
24
GNDB
GNDB
VCCB
OR
D9 (MSB)
NC
17
DGND
DGND
DVCC
16
DGND
14 15
CLK
13
DVCC
The TSA1001 is a 10-bit, 25Msps sampling frequency Analog to Digital converter using a CMOS
technology combining high performances and
very low power consumption.
The TSA1001 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and go beyond 9.8 effective bits at
Fs=25Msps, and Fin=10MHz.
Especially designed for portable applications, the
TSA1001 only dissipates 35mW at 25Msps. When
running at lower sampling frequencies, even lower
consumption can be achieved.
A voltage reference is integrated in the circuit to
simplify the design and minimize external components. It is nevertheless possible to use the circuit
with an external reference.
The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for synchronization purposes.
The TSA1001 is available in commercial (0 to
+70°C) and extended (-40 to +85°C) temperature
range, in a small 48 pins TQFP package.
Package
PACKAGE
7 × 7 mm TQFP48
APPLICATIONS
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Portable instrumentation
Video processing
Medical imaging and ultrasound
High resolution fax and scanners
Digital communications
October 2000
1/19
TSA1001
ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC
Parameter
Analog Supply voltage
DVCC
Digital Supply voltage
VCCB
Digital buffer Supply voltage 1)
Digital output current
Storage temperature
Electrical Static Discharge:
- HBM
- CDM-JEDEC Standard
IDout
Tstg
ESD
Values
Unit
0 to 3.3
V
0 to 3.3
V
0 to 3.3
V
-100 to 100
+150
mA
°C
KV
1)
1)
2
1.5
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
AVCC
Analog Supply voltage
2.25
2.5
2.7
V
DVCC
Digital Supply voltage
2.25
2.5
2.7
V
VCCB
Digital buffer Supply voltage
2.25
2.5
2.7
V
VREFP
Forced top voltage reference
1.16
-
AVCC
V
VREFM
Forced bottom reference voltage
0
0
0.5
V
BLOCK DIAGRAM
VREFP
+2.5V
GNDA
VIN
stage
1
INCM
VINB
stage
2
stage
n
Reference
circuit
IPOL
VREFM
DFSB
Sequencer-phase shifting
OEB
CLK
Timing
Digital data correction
DR
DO
Buffers
TO
D9
OR
GND
2/19
TSA1001
PIN CONNECTIONS (top view)
VCCB
41
40
39
38
NC
GNDB
42
DR
VCCB
44 43
NC
45
NC
DFSB
47 46
OEB
AVCC
48
AVCC
AGND
index
corner
37
IPOL
1
36 NC
VREFP
2
35 NC
VREFM
3
34 NC
AGND
4
33 D0 (LSB)
VIN
5
32 D1
AGND
6
31 D2
VINB
7
AGND
8
29 D4
INCM
9
28 D5
AGND
10
27 D6
AVCC
11
26 D7
AVCC
12
TSA1001
30 D3
25 D8
20
21
CLK
DGND
NC
DGND
GNDB
GNDB
22
23
24
D9 (MSB)
18 19
OR
17
VCCB
16
DGND
DVCC
14 15
DVCC
13
PIN DESCRIPTION
Pin No
Name
1
IPOL
Description
Observation
Analog bias current input
Pin No
Name
25
D8
Description
Digital output
Observation
CMOS output (2.5V)
2
VREFP
Top voltage reference
1V
26
D7
Digital output
CMOS output (2.5V)
3
VREFM
Bottom voltage reference
0V
27
D6
Digital output
CMOS output (2.5V)
4
AGND
5
VIN
6
AGND
7
VINB
8
9
10
Analog ground
0V
28
D5
Digital output
CMOS output (2.5V)
Analog input
1Vpp
29
D4
Digital output
CMOS output (2.5V)
Analog ground
0V
30
D3
Digital output
CMOS output (2.5V)
Inverted analog input
1Vpp
31
D2
Digital output
CMOS output (2.5V)
AGND
Analog ground
0V
32
D1
Digital output
CMOS output (2.5V)
INCM
Input common mode
0.5V
33
D0(LSB)
Least Significant Bit output
CMOS output (2.5V)
AGND
Analog ground
0V
34
NC
Non connected
11
AVCC
Analog power supply
2.5V
35
NC
Non connected
12
AVCC
Analog power supply
2.5V
36
NC
Non connected
13
DVCC
Digital power supply
2.5V
37
NC
Non connected
14
DVCC
Digital power supply
2.5V
38
DR
Data Ready output
CMOS output (2.5V)
15
DGND
Digital ground
0V
39
VCCB
Digital Buffer power supply
2.5V
16
CLK
Clock input
2.5V compatible CMOS input
40
GNDB
Digital Buffer ground
0V
17
DGND
Digital ground
0V
41
VCCB
Digital Buffer power supply
2.5V
18
NC
Non connected
42
NC
19
DGND
Digital ground
0V
43
NC
20
GNDB
Digital buffer ground
0V
44
OEB
Output Enable input
2.5V compatible CMOS input
21
GNDB
Digital buffer ground
0V
45
DFSB
Data Format Select input
2.5V compatible CMOS input
22
VCCB
Digital buffer power supply
2.5V
46
AVCC
Analog power supply
2.5V
23
OR
Out Of Range output
CMOS output (2.5V)
47
AVCC
Analog power supply
2.5V
CMOS output (2.5V)
48
AGND
Analog ground
0V
24
D9(MSB) Most Significant Bit output
Non connected
Non connected
3/19
TSA1001
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
25
MHz
55
%
FS
Sampling Frequency
0.5
DC
Clock Duty Cycle
45
50
TC1
Clock pulse width (high)
18
20
ns
TC2
Clock pulse width (low)
18
20
ns
Tod
Data Output Delay (Fall of Clock 10pF load capacitance
to Data Valid)
5
ns
Tpd
Data Pipeline delay
6.5
cycles
Ton
Falling edge of OEB to digital
output valid data
1
ns
Toff
Rising edge of OEB to digital
output tri-state
1
ns
TIMING DIAGRAM
N+4
N+5
N+3
N+6
N+7
N+2
N-1
N+1
N
N+8
CLK
6.5 clk cycles
OEB
DATA
OUT
N-8
Ton
Toff
Tod
N-7
N-6
N-5
N-4
N-3
N
N-2
DR
HZ state
4/19
N+1
TSA1001
CONDITIONS:
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol
Parameter
Test conditions
Min
VIN-VINB Full scale reference voltage
Cin
Input capacitance
BW
Analog Input Bandwitdh
ERB
Effective Resolution Bandwidth1)
Vin@Full Scale, FS=25Msps
Typ
Max
Unit
2.0
Vpp
7.
pF
100
MHz
60
MHz
1). See parameters definition for more information
REFERENCE VOLTAGE
Symbol
VREFP
Parameter
Top internal reference voltage
Test conditions
Tmin= -40°C to Tmax= 85°C1)
Min
Typ
Max
Unit
0.91
1.03
1.15
V
1.16
V
1.35
V
1.36
V
70
µA
0.90
1.20
Vpol
Analog bias voltage
1)
Tmin= -40°C to Tmax= 85°C
Ipol
Analog bias current
Normal operating mode
Ipol
Analog bias current
Shutdown mode
1.19
25
Input common mode voltage
Tmin= -40°C to Tmax=
50
0
0.48
VINCM
1.27
85°C1)
0.48
0.57
µA
0.65
V
0.66
V
1). Not fully tested over the temperature range. Guaranted by sampling.
5/19
TSA1001
CONDITIONS:
AVCC = DVCC = VCCB = 2.5V, Fs= 25Msps, Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
POWER CONSUMPTION
Symbol
Parameter
Test conditions
Min
1)
ICCA
Typ
Max
Unit
11.8
14
mA
14
mA
2
mA
2
mA
5
mA
5
mA
40
100
µA
35
47
mW
47
mW
37
mW
Analog Supply current
Tmin= -40°C to Tmax= 85°C2)
1)
ICCD
Digital Supply Current
1
Tmin= -40°C to Tmax= 85°C2)
1)
ICCB
Digital Buffer Supply Current
ICCBZ
Digital Buffer Supply Current in
High Impedance Mode
Pd
Power consumption in normal
operation mode
1.4
Tmin= -40°C to Tmax= 85°C2)
1)
1)
Tmin= -40°C to Tmax= 85°C2)
1)
PdZ
Power consumption in High
Impedance mode
Rthja
Junction-ambient thermal resistor (TQFP48)
80
°C/W
Rthjc
Junction-case thermal resistor
(TQFP48)
18
°C/W
32
1). Rpol= 25KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF
2). Not fully tested over the temperature range. Guaranted by sampling.
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
0.8
V
Digital inputs
VIL
Logic "0" voltage
VIH
Logic "1" voltage
2.0
V
Digital Outputs
VOL
Logic "0" voltage
Iol=10µA
VOH
Logic "1" voltage
Ioh=10µA
IOZ
High Impedance leakage current OEB set to VIH
CL
0.4
2.4
V
V
-1.5
Output Load Capacitance
1.5
µA
15
pF
ACCURACY
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
-5
±0.1
+5
%
OE
Offset Error
DNL
Differential Non Linearity
-0.7
±0.3
+0.7
LSB
INL
Integral Non Linearity
-0.8
±0.3
+0.8
LSB
-
6/19
Monotonicity and no missing
codes
Guaranted
TSA1001
CONDITIONS:
AVCC = DVCC = 2.5V, Fs= 25Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol
Parameter
Test conditions
Fin= 5MHz
Fin= 10MHz
SFDR
THD
SINAD
ENOB
Typ
66
80.5
66
76
Max
Unit
dBc
Spurious Free Dynamic Range
Fin= 5MHz
Fin= 10MHz
SNR
1)
Min
Signal to Noise Ratio
Total Harmonic Distortion
Signal to Noise and DistortionRatio
Effective Number of Bits
2)
66
dBc
66
Fin= 5MHz
Fin= 10MHz
1)
Fin= 5MHz
Fin= 10MHz
2)
Fin= 5MHz
Fin= 10MHz
1)
Fin= 5MHz
Fin= 10MHz
2)
Fin= 5MHz
Fin= 10MHz
1)
Fin= 5MHz
Fin= 10MHz
2)
Fin= 5MHz
Fin= 10MHz
1)
Fin= 5MHz
Fin= 10MHz
2)
58
59.3
58
59.3
58
dB
58
63
79.5
63
75
62
58
59.0
58
59.0
58
dB
dB
58
9.5
9.70
9.5
9.70
9.5
dB
dB
62
9.5
dB
bits
bits
1). Rpol= 25KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF
2). Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranted by sampling.
7/19
TSA1001
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERS
Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 25Msps, which is high enough to fully
characterize the test frequency response. The input level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)
The average deviation of any output code width
from the ideal code width of 1LSB.
Integral Non linearity (INL)
An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERS
Dynamic measurements are performed by
spectral analysis, applied to an input sinewave of
various frequencies and sampled at 25Msps.
Spurious Free Dynamic Range (SFDR)
The ratio between the amplitude of fundamental
tone (signal power) and the power of the worst
spurious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
8/19
Signal to Noise Ratio (SNR)
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distorsion Ratio (SINAD)
Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)
The ENOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between time when the analog input is
initially sampled and time when the corresponding
digital data output is valid on the output bus. Also
called data latency. It is expressed as a number of
clock cycles.
TSA1001
EQUIVALENT CIRCUITS
Figure 1 : Analog Input Circuit
Figure 3 : Input buffers
VCCbuf=2.5V
AVCC=2.5V
VIN
355.5 Ω
278.5 Ω 208.2 Ω
DFS
(or VINB)
PAD
CAPACITANCE
7 pF
7 pF
PAD
CAPACITANCE
AGND=0V
GNDbuff=0V
common mode
Figure 2 : Input clock circuit
Figure 4 : Tri-state output buffers
VCC buf=2.5V
DVCC=2.5V
OE
CLK
DATA
GND buff=0V
VCC buf =2.5V
PAD
CAPACITANCE
7 pF
OUT
2 mA
OUTPUT
BUFFER
PAD CAPACITANCE
7pF
DGND=0V
GND buff=0V
9/19
TSA1001
Static parameter: Integral Non Linearity
Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072pts
0 .4
0 .3
0 .2
INL (LSBs)
0 .1
0
- 0 .1
- 0 .2
- 0 .3
- 0 .4
- 0 .5
0
200
400
600
800
1000
600
800
1000
O u tp u t C o d e
Static parameter: Differential Non Linearity
Fs=25MSPS; Fin=1MHz; Icca=11mA; N=131072 pts
0 .3
0 .2
DNL (LSBs)
0 .1
0
-0 .1
-0 .2
-0 .3
0
200
400
O u tp u t C o d e
Linearity vs. AVcc
Fs=25MSPS; Icca=11mA; Fin=1MHz
9.9
60
9.85
SINAD
9.8
59.5
9.75
59
ENOB
9.7
58.5
9.65
9.6
2.35
2.45
2.55
AVCC (V)
2.65
Dynamic Parameters (dB)
SNR
ENOB (bits)
Dynamic parameters (dB)
9.95
60.5
58
2.25
-67
10
61
10/19
Distortion vs. AVcc
Fs=25MSPS; Icca=11mA; Fin=1MHz
-69
-71
THD
-73
-75
-77
SFDR
-79
-81
-83
-85
2.25
2.35
2.45
AVCC (V)
2.55
2.65
TSA1001
Linearity vs. DVcc
Fs=25MSPS; Icca=11mA; Fin=1MHz
Distortion vs. DVcc
Fs=25MSPS; Icca=11mA; Fin=1MHz
9.95
SNR
60
9.9
SINAD
59.5
9.85
59
9.8
ENOB
58.5
9.75
Dynamic Parameters (dB)
60.5
58
2.25
-70
10
ENOB (bits)
Dynamic parameters (dB)
61
9.7
2.35
2.45
2.55
-71
-72
-73
THD
-74
-75
-76
-77
SFDR
-78
-79
-80
2.25
2.65
2.35
2.45
DVCC (V)
Distortion vs. VccB
Fs=25MSPS; Icca=11mA; Fin=1MHz
SNR
9.9
60
9.85
SINAD
9.8
59.5
59
9.75
ENOB
ENOB (bits)
Dynamic parameters (dB)
9.95
60.5
9.7
58.5
9.65
Dynamic Parameters (dB)
10
61
9.6
2.35
2.45
2.55
-71
-73
THD
-75
-77
SFDR
-79
-81
-83
-85
2.25
2.65
2.35
2.45
VCCB (V)
SNR
60
9
58
8.5
56
SINAD
8
54
7.5
52
50
7
25
35
45
Dynamic parameters (dB)
9.5
62
Fs (MHz)
35
45
-50
ENOB (bits)
Dynamic parameters (dB)
10
15
2.65
Distortion vs. Fs
Icca=11mA; Fin=1MHz
ENOB
64
2.55
VCCB (V)
Linearity vs. Fs
Icca=11mA; Fin=1MHz
5
2.65
DVCC (V)
Linearity vs. VccB
Fs=25MSPS; Icca=11mA; Fin=1MHz
58
2.25
2.55
-55
-60
-65
-70
THD
-75
-80
SFDR
-85
5
15
25
Fs (MHz)
11/19
TSA1001
Distortion vs. Fs
Icca=11mA; Fin=15MHz
Linearity vs. Fs
Icca=11mA; Fin=15MHz
-50
SNR
60
9.5
9
58
8.5
SINAD
56
8
54
7.5
52
50
Dynamic parameters (dB)
ENOB
62
ENOB (bits)
Dynamic parameters (dB)
10
64
15
25
35
-60
-65
THD
-70
-75
SFDR
-80
-85
-90
7
5
-55
5
45
15
10
68
9.8
9.4
64
9.2
62
9
SNR
8.8
60
8.6
SINAD
8.4
56
8.2
54
8
40
Dynamic parameters (dB)
9.6
ENOB
66
-40
ENOB (bits)
Dynamic parameters (dB)
70
20
-45
-50
-55
THD
-60
-65
-70
SFDR
-75
-80
-85
-90
60
0
10
20
Fin (MHz)
9.9
SNR
9.85
59.2
9.8
59
SINAD
9.75
58.6
9.7
58.4
ENOB
0
50
Temperature (°C)
12/19
9.65
9.6
58
-50
50
60
80
100
Dynamic Parameters (dB)
Dynamic Parameters (dB)
9.95
59.6
58.2
40
Distortion vs. Temperature
Fs=25MSPS; Icca=11mA; Fin=5MHz;
10
60
59.8
58.8
30
Fin (MHz)
Linearity vs.Temperature
Fs=25MSPS; Icca=11mA; Fin=5MHz
59.4
45
Distortion vs. Fin
Fs=25MSPS; Icca=11mA
Linearity vs. Fin
Fs=25MSPS; Icca=11mA
0
35
Fs (MHz)
Fs (MHz)
58
25
78
76
THD
74
72
SFDR
70
68
-50
0
50
Temperature (°C)
100
70
TSA1001 APPLICATION NOTE
stage. The corrected data are outputed through
the digital buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the falling edge of the Data Ready signal.
The advantages of such a converter reside in the
combination of pipeline architecture and the most
advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level.
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described in
the following table.
The TSA1001 is pin to pin compatible with the
8bits/40Msps TSA0801, the 10bits/50Msps
TSA1002 and the 12bits/50Msps TSA1201. This
ensures a conformity within the product family and
above all, an easy upgrade of the application.
DETAILED INFORMATION
The TSA1001 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 9 internal conversion stages in which the analog signal is fed
and sequencially converted into digital data.
Each 8 first stages consists of an Analog to Digital
converter, a Digital to Analog converter, a Sample
and Hold and a gain of 2 amplifier. A 1.5bit conversion resolution is achieved in each stage. The latest stage simply is a comparator. Each resulting
LSB-MSB couple is then time shifted to recover
from the conversion delay. Digital data correction
completes the processing by recovering from the
redundancy of the (LSB-MSB) couple for each
OPERATIONAL MODES DESCRIPTION
Inputs
Outputs
Analog input differential level
DFSB
OEB
OR
DR
Most Significant Bit (MSB)
(VIN-VINB)
>
RANGE
-RANGE
>
(VIN-VINB)
RANGE> (VIN-VINB) >-RANGE
(VIN-VINB)
>
RANGE
-RANGE
>
(VIN-VINB)
RANGE> (VIN-VINB) >-RANGE
X
H
H
H
L
L
L
X
L
L
L
L
L
L
H
H
H
L
H
H
L
HZ
CLK
CLK
CLK
CLK
CLK
CLK
HZ
D9
D9
D9
Complemented D9
Complemented D9
Complemented D9
HZ
Data Format Select (DFSB)
When set to low level (VIL), the digital input DFSB
provides a two’s complement digital output MSB.
This can be of interest when performing some further signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.
Output Enable (OEB)
When set to low level (VIL), all digital outputs remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. This results in
13/19
lower consumption while the converter goes on
sampling.
When OEB is set to low level again, , the data is
then valid on the output with a very short Ton delay.
The timing diagram summarizes this operating cycle.
Out of Range (OR)
This function is implemented on the output stage
in order to set up an "Out of Range" flag whenever
the digital data are over the full scale range.
Typically, there is a detection of all the data being
at ’0’ or all the data being at ’1’. This ends up with
an output signal OR which is in low level state
TSA1001
(VOL) when the data stay within the range, or in
high level state (VOH) when the data is out of the
range.
Data Ready (DR)
The Data Ready output is an image of the clock
being synchronized on the output data (D0 to D9).
This is a very helpful signal that simplifies the synchronization of the measurement equipment or
the controlling DSP.
As digital output, DR goes in high impedance state
when OEB is asserted to High level as described
in the timing diagram.
In this case, it is recommended to use an
AC-coupled analog input and connect the other
analog input to the common mode voltage of the
circuit (INCM) so as to properly bias the ADC. The
INCM may remain at the same internal level
(0.56V) thus driving only a 1Vpp input amplitude,
or it must be increased to 0.9V to drive a 2Vpp
input amplitude. You will get higher performances
using a 2Vpp signal.
Figure 6 : Single-ended input configuration
Signal source
100nF
DRIVING THE ANALOG INPUT
VIN
TSA1001
50Ω
Differential inputs
VINB
The TSA1001 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve
such performances.
Figure 5 describes the schematics. The input signal is fed to the primary of the transformer, while
the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this
common voltage, internally set to 0.56V. The
INCM is decoupled to maintain a low noise level
on this node. Our evaluation board is mounted
with a 1:1 ADT1-1 transformer from Minicircuits.
You might also use a higher impedance ratio (1:2
or 1:4) to reduce the driving requirement on the
analog signal source.
Each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is
2Vpp.
Figure 5 : Differential input configuration
Analog source
ADT1-1
1:1
VIN
50Ω
TSA1001
100pF
VINB
330pF
10nF
0.9V
REFERENCE CONNECTION
Internal reference
In the standard configuration, the ADC is biased
with the internal reference voltage. VREFM pin is
connected to Analog Ground while VREFP is
internally set to a voltage of 1.03V. It is
recommended to decouple the VREFP in order to
minimize low and high frequency noise. Refer to
Figure 7 for the schematics.
Figure 7 : Internal reference setting
INCM
470nF
VIN
VREFP
TSA1001
VINB
VREFM
Single-ended input configuration
Some applications may require a single-ended input which is easily achieved with the configuration
reported on Figure 6.
14/19
470nF
Dynamic characteristics, while not being as remarkable as for differential configuration, are still
of very good quality. Measurements done at
25Msps, 1MHz input frequency, -1dBFS input level sum up these performances. An SFDR of
-69.5dBc, an SNR of 59.5dB and an ENOB Full
Scale of 9.7bits are achieved.
1.03V
330pF
10nF
INCM
330pF
10nF 470nF
TSA1001
External reference
It is possible to use an external reference voltage
instead of the internal one for specific applications
requiring even better linearity or enhanced
temperature behaviour. In this case, the amplitude
of the external voltage must be at least equal to
the
internal
one
(1.03V).
Using
the
STMicroelectronics Vref TS821 leads to optimum
performances when configured as shown on
Figure 8.
Figure 8 : External reference setting
Total power consumption optimization
depending on Rpol value
1kΩ
330pF
VCCA VREFP
VIN
TSA1001
VINB
VREFM
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA1001 will combine highest performances
and lowest consumption at 25Msps when Rpol is
equal to 25kΩ.
At lower sampling frequency range (< 10Msps),
this value of resistor may be adjusted in order to
decrease the analog current without any
degradation of dynamic performances.
As an example, 10mW total power consumption is
achieved at 5 Msps with Rpol equal to 390kΩ.
The table below sums up the relevant data.
10nF 470nF
Fs (Msps)
Rpol (kΩ)
TS821
external
reference
At 15Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up to 2dBc on SFDR
and 0.3dB on SINAD. At 25Msps sampling frequency, 1MHz input frequency and -1dBFS amplitude signal, performances can be improved of up
to 1dBc on SFDR and 0.5dB on SINAD.
This can be very helpful for example for multichannel application to keep a good matching among
the sampling frequency range.
Clock input
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator
is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption optimization
The internal architecture of the TSA1001 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
Optimized
power (mW)
5
390
15
40
25
25
10
25
35
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is mandatory for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
15/19
TSA1001
EVAL1002 evaluation board
The characterization of the board has been made
with a fully ADC devoted test bench as shown on
Figure 10. The analog signal must be filtered to be
very pure.
The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the octal
buffers 74LCX573.
All characterization measurements have been
made with: SFSR=+0.2dB for static parameters.SFSR=-0.5dB for dynamic parameters.
Figure 9 : Analog to Digital Converter characterization bench
Power
HP8644B
Sine wave
Generator
Vin
ADC
evaluation
board
data
Logic
Analyzer
dataready
ck
TLA704
16/19
HP8133A
Pulse
Generator
HP8644B
Sine Wave
Generator
1
2
1
2
R1
50
3
1
GndB1
1
2
J22
GndB2
1
2
J21
DGND
1
2
J20
AGND
1
2
J19
AVCC
2
1
Mes com Mode
J12
1
2
Regl com mode
J8
J7
J1
Vin
VrefM
J5
VrefP
1
2
2
6
+
C42
47µF
C41
10µF
470nF 10nF
330pF
C5
C6
C7
C8
330pF
C9
C1
100pF
470nF 10nF
C10
4
T2-AT1-1WT
T2
AVCC
470nF
C32
10nF
C31
C4
10µ
1
2
3
4
5
6
7
8
9
10
11
12
J16
CON2
C36
47µ
470nF
C23
10nF
C22
330pF
C21
C20
330pF
C2
330pF
C11
J15
DVCC
470nF 10nF
C3
C30
330pF 470nF 10nF
C13 C12
R2
1K
Raj1
47K
Ipol
VrefP
VrefM
AGND
Vin
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
330pF
10nF
C14
470nF
C15
C16 AVCC
47K
R13
47K
R12
47K
R11
47K
R10
1
2
6
8-14bits ADC
TSA1001
50
R3
CLJ/SMB
J4
1
J2
+
2
J11
J13
330pF
10nF
C25
470nF
C27
C29
C35
47µ
10µ
470nF
C24
10nF
C19
10µF C17
T1
T2-AT1-1WT
330pF
C18
J18
VccB1
VCCB1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
R14 R15 R16 R17 R18 R19
47K 47K 47K 47K 47K 47K
C28 VCCB1
1
2
J10
OEB
+
2
1
1
2
4
3
+
2
1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
AGND
AVCC
AVCC
DFSB
OEB
NC
NC
2.5VCCBUFF
GNDBUFF
2.5VCCBUFF
DR
D0
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBUFF
GNDBUFF
2.5VCCBUFF
OR
D13
13
14
15
16
17
18
19
20
21
22
23
24
330pF
10nF
C33
470nF
C40
C38
74LCX573
OEB VCC
D0
Q0
D1 U3 Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
GND
LE
74LCX573
OEB VCC
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
U2
D5
Q5
D6
Q6
D7
Q7
GND
LE
330pF
10nF
C26
470nF
C39
47µ
C37
C34
+
2
1
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
J17
VDDBUFF3V
VCCB2
1
2
J9
DFSB
DR
OR
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
32PIN
J6
TSA1001
Figure 10 : TSA1001 Evaluation board schematic
17/19
TSA1001
Figure 11 : Printed circuit board - Top side silkscreen
Printed circuit board - List of components
P a rt
D e s i g n F o o t p r in t
P a rt
D e s ig n F o o t p r in t
P a rt
D e s i g n F o o t p r in t
P a rt
D e s ig n
T yp e
ato r
T yp e
ato r
T yp e
ato r
T yp e
ato r
F o o t p r in t
10 u F
C 24
12 10
3 3 0 pF
C 33
603
470nF
C7
805
A VC C
J 12
F IC H E 2 M M
10 u F
C 23
12 10
3 3 0 pF
C 20
603
470nF
C 16
805
C LJ / S M B
J4
SM B /H
10 u F
C 41
12 10
3 3 0 pF
C8
603
470nF
C 19
805
A GN D
J 19
F IC H E 2 M M
10 u F
C 29
12 10
3 3 0 pF
C2
603
470nF
C3
805
D FSB
J9
F IC H E 2 M M
10 0 p F
C1
603
3 3 0 pF
C5
603
47K Ω
R 12
603
D GN D
J20
F IC H E 2 M M
10 n F
C 12
603
3 3 0 pF
C 11
603
47K Ω
R 14
603
D VC C
J 15
F IC H E 2 M M
10 n F
C 39
603
3 3 0 pF
C 30
603
47K Ω
R 11
603
G ndB 1
J22
F IC H E 2 M M
10 n F
C 15
603
3 3 0 pF
C 17
603
47K Ω
R a j1
VR 5
G ndB 2
J21
10 n F
C 40
603
3 3 0 pF
C 14
603
47K Ω
R 10
603
M es co m m o de J8
F IC H E 2 M M
10 n F
C 27
603
47uF
C 36
CAP
47K Ω
R 19
603
OEB
F IC H E 2 M M
10 n F
C4
603
47uF
C 34
CAP
47K Ω
R 13
603
R e gl c o m m o de J 7
F IC H E 2 M M
10 n F
C 21
603
47uF
C 35
CAP
47K Ω
R 15
603
T 2 - A T 1- 1W T
T2
ADT
10 n F
C 31
603
47uF
C 42
CAP
47K Ω
R 16
603
T 2 - A T 1- 1W T
T1
ADT
10 n F
C6
603
4 7 0 nF
C 22
805
47K Ω
R 17
603
VccB 1
J 18
F IC H E 2 M M
10 n F
C9
603
4 7 0 nF
C 32
805
47K Ω
R 18
603
VD D B UF F 3V
J 17
F IC H E 2 M M
10 n F
C 18
603
4 7 0 nF
C 37
805
50 Ω
R3
603
V in
J1
SM B /H
R1
1K Ω
R2
603
4 7 0 nF
C 38
805
50 Ω
3 2 P IN
J6
ID C 3 2
4 7 0 nF
C 13
805
7 4 LC X 5 7 3 U3
330pF
C 25
603
4 7 0 nF
C 28
805
330pF
C 26
603
4 7 0 nF
C 10
805
18/19
J 10
F IC H E 2 M M
603
V re f M
J5
F IC H E 2 M M
TSSOP 20
V re f P
J2
F IC H E 2 M M
7 4 LC X 5 7 3 U2
TSSOP 20
T S A 10 0 1
U1
T QF P 48
CON2
S IP 2
J 16
TSA1001
PACKAGE MECHANICAL DATA
48 PINS - PLASTIC PACKAGE
A
A2
e
48
A1
37
36
12
25
E3
E1
E
B
1
0,10 mm
.004 inch
SEATING PLANE
c
24
L1
D3
D1
D
L
13
K
0,25 mm
.010 inch
GAGE PLANE
Millimeters
Inches
Dim.
Min.
A
A1
A2
B
C
D
D1
D3
e
E
E1
E3
L
L1
K
0.05
1.35
0.17
0.09
0.45
Typ.
1.40
0.22
9.00
7.00
5.50
0.50
9.00
7.00
5.50
0.60
1.00
Max.
Min.
1.60
0.15
1.45
0.27
0.20
0.002
0.053
0.007
0.004
0.75
0.018
Typ.
0.055
0.009
0.354
0.276
0.216
0.0197
0.354
0.276
0.216
0.024
0.039
Max.
0.063
0.006
0.057
0.011
0.008
0.030
0° (min.), 7° (max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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19/19