TSA1204 DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER ■ 0.5Msps to 20Msps sampling frequency ■ Adaptive power consumption: 120mW @ PIN CONNECTIONS (top view) D1 D0(LSB) VCCBE GNDBE VCCBI VCCBI OEB AVCC AVCC 34 D4 INIB 4 33 D5 AGND 5 32 D6 IPOL 6 31 D7 TSA1204 AVCCB 7 30 D8 29 D9 AGND 8 INQ 9 28 D10 AGND 10 27 D11(MSB) INBQ 11 26 VCCBE 25 GNDBE GNDBI DVCC DGND SELECT CLK AVCC DGND REFMQ DVCC 17 18 19 20 21 22 23 24 AGND 14 15 16 INCMQ 13 BLOCK DIAGRAM +2.5V/3.3V CLK SELECT OEB VCCBE Timing VINI AD 12 I channel VINBI VINCMI 12 common mode VREFPI REF I VREFMI IPOL M U X Polar. 12 12 Buffers D0 TO D11 VREFPQ REF Q VREFMQ VINCMQ common mode VINQ AD 12 Q channel 12 GNDBE PACKAGE 7 × 7 mm TQFP48 Package Conditioning Marking TSA1204IF -40°C to +85°C TQFP48 Tray SA1204I TSA1204IFT -40°C to +85°C TQFP48 Tape & Reel SA1204I EVAL1204/BA 35 D3 AGND 3 GND ORDER CODE February 2003 36 D2 REFPQ Medical imaging and ultrasound 3G base station I/Q signal processing applications High speed data acquisition system Portable instrumentation Temperature Range 41 40 39 38 37 44 43 42 2 INI VINBQ APPLICATIONS Part Number 47 46 45 AGND 1 AGND 12 The TSA1204 is a new generation of high speed, dual-channel Analog to Digital converter processed in a mainstream 0.25µm CMOS technology yielding high performances and very low power consumption. The TSA1204 is specifically designed for applications requiring very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction to provide excellent static linearity and over 11.2 effective bits at Fs=20Msps, and Fin=10MHz. For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. Each ADC outputs are multiplexed in a common bus with small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially driven. The TSA1204 is available in extended (-40 to +85°C) temperature range, in a small 48 pins TQFP package. ■ ■ ■ ■ ■ 48 INCMI DESCRIPTION index corner REFMI ■ ■ ■ ■ ■ ■ ■ Independent supply for CMOS output stage with 2.5V/3.3V capability ENOB=11.2 @ Nyquist SFDR= -81.5 dBc @ Nyquist 1GHz analog bandwidth Track-and-Hold Common clocking between channels Dual simultaneous Sample and Hold inputs Multiplexed outputs Built-in reference voltage with external bias capability. REFPI 20Msps, 95mW@10Msps ■ Single supply voltage: 2.5V Evaluation board 1/20 TSA1204 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25°C (unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol SFDR Parameter Test conditions Min Spurious Free Dynamic Range SNR Signal to Noise Ratio THD Total Harmonics Distortion 66.9 Typ Max Unit -81.5 -71.0 dBc 68.5 -80 dB -70 dBc SINAD Signal to Noise and Distortion Ratio 64.8 68 dB ENOB Effective Number of Bits 10.6 11.2 bits Min Typ TIMING CHARACTERISTICS Symbol Parameter Test conditions Max Unit 20 MHz 55 % FS Sampling Frequency 0.5 DC Clock Duty Cycle 45 50 TC1 Clock pulse width (high) 22.5 25 ns TC2 Clock pulse width (low) 22.5 25 ns Tod Data Output Delay (Clock edge to Data Valid) 9 ns 10pF load capacitance Tpd I Data Pipeline delay for I channel 7 cycles Tpd Q Data Pipeline delay for Q channel 7.5 cycles Ton Falling edge of OEB to digital output valid data 1 ns Toff Rising edge of OEB to digital output tri-state 1 ns 2/20 TSA1204 TIMING DIAGRAM Simultaneous sampling on I/Q channels N+4 N+5 N+13 N+3 N+12 N+6 I N N+11 N+7 N+2 N-1 N+1 N+8 N+10 N+9 Q CLK Tpd I + Tod Tod SELECT CLOCK AND SELECT CONNECTED TOGETHER OEB sample N-8 I channel sample N-6 Q channel sample N Q channel sample N+1 Q channel sample N+2 Q channel DATA OUTPUT sample N-9 I channel sample N-7 Q channel sample N+1 sample N+2 I channel I channel sample N+3 I channel PIN CONNECTIONS (top view) AVCC AVCC OEB VCCBI VCCBI GNDBE VCCBE D0(LSB) 47 46 45 44 43 42 41 40 39 38 37 D1 INCMI 48 REFMI REFPI index corner 36 D2 AGND 1 2 35 D3 AGND 3 34 D4 INIB 4 33 D5 INI AGND 5 32 D6 IPOL 6 31 D7 TSA1204 AVCCB 7 30 D8 29 D9 AGND 8 INQ 9 28 D10 AGND 10 27 D11(MSB) INBQ 11 26 VCCBE AGND 12 25 GNDBE 21 22 23 24 SELECT DGND DVCC GNDBI AVCC 20 CLK AGND 18 19 DGND 17 DVCC 16 INCMQ REFPQ 14 15 REFMQ 13 3/20 TSA1204 PIN DESCRIPTION Pin No Name Description Observation 1 AGND 2 INI 3 AGND 4 INBI 5 AGND 6 IPOL Analog bias current input 7 AVCC Analog power supply 2.5V 8 AGND Analog ground 0V 9 INQ 10 AGND Analog ground 11 INBQ Q channel inverted analog input 12 AGND Analog ground 13 REFPQ Q channel top reference voltage 14 REFMQ Q channel bottom reference voltage 15 INCMQ Q channel input common mode 16 AGND Analog ground 17 AVCC Analog power supply Analog ground 0V I channel analog input Analog ground 0V I channel inverted analog input Analog ground 0V Q channel analog input 0V 0V Pin No Name 25 GNDBE Digital buffer ground 0V 26 VCCBE Digital Buffer power supply 2.5V/3.3V 27 D11(MSB) Most Significant Bit output Digital output CMOS output (2.5V/3.3V) 29 D9 Digital output CMOS output (2.5V/3.3V) 30 D8 Digital output CMOS output (2.5V/3.3V) 31 D7 Digital output CMOS output (2.5V/3.3V) 32 D6 Digital output CMOS output (2.5V/3.3V) 33 D5 Digital output CMOS output (2.5V/3.3V) 34 D4 Digital output CMOS output (2.5V/3.3V) 35 D3 Digital output CMOS output (2.5V/3.3V) 36 D2 Digital output CMOS output (2.5V/3.3V) 37 D1 Digital output CMOS output (2.5V/3.3V) 38 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V) 39 VCCBE Digital Buffer power supply 2.5V/3.3V - See Application Note 0V 40 GNDBE Digital buffer ground 0V 2.5V 41 VCCBI Digital Buffer power supply 2.5V 0V DVCC Digital power supply 2.5V 42 DVCC DGND Digital ground 0V 43 OEB CLK SELECT 22 23 24 CMOS output (2.5V/3.3V) D10 19 21 Observation 28 18 20 Description Digital Buffer power supply 2.5V Output Enable input 2.5V/3.3V CMOS input Clock input 2.5V CMOS input 44 AVCC Analog power supply 2.5V Channel selection 2.5V CMOS input 45 AVCC Analog power supply 2.5V DGND Digital ground 0V 46 INCMI I channel input common mode DVCC Digital power supply 2.5V 47 REFMI I channel bottom reference voltage 0V GNDBI Digital buffer ground 0V 48 REFPI I channel top reference voltage ABSOLUTE MAXIMUM RATINGS Symbol AVCC DVCC VCCBE VCCBI IDout Tstg ESD Parameter Analog Supply voltage 1) 1) Values Unit 0 to 3.3 V 0 to 3.3 V Digital buffer Supply voltage 1) 0 to 3.6 V Digital buffer Supply voltage Digital output current Storage temperature 1) 0 to 3.3 V -100 to 100 +150 mA °C Digital Supply voltage HBM: Human Body Model2) CDM: Charged Device 2 kV 1.5 Model3) Latch-up Class4) A 1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC 2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ 3). Discharge to Ground of a device that has been previously charged. 4). Corporate ST Microelectronics procedure number 0018695 OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCBE External Digital buffer Supply voltage 1.8 2.5 3.5 V VCCBI Internal Digital buffer Supply voltage 2.25 2.5 2.7 V 4/20 TSA1204 Symbol Parameter VREFPI VREFPQ VREFMI VREFMQ INCMI INCMQ 1) Min Max Unit 0.96 1.4 V Forced bottom reference voltage 1) 0 0.4 V Forced input common mode voltage 0.2 1 V Forced top voltage reference 1) Typ Condition VRefP-VRefM>0.3V ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25°C (unless otherwise specified) ANALOG INPUTS Symbol Parameter VIN-VINB Full scale reference voltage Cin Input capacitance Req Equivalent input resistor BW Analog Input Bandwidth ERB Effective Resolution Bandwidth Test conditions Differential inputs mandatory Min Typ Max Unit 1.1 2.0 2.8 Vpp Vin@Full Scale, Fs=20Msps 7.0 pF 3 KΩ 1000 MHz 70 MHz DIGITAL INPUTS AND OUTPUTS Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock and Select inputs VIL Logic "0" voltage VIH Logic "1" voltage 2.0 2.5 V OEB input VIL Logic "0" voltage VIH Logic "1" voltage 0 0.25 x VCCBE 0.75 x VCCBE VCCBE V V Digital Outputs VOL VOH Logic "0" voltage Logic "1" voltage Iol=10µA Ioh=10µA IOZ High Impedance leakage current OEB set to VIH CL Output Load Capacitance 0 0.1 x VCCBE 0.9 x VCCBE VCCBE -1.7 V V 1.7 µA 15 pF 5/20 TSA1204 ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V Tamb = 25°C (unless otherwise specified) REFERENCE VOLTAGE Symbol VREFPI VREFPQ VINCMI VINCMQ Parameter Test conditions Min Typ Max Unit Top internal reference voltage 0.807 0.89 0.963 V Input common mode voltage 0.40 0.46 0.52 V POWER CONSUMPTION Symbol Parameter Min Typ Max Unit ICCA Analog Supply current 40 49.5 mA ICCD Digital Supply Current 2 3 mA ICCBE Digital Buffer Supply Current (10pF load) 6.2 9 mA ICCBI Digital Buffer Supply Current 73 221 µA Power consumption in normal operation mode 120 155 mW Thermal resistance (TQFP48) 80 Pd Rthja °C/W ACCURACY Symbol Parameter Min Typ Max Unit OE Offset Error -1.8 -0.5 1.8 LSB GE Gain Error -0.1 0 0.1 % DNL Differential Non Linearity -0.93 ±0.4 +0.93 LSB INL Integral Non Linearity -1.8 ±0.8 +1.8 LSB Mono tonicity and no missing codes Guaranteed MATCHING BETWEEN CHANNELS Symbol 6/20 Parameter Min Typ Max Unit GM Gain match 0.033 0.1 % OM Offset match 0.4 2.5 LSB PHM Phase match 1 dg XTLK Crosstalk rejection 87 dB TSA1204 DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 20Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 20Msps. The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Spurious Free Dynamic Range (SFDR) Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao =SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao =6.02 × ENOB + 1.76 dB + 20 log (2A 0/ FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Total Harmonic Distortion (THD) Pipeline delay The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. 7/20 TSA1204 Static parameter: Integral Non Linearity Fs=20MSPS; Icca=40mA; Fin=2MHz 0.8 INL (LSBs) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 3000 3500 4000 2500 3000 3500 4000 Output Code Static parameter: Differential Non Linearity Fs=20MSPS; Icca=40mA; Fin=2MHz 0.4 DNL (LSBs) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 500 1000 1500 2000 Output Code Linearity vs. Fs Fin=5MHz; Rpol adjustment 12 11 90 ENOB I 80 SNR_Q 10 SINAD_Q 9 70 8 60 SINAD_I SNR_I 50 7 6 40 5 10 15 20 Fs (MHz) 8/20 -20 25 Dynamic parameters (dBc) ENOB Q ENOB (bits) Dynamic parameters (dB) 100 Distortion vs. Fs Fin=5MHz; Rpol adjustment -30 -40 -50 THD_I SFDR_I -60 -70 -80 -90 -100 THD_Q -110 SFDR_Q -120 10 15 20 Fs (MHz) 25 TSA1204 Distortion vs. Fin Fs=20MSPS; Icca=40mA Linearity vs. Fin Fs=20MSPS; Icca=40mA 12 ENOB_I 90 -30 11 80 10 SINAD_Q SNR_Q 70 9 60 8 SNR_I 50 SINAD_I 7 40 6 30 5 0 10 20 30 40 Dynamic parameters (dBc) ENOB_Q ENOB (bits) Dynamic parameters (dB) 100 -40 -50 THD_Q -60 SFDR_I -70 -80 -90 THD_I SFDR_Q -100 -110 -120 50 0 10 20 Fin (MHz) 90 11 10.5 ENOB_Q SINAD_I 10 70 9.5 9 SNR_Q SINAD_Q 8.5 8 50 7.5 40 Dynamic parameters (dBc) 120 11.5 ENOB (bits) Dynamic parameters (dB) 12 ENOB_I 60 10 110 100 SFDR_Q 80 70 THD_I SFDR_I 60 50 -40 60 10 12 ENOB_Q 11 90 ENOB_I 10 80 75 SNR_Q 9 SINAD_Q 70 8 65 60 SINAD_I SNR_I 7 55 50 2.25 6 2.35 2.45 AVCC (V) 2.55 2.65 ENOB (bits) Dynamic parameters (dB) 100 Dynamic Parameters (dBc) Distortion vs. AVCC Fs=20MSPS; Icca=40mA; Fin=5MHz Linearity vs. AVCC Fs=20MSPS; Icca=40mA; Fin=5MHz 85 60 Temperature (°C) Temperature (°C) 95 THD_Q 90 40 7 -40 50 Distortion vs. Temperature Fs=20MSPS; Icca=40mA; Fin=2MHz 100 SNR_I 40 Fin (MHz) Linearity vs. Temperature Fs=20MSPS; Icca=40mA; Fin=2MHz 80 30 -30 -40 -50 -60 THD_I SFDR_I -70 -80 -90 THD_Q SFDR_Q -100 -110 -120 2.25 2.35 2.45 2.55 2.65 AVCC (V) 9/20 TSA1204 100 12 90 11 ENOB_I 80 10 SNR_Q SNR_I 70 9 60 SINAD_Q SINAD_I 8 50 40 2.25 ENOB (bits) Dynamic parameters (dB) ENOB_Q 7 Dynamic Parameters (dBc) Distortion vs. DVCC Fs=20MSPS; Icca=40mA; Fin=5MHz Linearity vs. DVCC Fs=20MSPS; Icca=40mA; Fin=5MHz 2.45 2.55 -50 -60 THD_I 2.65 -80 -90 THD_Q -110 2.35 11.5 ENOB_I 80 11 ENOB_Q 10.5 SNR_Q SNR_I 10 65 60 9.5 SINAD_Q 9 55 50 2.25 8.5 Dynamic Parameters (dBc) 12 SINAD_I 2.45 2.55 -50 -60 2.65 THD_I -80 -90 THD_Q -110 2.35 11.5 85 11 80 10.5 ENOB_Q 10 SINAD_I 9 65 60 SINAD_Q 7.5 7 2.75 VCCBE (V) 10/20 8.5 8 55 50 2.25 9.5 3.25 Dynamic Parameters (dBc) 12 ENOB_I SNR_Q 2.45 2.55 2.65 Distortion vs. VCCBE Fs=20MSPS; Icca=40mA; Fin=5MHz ENOB (bits) Dynamic parameters (dB) 90 SNR_I SFDR_Q -100 VCCBI (V) Linearity vs. VCCBE Fs=20MSPS; Icca=40mA; Fin=5MHz 70 SFDR_I -70 VCCBI (V) 75 2.65 -40 -120 2.25 8 2.35 2.55 Distortion vs. VCCBI Fs=20MSPS; Icca=40mA; Fin=5MHz ENOB (bits) Dynamic parameters (dB) 90 70 2.45 DVCC (V) Linearity vs. VCCBI Fs=20MSPS; Icca=40mA; Fin=5MHz 75 SFDR_Q -100 DVCC (V) 85 SFDR_I -70 -120 2.25 6 2.35 -40 -40 -50 -60 SFDR_Q THD_I -70 -80 -90 SFDR_I -100 -110 -120 2.25 THD_Q 2.75 VCCBE (V) 3.25 TSA1204 Linearity vs. Duty Cycle Fs=20MSPS; Icca=40mA; Fin=5MHz Distortion vs. Duty Cycle Fs=20MSPS; Icca=40mA; Fin=5MHz -40 Dynamic parameters (dBc) 12 ENOB_I 11.5 90 11 10.5 80 ENOB_Q SNR_I SINAD_I 70 10 9.5 9 60 SNR_Q 8.5 SINAD_Q ENOB (bits) Dynamic parameters (dB) 100 8 50 7.5 40 7 45 47 49 51 53 -50 -60 SFDR_Q THD_Q -70 -80 -90 SFDR_I THD_I -100 -110 -120 45 55 47 Positive Duty Cycle (%) 49 51 53 55 Positive Duty Cycle (%) Single-tone 8K FFT at 20Msps - I Channel Fin=5MHz; Icca=40mA, Vin@-1dBFS Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) Dual-tone 8K FFT at 20Msps - I Channel Fin1=9.7MHz; Fin2=10.7MHz; Icca=40mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-76dBc Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) 11/20 TSA1204 APPLICATION NOTE DETAILED INFORMATION The TSA1204 is a dual-channel, 12-bit resolution analog to digital converter based on a pipeline structure and the latest deep submicron CMOS process to achieve the best performances in terms of linearity and power consumption. Each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled on both channels on the rising edge of the clock. The output data is valid on the rising edge of the clock for I channel and on the falling edge of the clock for Q channel. The digital data out from the different stages must be time delayed depending on their order of conversion. Then a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The structure has been specifically designed to accept differential signals only. COMPLEMENTARY FUNCTIONS Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described as followed. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality. In order to remain in the normal operating mode, this pin should be grounded through a low value of resistor. 12/20 SELECT The digital data out from each ADC cores are multiplexed together to share the same output bus. This prevents from increasing the number of pins and enables to keep the same package as single channel ADC like TSA1201. The selection of the channel information is done through the "SELECT" pin. When set to high level (VIH), the I channel data are present on the bus D0-D11. When set to low level (VIL), the Q channel data are on the output bus D0-D11. Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D11; I channel on the rising edge of the clock and Q channel on the falling edge of the clock. (see timing diagram page 2). REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pins are connected externally to the Analog Ground while VREFP (respectively INCM) are set to their internal voltage of 0.89V (respectively 0.46V). It is recommended to decouple the VREFP and INCM pins in order to minimize low and high frequency noise (refer to Figure 1) Figure 1 : Internal reference and common mode setting 1.03V 330pF 10nF VIN TSA1204 VINB 4.7uF VREFP INCM VREFM 0.57V 330pF 10nF 4.7uF TSA1204 External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (Refer to table’ OPERATING CONDITIONS’ page 4 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). Using internal VREFP, the dynamic range is 1.8V. The best linearity and distortion performances are achieved with a dynamic range above 2Vpp and by increasing the VREFM voltage instead of lowering the VREFP one. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. Figure 2 : External reference setting 1kΩ node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1.4Vpp amplitude input signal, so the resultant differential amplitude is 2.8Vpp. Figure 3 : Differential input configuration with transformer Analog source ADT1-1 1:1 VIN 50Ω 33pF TSA1204 I or Q ch. VINB INCM 330pF 10nF 470nF Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. 330pF 10nF 4.7uF VCCA VREFP VIN TSA1204 VINB VREFM Figure 4 : AC-coupled differential input TS821 TS4041 external reference 50Ω VIN 10nF 100kΩ 33pF common mode DRIVING THE DIFFERENTIAL ANALOG INPUTS The TSA1204 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. As being an high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this 50Ω INCM 100kΩ TSA1204 VINB 10nF Figure 5 shows a DC-coupled configuration with forced VREFP and INCM to the 1V DC analog input while VREFM is connected to ground; we achieve a 2Vpp differential amplitude. 13/20 TSA1204 Figure 5 : DC-coupled 2Vpp differential analog input analog AC+DC VREFP VIN DC TSA1204 VINB analog VREFM INCM DC 330pF 10nF 4.7uF VREFP-VREFM = 1 V Clock input The TSA1204 performance is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption So as to optimize both performance and power consumption of the TSA1204 according the sampling frequency, a resistor is placed between IPOL and the analog Ground pins. Therefore, the total dissipation is adjustable from 10Msps up to 20Msps. The TSA1204 will combine highest performances and lowest consumption at 20Msps when Rpol is equal to 54kΩ. At lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. The table below sums up the relevant data. Figure 6 : Total power consumption optimization depending on Rpol value Fs (Msps) Rpol (kΩ) Optimized power (mW) 14/20 10 120 20 54 95 120 Layout precautions To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is mandatory to prevent noise from coupling onto the input signal. The best compromise is to connect from one part AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the power supplies AVCC, DVCC and VCCBI must be separated from the VCCBE one. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). APPLICATION Digital Interface application Thanks to its wide external buffer power supply range, the TSA1204 is perfectly suitable to plug in to 2.5V low voltage DSPs or digital interfaces as well as to 3.3V ones. Medical Imaging application Driven by the demand of the applications requiring nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs. As a typical system diagram shows figure 7, a narrow input beam of acoustic energy is sent into a living body via the transducer and the energy reflected back is analyzed. TSA1204 Figure 7 : Medical imaging application HV TX amps TX beam former Mux and T/R switches ADC RX beam former TGC amplifier Processing and display noise and very high linearity are mandatory factors. These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues. The input signal is in the range of 2 to 20MHz (mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization. The next RX beam former and processing blocks enable the analysis of the outputs channels versus the input beam. EVAL1204/BA evaluation board The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver. To compensate for skin and tissues attenuation effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the amplification of low voltage signals to the ADC input range. Differential output structure with low The EVAL1204/BA is a 4 layer board with high decoupling and grounding level. The schematic of the evaluation board is reported figure 11 and its top overlay view figure 10. The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 8. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=1dB for static parameters. Figure 8 : Analog to Digital Converter characterization bench HP8644 Sine Wave Generator Data Vin ADC evaluation board Logic Analyzer PC Clk Clk HP8133 Pulse Generator HP8644 Sine Wave Generator 15/20 TSA1204 Operating conditions of the evaluation board: Grounding consideration Find below the connections to the board for the power supplies and other pins: So as to better reject noise on the board, connect on the bottom overlay AG (AGND), DG(DGND), GB1(GNDBI) together from one part, and GB2(GNDBE) with GB3(GNDB3) from the other part. board notation connection internal external voltage (V) voltage (V) AV AVCC 2.5 AG AGND 0 RPI REFPI RMI REFMI CMI INCMI 0.46 <1 RPQ REFPQ 0.89 <1.4 RMQ REFMQ CMQ INCMQ DV Mode select <1 So as to evaluate a single channel or the dual ones, you have to connect on the board the relevant position for the SELECT pin. With the strap connected - to the upper connectors, the I channel at the output is selected. - horizontally, the Q channel at the output is selected - to the lower connectors, both channels are selected, relative to the clock edge. DVCC 2.5 Figure 9 : mode select DG DGND 0 GB1 GNDBI 0 VB1 VCCBI 2.5 GB2 GNDBE 0 VB2 VCCBE 1.8/2.5/3.3 GB3 GNDB3 0 0.89 <1.4 <0.4 <0.4 0.46 SELECT I channel SELECT I/Q channels CLK VB3 VCCB3 DGND DVCC 2.5 Care should be taken for the evaluation board as the outputs of the converter are 2.5V/3.3V (VCCB2) tolerant whereas the 74LCX573 external buffers are operating up to 2.5V. Single and Differential Inputs: The ADC board components are mounted to test the TSA1204 with single analog input; the ADT1-1WT transformer enables the differential drive into the converter; in this configuration, the resistors RSI6, RSI7, RSI8 for I channel (respectively RSQ6, RSQ7, RSQ8 for Q one) are connected as short circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9) are open circuits. The other way is to test it via JI1 and JI1B differential inputs. So, the resistances RSI5, RSI9 for I channel (respectively RSQ5, RSQ9 for Q one) are connected as short circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q one) are open circuits. 16/20 Q channel schematic board Consumption adjustment Before any characterization, care should be taken to adjust the Rpol (Raj1) and therefore Ipol value in function of your sampling frequency. TSA1204 Figure 10 : Printed circuit of evaluation board. 17/20 1 Q JQ1B InQB JI1B InIB RQ19 50 RQ1 50 3 3 RSQ61 0 RI19 50 RI1 50 RSI6 1 0 0 0 NC RSQ9 4 RSQ8 T2-AT1-1WT 0 0 NC RSQ7 TQ2 6 0 2 RSQ5 ANALOGIC VCC GND JA AVCC 0 NC RSI9 4 RSI8 T2-AT1-1WT 0 2 RSI7 + 0NM 0NM 0 NC TI2 6 RSI5 R22 R21 C42 47µF 10µF C41 0NM R23 CI9 JQ2 VREFQ 330pF CQ8 NM 33pF CQ9 CQ6 330pF CQ1 470nF 10nF CQ10 C2 NM 33pF C4 CI6 470nF 10nF C3 330pF CI8 CI1 470nF 10nF CI10 0NM R24 CI31 CQ30 330pF 470nF 10nF 1K R2 330pF CI30 CI12 C36 47µF C23 10µF C22 470nF C21 10nF AVCC DVCC AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND C51 330pF C52 10nF C14 330pF ADC DUAL12B 8-14bits ADC C32 47µF C31 10µF C13 470nF C11 10nF DIGITAL JD CON2 2 1 J27 CLK 100nF J4 50 C5 R3 DVCC SW1 CD3 330pF CD2 10nF CD1 470nF DVcc J9 10µF R5 50 J25 CKDATA C35 VCCB2 47µF C19 470nF C18 10nF C17 330pF C29 36 35 34 33 32 31 30 29 28 27 26 25 330pF 10nF C25 470nF C27 C28 VCCB2 CON2 VCCB2 2 1 J26 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11(MSB) VCCBE GNDBE 47µF C43 10µF C53 470nF AVCC VCCB1 C44 STG719 IN S2 Vcc D GNDS1 U1 C15 10nF C10 330pF 330pF 470nF 10nF C20 330pF CQ11 1 2 3 4 5 6 7 8 9 10 11 12 330pF CI11 CQ12 CQ13 470nF 10nF CI13 REFP REFM INCM CQ31 CQ32 Raj1 47K 470nF 10nF CI32 47K R11 R12 47K S5 SW-SPST VCCB1 VCCB2 S4 SW-SPST C16 470nF + JI2 VREFI + VCC GND + REFP REFM INCM 48 47 46 45 44 43 42 41 40 39 38 37 REFPI REFMI INCMI AVCC AVCC OEB VCCBI VCCBI GNDBE VCCBE D0(LSB) D1 18/20 + REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI J17 BUFPOW 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 10nF 330pF C26 C33 C40 C38 330pF 10nF 470nF OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74LCX573 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE 470nF C39 47µF C37 C34 VCCB3 74LCX573 VCCB2 GndB1 VccB1 GndB2 VccB2 GndB3 VccB3 VCCB1 + 13 14 15 16 17 18 19 20 21 22 23 24 NM: non soudé 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 Normal mode Test mode Switch S5 Open Short VCCB3 OEB Mode Normal mode High Impedance output mode Switch S4 Open Short analog input with transformer (default) single input differential input CLK D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RS5 RS6 RS7 RS8 RS9 C C C C C C C J6 CLK GND D11 GND D10 GND D9 GND D8 GND D7 GND D6 GND D5 GND D4 GND D3 GND D2 GND D1 GND D0 GND TSA1204 Figure 11 : TSA1204 Evaluation board schematic + TSA1204 Figure 12 : Printed circuit board - List of components Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC 0NC R24 0NC R23 R21 0NC R22 0NC 1K R2 47K R12 47K R11 Raj1 200K C23 C41 C29 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 trimmer CQ11 330pF 10µF 1210 CI8 330pF 10µF 1210 C14 330pF 10µF 1210 CI30 330pF Footprint Name 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 C26 C20 C33 C25 CI1 CQ1 C34 C42 C35 C44 C36 C32 C37 CQ10 C28 CI10 CQ32 CQ13 CI32 C13 C53 C16 C3 C22 CI13 C38 CD1 C19 Part Type 330pF 330pF 330pF 330pF 33pF 33pF 47µF 47µF 47µF 47µF 47µF 47µF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 connector 805 805 805 NC: non soldered 805 19/20 TSA1204 PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE A A2 e 48 A1 37 36 12 25 E3 E1 E B 1 0,10 mm .004 inch SEATING PLANE c 24 L1 D3 D1 D L 13 K 0,25 mm .010 inch GAGE PLANE Millimeters Inches Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 0.45 Typ. 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. Min. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.75 0.018 Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 0° (min.), 7° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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