TSA1005 DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER ■ 10-bit, dual-channel A/D converter in deep NC NC VCCBE GNDBE VCCBI VCCBI OEB 36 D0(LSB) 35 D1 AGND 3 34 D2 INIB 4 33 D3 AGND 5 32 D4 IPOL 6 31 D5 TSA1005 AVCCB 7 30 D6 29 D7 AGND 8 28 D8 AGND 10 27 D9(MSB) INBQ 11 26 VCCBE 25 GNDBE AGND 12 13 14 15 16 17 18 19 20 21 22 23 24 BLOCK DIAGRAM +2.5V/3.3V CLK SELECT OEB VCCBE Timing VINI AD 10 I channel VINBI VINCMI 10 common mode VREFPI REF I VREFMI IPOL M U X Polar. 10 10 Buffers D0 TO D9 VREFPQ VREFMQ REF Q common mode VINQ VINBQ AD 10 Q channel 10 GND ORDER CODE GNDBI DVCC DGND SELECT CLK DGND DVCC AVCC AGND INCMQ REFMQ REFPQ Medical imaging and ultrasound I/Q signal processing applications High speed data acquisition system Portable instrumentation High resolution fax and scanners GNDBE PACKAGE Temperature Range Status Conditioning TSA1005-20IF -40°C to +85°C Sample Tray TSA1005-20IFT -40°C to +85°C Sample Tape & Reel TSA1005I-40IF 0°C to +85°C Production Tray TSA1005-40IFT 0°C to +85°C Production Tape & Reel June 2003 41 40 39 38 37 2 INI VINCMQ APPLICATIONS EVAL1005-20/BA EVAL1005-40/BA 44 43 42 INQ 9 The TSA1005 belongs to a new generation of high speed, dual-channel Analog to Digital converters, processed in a mainstream 0.25 µm CMOS technology and yielding high performances. The TSA1005 is specifically designed for applications requiring a very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction, providing high static linearity at 20/40 Msp, and Fin = 10 MHz. For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. Each ADC output is multiplexed on a common bus with small number of pins. A tri-state capability is available for the output signals, allowing for chip selection. The input signals of the ADC must be differentially driven. The TSA1005 is supports an extended (0 to +85°C) temperature range, and is available in the small 48-pin TQFP package. Part Number AVCC 48 47 46 45 AGND 1 DESCRIPTION ■ ■ ■ ■ ■ AVCC ■ ■ ■ INCMI ■ index corner REFMI ■ REFPI ■ PIN CONNECTIONS (top view) submicron CMOS technology, 20/40Msps Single supply voltage: 2.5V Independent supply for CMOS output stage with 2.5V/3.3V capability ENOB=9.5 @ 20Msps, ENOB=9.2 @ 40Msps, Fin=10MHz SFDR typically up to 62.5dB @ 40Msps, Fin=10MHz. 1GHz analog bandwidth Track-and-Hold Common clocking between channels Multiplexed outputs 7 × 7 mm TQFP48 Evaluation board 1/22 TSA1005 ABSOLUTE MAXIMUM RATINGS Symbol Parameter AVCC Analog Supply voltage (1) DVCC Digital Supply voltage 1) VCCBE Digital buffer Supply voltage 1) VCCBI 1) IDout Tstg ESD Digital buffer Supply voltage Digital output current Storage temperature HBM: Human Body Model(2) CDM: Charged Device Values Unit 0 to 3.3 V 0 to 3.3 V 0 to 3.6 V 0 to 3.3 V -100 to 100 +150 mA °C 2 kV 1.5 Model(3) Latch-up Class(4) A 1 All voltage values, except for differential voltage, are with respect to the network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC 2 ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ 3 Discharge to Ground of a device that has been previously charged. 4 Corporate ST Microelectronics procedure number 0018695 OPERATING CONDITIONS Symbol AVCC DVCC VCCBE VCCBI VREFPI VREFPQ VREFMI VREFMQ INCMI INCMQ 2/22 TSA1005-20(1) Parameter TSA1005-40 Min. Typ. Max. Min. Typ. Max. Unit Analog Supply voltage Digital Supply voltage External Digital buffer Supply voltage Internal Digital buffer Supply voltage 2.25 2.25 2.25 2.25 2.5 2.5 2.5 2.5 2.7 2.7 3.5 2.7 2.25 2.25 2.25 2.25 2.5 2.5 2.5 2.5 2.7 2.7 3.5 2.7 V V V V Forced top voltage reference 0.94 1.4 0.94 1.4 V 0 0.4 0 0.4 V 0.2 1 0.2 1 V Forced bottom reference voltage Forced input common mode voltage TSA1005 PIN CONNECTIONS (top view) NC NC VCCBE GNDBE 44 43 42 VCCBI VCCBI 47 46 45 OEB AVCC AVCC 48 INCMI REFMI REFPI index corner 41 40 39 38 37 36 D0(LSB) AGND 1 2 35 D1 AGND 3 34 D2 INIB 4 33 D3 AGND 5 32 D4 INI 31 D5 IPOL 6 TSA1005 AVCCB 7 30 D6 29 D7 AGND 8 INQ 9 28 D8 AGND 10 27 D9(MSB) INBQ 11 26 VCCBE 25 GNDBE AGND 12 13 14 15 16 17 18 19 20 21 22 23 24 GNDBI DVCC DGND SELECT CLK DGND DVCC AVCC AGND INCMQ REFMQ REFPQ PIN DESCRIPTION Pin No Name 1 AGND 2 INI 3 AGND 4 INBI 5 AGND 6 IPOL Description Analog ground Observation 0V I channel analog input Analog ground 0V I channel inverted analog input Analog ground 0V Analog bias current input Pin No Name Description Observation 25 GNDBE Digital buffer ground 26 VCCBE Digital Buffer power supply 2.5V/3.3V 27 D9(MSB) Most Significant Bit output CMOS output (2.5V/3.3V) 28 D8 Digital output CMOS output (2.5V/3.3V) 29 D7 Digital output CMOS output (2.5V/3.3V) 30 D6 Digital output CMOS output (2.5V/3.3V) 0V 7 AVCC Analog power supply 2.5V 31 D5 Digital output CMOS output (2.5V/3.3V) 8 AGND Analog ground 0V 32 D4 Digital output CMOS output (2.5V/3.3V) 33 D3 Digital output CMOS output (2.5V/3.3V) 0V 34 D2 Digital output CMOS output (2.5V/3.3V) 35 D1 0V 36 D0(LSB) 37 NC Non connected 38 NC Non connected 39 VCCBE 9 INQ 10 AGND Q channel analog input Analog ground 11 INBQ Q channel inverted analog input 12 AGND Analog ground 13 REFPQ Q channel top reference voltage 14 REFMQ Q channel bottom reference voltage 15 INCMQ Q channel input common mode 16 AGND Analog ground 0V 40 GNDBE Digital buffer ground 0V 17 AVCC Analog power supply 2.5V 41 VCCBI Digital Buffer power supply 2.5V 2.5V 0V Digital output CMOS output (2.5V/3.3V) Least Significant Bit output CMOS output (2.5V/3.3V) Digital Buffer power supply 2.5V/3.3V - See Application Note 18 DVCC Digital power supply 2.5V 42 VCCBI Digital Power Supply 19 DGND Digital ground 0V 43 OEB Output Enable input 2.5V/3.3V CMOS input 20 CLK Clock input 2.5V CMOS input 44 AVCC Analog power supply 2.5V 21 SELECT Channel selection 2.5V CMOS input 45 AVCC Analog power supply 2.5V 22 DGND Digital ground 0V 46 INCMI I channel input common mode 23 DVCC Digital power supply 2.5V 47 REFMI I channel bottom reference voltage 0V 24 GNDBI Digital buffer ground 0V 48 REFPI I channel top reference voltage 3/22 TSA1005 ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V, VREFM = 0 V Tamb = 25°C (unless otherwise specified) TIMING CHARACTERISTICS TSA1005-20(1) Symbol TSA1005-40 Parameter. Min. Typ. 0.5 Max. Min. 20 0.5 Typ. Max. Unit 40 MHz 55 % FS Sampling Frequency DC Clock Duty Cycle 50 TC1 Clock pulse width (high) 25 12.5 ns TC2 Clock pulse width (low) 25 12.5 ns Tod Data Output Delay (Clock edge to Data Valid) - 10pF load capacitance 5 5 ns 45 50 Tpd I Data Pipeline delay for I channel 7 7 cycles Tpd Q Data Pipeline delay for Q channel 7.5 7.5 cycles Ton Falling edge of OEB to digital output valid data 1 1 ns Toff Rising edge of OEB to digital output tri-state 1 1 ns 1 Preliminary data. TIMING DIAGRAM Simultaneous sampling on I/Q channels N+4 N+3 I N N+13 N+12 N+6 N+11 N+7 N+2 N-1 N+5 N+1 N+8 N+9 Q N+10 CLK Tpd I + Tod Tod SELECT CLOCK AND SELECT CONNECTED TOGETHER OEB sample N-8 I channel sample N-6 Q channel sample N Q channel sample N+1 Q channel sample N+2 Q channel DATA OUTPUT sample N-9 I channel 4/22 sample N-7 Q channel sample N+1 sample N+2 I channel I channel sample N+3 I channel TSA1005 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25°C (unless otherwise specified) ANALOG INPUTS Symbol TSA1005-20(1) Parameter VIN-VINB Cin Req BW Full scale reference voltage Input capacitance Equivalent input resistor Analog Input Bandwidth Min. Typ. Max. Min. Typ. Max. Unit 1.1 2.0 7.0 3.3 2.8 1.1 2.0 7 1.6 2.8 Vpp pF KΩ Vin Full scale, Fs max Effective Resolution Bandwidth ERB TSA1005-40 1000 1000 MHz 70 70 MHz 1 Preliminary data DIGITAL INPUTS AND OUTPUTS Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock and Select inputs VIL Logic "0" voltage VIH Logic "1" voltage 2.0 2.5 V OEB input VIL Logic "0" voltage VIH Logic "1" voltage 0 0.25 x VCCBE 0.75 x VCCBE VCCBE V V Digital Outputs VOL Logic "0" voltage Iol=10µA VOH Logic "1" voltage Ioh=10µA IOZ High Impedance leakage current OEB set to VIH CL Output Load Capacitance 0 0.1 x VCCBE 0.9 x VCCBE VCCBE -1.67 0 V V 1.67 µA 15 pF REFERENCE VOLTAGE Symbol VREFPI VREFPQ VINCMI VINCMQ Parameter TSA1005-20(1) TSA1005-40 Min. Typ. Max. Min. Typ. Max. Unit Top internal reference voltage 0.81 0.88 0.94 0.81 0.88 0.94 V Input common mode voltage 0.41 0.46 0.50 0.41 0.46 0.50 V 5/22 TSA1005 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V Tamb = 25°C (unless otherwise specified) POWER CONSUMPTION Symbol Parameter TSA1005-20(1) Min. Typ. TSA1005-40 Max. Min. Typ. Max. Unit ICCA Analog Supply current 30 69.5 72.8 mA ICCD Digital Supply Current 4 3.5 3.6 mA ICCBE Digital Buffer Supply Current (10pF load) 6 6.5 6.9 mA ICCBI Digital Buffer Supply Current 274 131 149 uA Power consumption in normal operation mode 100 199.5 207.7 mW Thermal resistance (TQFP48) 80 80 TSA1005-20(1) TSA1005-40 Pd Rthja °C/W ACCURACY Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit OE Offset Error 2.97 2.97 LSB GE Gain Error 0.1 0.1 % DNL Differential Non Linearity ±0.5 ±0.6 LSB INL Integral Non Linearity ±0.7 ±1 LSB - Monotonicity and no missing codes Guaranteed Guaranteed DYNAMIC CHARACTERISTICS Symbol TSA1005-20(1) Symbol Min. SFDR SNR THD SINAD ENOB Spurious Free Dynamic Range Typ. Max. TSA1005-40 Min. -73 57.1 Typ. Max. Unit -62.6 -58.1 dBc -57.5 dBc Signal to Noise Ratio 60 Total Harmonics Distortion -73 59.8 Signal to Noise and Distortion Ratio 59 54.9 57.3 dB Effective number of bits 9.5 8.8 9.2 bits -62 dB MATCHING BETWEEN CHANNELS Symbol Parameter TSA1005-20(1) Min. Typ. Max. TSA1005-40 Typ. Max. Unit GM Gain match 0.04 Min. 0.04 1 % OM Offset match 0.5 0.5 LSB PHM Phase match 1 1 dg XTLK Crosstalk rejection 85 85 dB 1 Preliminary data 6/22 TSA1005 Static parameter: Integral Non Linearity Fs=20MSPS; Icca=30mA; Fin=10MHz 1 INL (LSBs) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 200 400 600 800 1000 Output Code Static parameter: Integral Non Linearity Fs=40MSPS; Icca=45mA; Fin=10MHz 2 1.5 INL (LSBs) 1 0.5 0 -0.5 -1 -1.5 -2 0 200 400 600 800 1000 Output Code Static parameter: Differential Non Linearity Fs=20MSPS; Icca=30mA; Fin=10MHz 1 0.8 DNL (LSBs) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 200 400 600 800 1000 Output Code 7/22 TSA1005 Static parameter: Differential Non Linearity Fs=40MSPS; Icca=45mA; Fin=10MHz 1 0.8 DNL (LSBs) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 200 400 600 800 1000 Output Code Distortion vs. Fin Fs=20MHz; Icca=30mA Linearity vs. Fin Fs=20MHz; Icca=30mA 90 ENOB_Q 11 ENOB_I 80 10 70 9 SNR_Q SINAD_Q 60 8 50 7 SNR_I SINAD_I 40 6 30 20 40 -20 -40 SFDR_I THD_I -60 -80 -100 THD_Q 0 60 20 40 Linearity vs. Fin Fs=40MHz; Icca=45mA Distortion vs. Fin Fs=40MHz; Icca=45mA 90 9 ENOB_Q 80 8 SNR_Q SINAD_Q 7 60 6 50 SNR_I SINAD_I 5 40 30 4 0 20 40 Fin (MHz) 8/22 60 Dynamic parameters (dBc) 10 ENOB (bits) Dynamic parameters (dB) 100 70 60 Fin (MHz) Fin (MHz) ENOB_I SFDR_Q -120 -140 5 0 Dynamic parameters (dBc) 0 12 ENOB (bits) Dynamic parameters (dB) 100 0 -20 -40 THD_I SFDR_I -60 -80 SFDR_Q THD_Q -100 -120 0 20 40 Fin (MHz) 60 TSA1005 Linearity vs. AVCC Fs=20MSPS; Icca=30mA; Fin=5MHz 9.8 75 ENOB_I ENOB_Q 9.6 9.4 70 9.2 65 SNR_Q 9 SINAD_Q 8.8 60 55 8.6 SINAD_I 8.4 SNR_I 8.2 50 2.25 Dynamic Parameters (dBc) 10 ENOB (bits) Dynamic parameters (dB) 80 Distortion vs. AVCC Fs=20MSPS; Icca=30mA; Fin=5MHz 2.45 2.55 -40 -50 2.65 -70 -80 -90 THD_I SFDR_I -100 -110 2.35 2.45 10 9.5 90 9 ENOB_I 8.5 80 8 70 7.5 SINAD_Q 7 60 40 2.25 6.5 6 SNR_I SINAD_I 5.5 Dynamic Parameters (dBc) Fs=40MSPS; Icca=45mA; Fin=5MHz ENOB (bits) Dynamic parameters (dB) 100 50 2.45 2.55 -30 -40 -50 2.65 -70 -80 SFDR_I -90 THD_I -100 -110 2.35 Linearity vs. DVCC Fs=20MSPS; Icca=30mA; Fin=10MHz ENOB_I 9.6 9.4 70 9.2 SNR_Q 9 SNR_I 8.8 60 55 8.6 SINAD_I 8.4 SINAD_Q 8.2 50 2.25 8 2.35 2.45 DVCC (V) 2.55 2.65 Dynamic Parameters (dBc) 10 9.8 65 2.55 2.65 Distortion vs. DVCC Fs=20MSPS; Icca=30mA; Fin=10MHz ENOB (bits) Dynamic parameters (dB) 80 ENOB_Q 2.45 AVCC (V) AVCC (V) 75 SFDR_Q THD_Q -60 -120 2.25 5 2.35 2.65 Distortion vs. AVCC Linearity vs. AVCC Fs=40MSPS; Icca=45mA; Fin=5MHz SNR_Q 2.55 AVCC (V) AVCC (V) ENOB_Q SFDR_Q THD_Q -60 -120 2.25 8 2.35 -30 -40 -50 -60 THD_Q SFDR_Q -70 -80 -90 THD_I SFDR_I -100 -110 -120 2.25 2.35 2.45 2.55 2.65 DVCC (V) 9/22 TSA1005 Dynamic parameters (dB) 100 10 9.5 ENOB_Q 9 ENOB_I 8.5 80 8 70 7.5 SINAD_Q SNR_Q 7 60 50 6.5 SINAD_I SNR_I ENOB (bits) 90 6 5.5 40 2.25 Dynamic Parameters (dBc) Distortion vs. DVCC Fs=40MSPS; Icca=45mA; Fin=10MHz Linearity vs. DVCC Fs=40MSPS; Icca=45mA; Fin=10MHz 2.45 2.55 -20 -40 2.65 -80 -100 THD_I THD_Q 2.35 2.45 85 9.8 9.6 ENOB_Q 9.4 75 9.2 70 9 65 8.8 SNR_Q 8.6 60 55 50 2.25 8.4 SINAD_I 8.2 SINAD_Q Dynamic Parameters (dBc) 10 ENOB (bits) Dynamic parameters (dB) 90 SNR_I 2.45 2.55 -40 -50 2.65 THD_Q -60 -80 -90 -110 2.35 2.45 9.5 85 9 ENOB_Q 8.5 75 8 70 7.5 7 SNR_Q 6.5 60 55 50 2.25 6 SINAD_I 5.5 SNR_I 5 2.35 2.45 2.55 VCCBI (V) 10/22 2.65 Dynamic Parameters (dBc) 10 SINAD_Q 2.65 Distortion vs. VCCBI Fs=40MSPS; Icca=45mA; Fin=10MHz ENOB (bits) Dynamic parameters (dB) 90 65 2.55 VCCBI (V) Linearity vs. VCCBI Fs=40MSPS; Icca=45mA; Fin=10MHz 80 SFDR_I THD_I -100 VCCBI (V) ENOB_I SFDR_Q -70 -120 2.25 8 2.35 2.65 Distortion vs. VCCBI Fs=20MSPS; Icca=30mA; Fin=10MHz Linearity vs. VCCBI Fs=20MSPS; Icca=30mA; Fin=10MHz 80 2.55 DVCC (V) DVCC (V) ENOB_I SFDR_I SFDR_Q -60 -120 2.25 5 2.35 0 -40 -50 THD_Q -60 SFDR_Q -70 -80 -90 THD_I SFDR_I -100 -110 -120 2.25 2.35 2.45 VCCBI (V) 2.55 2.65 TSA1005 10 85 9.8 ENOB_I 80 9.6 ENOB_Q 9.4 75 9.2 70 9 65 8.8 SNR_I SINAD_I 8.6 60 8.4 SNR_Q 55 ENOB (bits) Dynamic parameters (dB) 90 SINAD_Q 8.2 50 Dynamic Parameters (dBc) Distortion vs. VCCBE Fs=20MSPS; Icca=30mA; Fin=10MHz Linearity vs. VCCBE Fs=20MSPS; Icca=30mA; Fin=10MHz 2.3 2.8 THD_Q -65 -70 -75 -80 -85 THD_I -95 1.8 3.3 2.3 9.8 9.6 ENOB_Q 9.4 75 9.2 70 9 8.8 SINAD_I 8.6 60 8.4 55 SINAD_Q SNR_Q 50 2.25 8.2 Dynamic Parameters (dBc) 85 ENOB (bits) Dynamic parameters (dB) 10 SNR_I -30 -40 -50 3.25 -70 -80 THD_I -90 SFDR_I -100 -110 2.75 Distortion vs. Duty Cycle Fs=20MHz; Icca=30mA; Fin=5MHz Linearity vs. Duty Cycle Fs=20MHz; Icca=30mA; Fin=5MHz -40 9.5 ENOB_Q 80 9 75 70 8.5 SNR_I SINAD_I 8 60 55 7.5 SINAD_Q SNR_Q 50 7 45 47 49 51 53 Positive Duty Cycle (%) 55 Dynamic parameters (dBc) 10 85 ENOB (bits) Dynamic parameters (dB) 90 65 3.25 VCCBE (V) VCCBE (V) ENOB_I SFDR_Q THD_Q -60 -120 2.25 8 2.75 3.3 Distortion vs. VCCBE Fs=40MSPS; Icca=45mA; Fin=10MHz 90 65 2.8 VCCBE (V) Linearity vs. VCCBE Fs=40MSPS; Icca=45mA; Fin=10MHz ENOB_I SFDR_I -90 VCCBE (V) 80 SFDR_Q -100 8 1.8 -60 -50 SFDR_Q -60 THD_Q -70 -80 -90 SFDR_I THD_I -100 -110 -120 45 47 49 51 53 55 Positive Duty Cycle (%) 11/22 TSA1005 Linearity vs. Duty Cycle Fs=40MHz; Icca=45mA; Fin=5MHz Distortion vs. Duty Cycle Fs=40MHz; Icca=45mA; Fin=5MHz 10 Dynamic parameters (dBc) -40 9.5 90 9 ENOB 8.5 80 8 70 SNR 7.5 SINAD 7 60 6.5 ENOB (bits) Dynamic parameters (dB) 100 6 50 5.5 40 5 45 47 49 51 53 -50 SFDR -60 -70 -80 THD -90 -100 -110 -120 55 45 47 Positive Duty Cycle (%) 49 51 53 Positive Duty Cycle (%) Single-tone 8K FFT at 24.8Msps - Q Channel Fin=10MHz; Icca=30mA, Vin@-1dBFS Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 2 4 6 8 10 12 Frequency (MHz) Single-tone 8K FFT at 39.7Msps - Q Channel Fin=10MHz; Icca=45mA, Vin@-1dBFS Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 2 4 6 8 10 12 Frequency (MHz) 12/22 14 16 18 20 55 TSA1005 DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Static measurements are performed using a histogram method with on a 2 MHz input signal, sampled at 40 Msps, which is high enough to fully characterize the test frequency response. An input level of +1 dBFS is required to saturate the signal. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD 2Ao = SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao = 6.02 × ENOB + 1.76dB + 20 log (2A0/FS) Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 40 Msps. The ENOB is expressed in bits. The input level is -1 dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 dB. Higher values can be achieved with smaller input levels. Spurious Free Dynamic Range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. 13/22 TSA1005 APPLICATION NOTE DETAILED INFORMATION The TSA1005 is a dual-channel, 10-bit resolution analog to digital converter based on a pipeline structure and the latest deep sub micron CMOS process to achieve the best performances in terms of linearity and power consumption. Each channel achieves 10-bit resolution through the pipeline structure. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled on both channels on the rising edge of the clock. The output data is valid on the rising edge of the clock for I channel and on the falling edge of the clock for Q channel. The digital data out from the different stages must be time delayed depending on their order of conversion. Then a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The structure has been specifically designed to accept differential signals. The TSA1005 is pin to pin compatible with the dual 12bits/20Msps TSA1204 and the dual 12bits/ 40Msps TSA1203. COMPLEMENTARY FUNCTIONS Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described as followed. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality. In order to remain in the normal operating mode, this pin should be grounded through a low value of resistor. SELECT and enables to keep the same package as single channel ADC like TSA1002. The selection of the channel information is done through the "SELECT" pin. When set to high level (VIH), the I channel data are present on the bus D0-D9. When set to low level (VIL), the Q channel data are on the output bus D0-D9. Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D9; I channel on the rising edge of the clock and Q channel on the falling edge of the clock. (see timing diagram page 2). REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pins are connected externally to the Analog Ground while VREFP (respectively INCM) are set to their internal voltage of 0.88V (respectively 0.46V). It is recommended to decouple the VREFP and INCM in order to minimize low and high frequency noise (refer to Figure 1) Figure 1: Internal reference and common mode setting 330pF 10nF VIN 4.7uF VREFP TSA1005 VINB INCM 330pF 10nF 4.7uF VREFM The digital data out from each ADC core are multiplexed together to share the same output bus. This prevents from increasing the number of pins 14/22 TSA1005 External reference and common mode Each of the voltages VREFP and INCM can be fixed externally to better fit to the application needs (Refer to table ’OPERATING CONDITIONS’ page 4 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). Using internal references, the dynamic range is 1.8V. The INCM is the mid voltage of the analog input signal. It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2. 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1.4Vpp amplitude input signal, so the resultant differential amplitude is 2.8Vpp. Figure 3: Differential input configuration with transformer Analog source ADT1-1 1:1 VIN 50Ω 33pF TSA1005 I or Q ch. VINB INCM 330pF 10nF 470nF Figure 2: External reference setting 1kΩ 330pF 10nF 4.7uF VCCA VREFP VIN TSA1005 VINB VREFM TS821 TS4041 external reference Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. Figure 4: AC-coupled differential input DRIVING THE DIFFERENTIAL ANALOG INPUTS The TSA1005 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. As being an high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 15/22 50Ω VIN 10nF 100kΩ 33pF common mode 50Ω INCM 100kΩ TSA1005 VINB 10nF Figure 5: AC-coupled Single-ended input Signal source 10nF VIN 100kΩ 50Ω INCM 33pF TSA1005 100kΩ VINB TSA1005 Clock input APPLICATION The TSA1005 performance is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. Layout precautions The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption So as to optimize both performance and power consumption of the TSA1005 according the sampling frequency, a resistor is placed between IPOL and the analog Ground pins. Therefore, the total dissipation is adjustable from 5Msps up to 40Msps. The TSA1005 will combine highest performances and lowest consumption at 20Msps when Rpol is equal to 70kΩ, at 40Msps when Rpol is equal to 35kΩ. These values are nevertheless dependant on application and environment. At lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. The figure 6 sums up the relevant data. Figure 6: analog current consumption optimization depending on Rpol value To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is mandatory to prevent noise from coupling onto the input signal. The best compromise is to connect from one part AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the power supplies AVCC, DVCC and VCCBI must be separated from the VCCBE one. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). Digital Interface application 100 250 90 200 70 60 150 ICCA 50 40 100 30 20 50 10 RPOL 0 0 5 15 25 35 Fs (MHz) 45 55 Rpol (kOhms) Icca (mA) 80 Thanks to its wide external buffer power supply range, the TSA1005 is perfectly suitable to plug in to 2.5V low voltage DSPs or digital interfaces as well as to 3.3V ones. Medical Imaging application Driven by the demand of the applications requiring nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs. As a typical system diagram shows figure 10, a narrow input beam of acoustic energy is sent into a living body via the transducer and the energy reflected back is analyzed. 16/22 TSA1005 noise and very high linearity are mandatory factors. These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues. The input signal is in the range of 2 to 20MHz (mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization. The next RX beam former and processing blocks enable the analysis of the outputs channels versus the input beam. Figure 7: Medical imaging application HV TX amps TX Mux and AD RX TGC amplifier Proces EVAL1005/BA evaluation board The EVAL1005/BA is a 4-layer board with high decoupling and grounding level. The schematic of the evaluation board is reported figure 11 and its top overlay view figure 10.The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 8. The analog input signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=1dB for static parameters. - SFSR=-1dB for dynamic parameters. The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver. To compensate for skin and tissues attenuation effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the amplification of low voltage signals to the ADC input range. Differential output structure with low Figure 8: Analog to Digital Converter characterization bench HP8644 Sine Wave Generator Data Vin ADC evaluation Logic Clk Clk 17/22 HP8133 Pulse HP8644 Sine Wave Generator PC TSA1005 Operating conditions of the evaluation board: Find below the connections to the board for the power supplies and other pins: board notation connection internal external voltage (V) voltage (V) AV AVCC 2.5 AG AGND 0 RPI REFPI RMI REFMI CMI INCMI 0.46 0.2 to 1 RPQ REFPQ 0.88 0.94 to 1.4 RMQ REFMQ CMQ INCMQ DV DVCC 2.5 DG DGND 0 GB1 GNDBI 0 VB1 VCCBI 2.5 GB2 GNDBE 0 VB2 VCCBE 2.5/3.3 GB3 GNDB3 0 VB3 VCCB3 2.5 0.88 0.94 to 1.4 0 to 0.4 0 to 0.4 0.46 0.2 to 1 Grounding consideration So as to better reject noise on the board, connect on the bottom overlay AG (AGND), DG(DGND), GB1(GNDBI) together from one part, and GB2(GNDBE) with GB3(GNDB3) from the other part. Mode select So as to evaluate a single channel or the dual ones, you have to connect on the board the relevant position for the SELECT pin. With the strap connected: - to the upper connectors, the I channel at the output is selected. - horizontally, the Q channel at the output is selected. - to the lower connectors, both channels are selected, relative to the clock edge. Figure 9: mode select SELECT I channel Care should be taken for the evaluation board considering the fact that the outputs of the converter are 2.5V/3.3V (VB2) tolerant whereas the 74LCX573 external buffers are operating up to 2.5V. The ADC outputs on the connector J6 are D11 (MSB) to D2 (LSB). SELECT Q channel I/Q channels CLK DGND DVCC schematic board Consumption adjustment Before any characterization, care should be taken to adjust the Rpol (Raj1) and therefore Ipol value in function of your sampling frequency. Single and Differential Inputs: The ADC board components are mounted to test the TSA1005 with single analog input; the ADT1-1WT transformer enables the differential drive into the converter; in this configuration, the resistors RSI6, RSI7, RSI8 for I channel (respectively RSQ6, RSQ7, RSQ8 for Q one) are connected as short circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9) are open circuits. The other way is to test it via JI1 and JI1B differential inputs. So, the resistances RSI5, RSI9 for I channel (respectively RSQ5, RSQ9 for Q one) are connected as short circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q one) are open circuits. 18/22 TSA1005 Figure 10: Printed circuit of evaluation board. 19/22 1 Q JQ1B InQB JI1B InIB 0 RQ19 50 RQ1 50 3 3 RSQ61 0 RI19 50 RI1 50 RSI6 1 0 JA 0 NC RSQ9 4 RSQ8 T2-AT1-1WT 0 0 NC RSQ7 TQ2 6 0 2 RSQ5 ANALOGIC VCC GND AVCC 0 NC RSI9 4 RSI8 T2-AT1-1WT0 2 RSI7 + 0NM 0 NC TI2 6 RSI5 R22 0NM C41 C42 47µF10µF 0NM R23 CI9 C4 470nF 10nF CQ10 CQ9 33pF CQ1 JQ2 VREFQ 330pF CQ8 NM CQ6 330pF C2 NM 33pF 470nF 10nF C3 CI6 330pF CI8 CI1 470nF 10nF CI10 0NM R24 CI31 CQ30 330pF 470nF 10nF 1K R2 330pF CI30 CI12 1 2 3 4 5 6 7 8 9 10 11 12 330pF CI11 C36 47µF C23 10µF C22 470nF C21 10nF C20 330pF AVCC DVCC 47µF AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND C51 330pF C52 10nF C14 330pF C43 10µF VCCB1 C44 STG719 IN S2 Vcc D GNDS1 U1 C53 470nF AVCC R12 47K S5 SW-SPST C15 10nF C32 47µF C31 10µF C13 470nF C11 10nF C10 330pF 330pF CQ12 CQ11 470nF 10nF CQ13 470nF 10nF CI13 REFP REFM INCM CQ32 CQ31 Raj1 200K 470nF 10nF CI32 47K C16 470nF + R21 R11 S4 SW-SPST VCCB1 VCCB2 ADC DUAL 10B REFPI REFMI INCMI AVCC AVCC OEB VCCBI VCCBI GNDBE VCCBE NC NC JI2 VREFI 48 47 46 45 44 43 42 41 40 39 38 37 VCC GND DIGITAL JD CON2 2 1 J27 CLK 100nF J4 50 C5 R3 DVCC SW1 CD3 330pF CD2 10nF CD1 470nF DVcc D0(LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9(MSB) VCCBE GNDBE 36 35 34 33 32 31 30 29 28 27 26 25 10µF R5 50 J25 CKDATA C35 VCCB2 47µF C19 470nF C18 10nF C17 330pF C29 Ra 330pF 10nF C25 470nF C27 C28 VCCB2 CON2 VCCB2 2 1 J26 + REFP REFM INCM + REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI J17 BUFPOW 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 10nF 330pF C26 OEB VCC D0 Q0 D1 Q1 D2 U3 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74LCX573 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE 470nF C39 47µF C37 C34 VCCB3 C33 C40 C38 330pF 10nF 470nF 74LCX573 VCCB2 GndB1 VccB1 GndB2 VccB2 GndB3 VccB3 VCCB1 + 13 14 15 16 17 18 19 20 21 22 23 24 NM: non soudé 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 Normal mode Test mode Switch S5 Open Short VCCB3 OEB Mode Normal mode High Impedance output mode Switch S4 Open Short analog input with transformer (default) single input differential input CLK D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RS5 RS6 RS7 RS8 RS9 C C C C C C C J6 CLK GND D11 GND (MSB) D10 GND D9 GND D8 GND D7 GND D6 GND D5 GND D4 GND D3 GND D2 GND (LSB) D1 GND D0 GND TSA1005 Figure 11: TSA1005 Evaluation board schematic + + 20/22 TSA1005 Figure 12: Printed circuit board - List of components Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC 0NC R24 0NC R23 R21 0NC R22 0NC 1K R2 47K R12 47K R11 Raj1 200K C23 C41 C29 21/22 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 trimmer CQ11 330pF 10µF 1210 CI8 330pF 10µF 1210 C14 330pF 10µF 1210 CI30 330pF Footprint Name 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 C26 C20 C33 C25 CI1 CQ1 C34 C42 C35 C44 C36 C32 C37 CQ10 C28 CI10 CQ32 CQ13 CI32 C13 C53 C16 C3 C22 CI13 C38 CD1 C19 Part Type 330pF 330pF 330pF 330pF 33pF 33pF 47µF 47µF 47µF 47µF 47µF 47µF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 connector 805 805 805 NC: non soldered 805 TSA1005 PACKAGE MECHANICAL DATA TQFP48 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 1.6 A1 0.05 A2 1.35 B 0.17 C 0.09 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.22 0.27 0.007 0.009 0.20 0.0035 9.00 0.354 D1 7.00 0.276 D3 5.50 0.216 e 0.50 0.020 E 9.00 0.354 E1 7.00 0.276 E3 5.50 0.45 L1 K 0.60 3.5˚ 0.011 0.216 0.75 0.018 1.00 0˚ 0.057 0.0079 D L MAX. 0.063 0.024 0.030 0.039 7˚ 0˚ 3.5˚ 7˚ 0110596/C Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com 22/22