TSA1005-40 DUAL-CHANNEL, 10-BIT, 40MSPS, 150mW A/D CONVERTER Preliminary Data ■ 10-bit, dual-channel A/D converter in deep NC NC VCCBE 44 43 42 GNDBE VCCBI VCCBI OEB 48 47 46 45 AVCC AVCC INCMI ■ ■ ■ ■ index corner REFMI ■ ■ REFPI ■ PIN CONNECTIONS (top view) submicron CMOS technology Single supply voltage: 2.5V Independent supply for CMOS output stage with 2.5V/3.3V capability ENOB=9.4 @ 40Msps, Fin=10MHz SFDR typically up to 73dB @ 40Msps, Fin=10MHz. 40Msps sampling frequency 1GHz analog bandwidth Track-and-Hold Common clocking between channels Multiplexed outputs 41 40 39 38 37 36 D0(LSB) AGND 1 2 35 D1 AGND 3 34 D2 INIB 4 33 D3 INI AGND 5 32 D4 IPOL 6 31 D5 TSA1005-40 AVCCB 7 30 D6 29 D7 AGND 8 INQ 9 28 D8 DESCRIPTION AGND 10 27 D9(MSB) INBQ 11 26 VCCBE The TSA1005-40 is a new generation of high speed, dual-channel Analog to Digital converter processed in a mainstream 0.25µm CMOS technology yielding high performances. The TSA1005-40 is specifically designed for applications requiring very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction to provide high static linearity at Fs=40Msps, and Fin=10MHz. For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references. Each ADC outputs are multiplexed in a common bus with small number of pins. Differential or single-ended analog inputs can be applied. A tri-state capability is available for the outputs, allowing chip selection. The TSA1005-40 is available in extended (0 to +85°C) temperature range, in a small 48 pins TQFP package. AGND 12 GNDBI DVCC DGND SELECT CLK DGND DVCC AVCC Package Condition ing Marking TSA1005-40IF 0°C to +85°C TQFP48 Tray SA1005I 0°C to +85°C TQFP48 Tape & Reel SA1005I September 2002 CLK SELECT OEB VCCBE Timing VINI AD 10 I channel VINBI VINCMI 10 common mode VREFPI REF I VREFMI IPOL M U X Polar. 10 10 Buffers D0 TO D9 VREFPQ REF Q VREFMQ VINCMQ common mode AD 10 10 Q channel GND GNDBE PACKAGE 7 × 7 mm TQFP48 TSA1005-40IFT EVAL1005/BA AGND Temperature Range INCMQ Part Number REFMQ ORDER CODE 23 24 +2.5V/3.3V VINBQ Medical imaging and ultrasound I/Q signal processing applications High speed data acquisition system Portable instrumentation High resolution fax and scanners 17 18 19 20 21 22 REFPQ ■ ■ ■ ■ ■ 14 15 16 BLOCK DIAGRAM VINQ APPLICATIONS 25 GNDBE 13 Evaluation board 1/19 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice TSA1005-40 ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V Tamb = 25°C (unless otherwise specified) DYNAMIC CHARACTERISTICS Symbol Parameter Test conditions Min Typ Max Unit SFDR Spurious Free Dynamic Range -73 dBc SNR Signal to Noise Ratio 59 dB THD Total Harmonics Distortion -73 dBc Signal to Noise and Distortion Ratio 58.5 dB SINAD TIMING CHARACTERISTICS Symbol Parameter Test conditio ns Min Typ Max Unit 40 MHz 55 % FS Sampling Frequency 0.5 DC Clock Duty Cycle 45 TC1 Clock pulse width (high) 12.5 ns TC2 Clock pulse width (low) 12.5 ns Tod Data Output Delay (Clock edge to Data Valid) 5 ns 50 10pF load capacitance Tpd I Data Pipeline delay for I channel 7 cycles Tpd Q Data Pipeline delay for Q channel 7.5 cycles Ton Falling edge of OEB to digital output valid data 1 ns Toff Rising edge of OEB to digital output tri-state 1 ns TIMING DIAGRAM Simultaneous sampling on I/Q channels N+4 N+3 I N N+13 N+6 N+12 N+11 N+7 N+2 N-1 N+5 N+1 N+8 N+9 Q N+10 CLK Tpd I + Tod Tod SELECT CLOCK AND SELECT CONNECTED TOGETHER OEB sample N-8 I channel sample N-6 Q channel sample N Q channel sample N+1 Q channel sample N+2 Q channel DATA OUTPUT sample N-9 I channel 2/19 sample N-7 Q channel sample N+1 sample N+2 sample N+3 I channel I channel I channel TSA1005-40 ABSOLUTE MAXIMUM RATINGS Symbol Parameter AVCC Analog Supply voltage 1) DVCC Digital Supply voltage 1) VCCBE VCCBI IDout Tstg ESD Values Unit 0 to 3.3 V 0 to 3.3 V Digital buffer Supply voltage 1) 0 to 3.6 V Digital buffer Supply voltage Digital output current Storage temperature 1) 0 to 3.3 V -100 to 100 +150 mA °C HBM: Human Body Model2) CDM: Charged Device 2 kV 1.5 Model3) Latch-up Class 4) A 1). All voltages values, except differential voltage, are with respect to network ground terminal . The magnitude of input and output voltages must not exceed -0.3V or VCC 2). ElectroStati cDischarge pu lse (ESD pulse) simulating a human bod y discharge of 100 pF through 1.5kΩ 3). Discharge to Ground of a device that has been previously charged. 4). Corporate ST Microelectronics procedu renumber 0018695 PIN CONNECTIONS (top view) NC NC 44 VCCBE AVCC 45 NDBE AVCC 46 VCCBI INCMI 47 OEB REFMI 48 VCCBI REFPI i nd ex c or ner 43 42 41 40 39 38 37 36 D 0( L SB ) A GND 1 3 5 D1 INI 2 A GND 3 34 D 2 INIB 4 33 D 3 A GND 5 3 2 D4 IPO L 6 31 D 5 T S A1 00 5-40 A V CC B 7 A GND 8 INQ 9 30 D 6 29 D 7 28 D 8 A GND 10 2 7 D 9( M SB ) INB Q 2 6 VC C B E 11 25 GND BE A GND 12 19 20 21 AGND AVCC DVCC DGND CLK SELECT 22 23 24 GNDBI 18 DVCC 17 DGND 16 INCMQ REFPQ 14 1 5 REFMQ 13 PIN DESCRIPTION Pin No N ame 1 AGND 2 IN I 3 AGND Pin No Name Analog ground D escription 0V Observation 25 GNDBE Description I channel analog input 1Vpp 26 VCCB E D igital Buffer power supply 2.5V/3.3V Analog ground 0V 27 D9(MSB) Most Significant Bit output CMOS output (2.5V/3.3V) D igital buffer ground Observation 0V 4 INB I I channel inverted analog input 1Vpp 28 D8 D igital output CMOS output (2.5V/3.3V) 5 AGND Analog ground 0V 29 D7 D igital output CMOS output (2.5V/3.3V) 6 IPOL Analog bias current input 30 D6 D igital output CMOS output (2.5V/3.3V) 7 AVCC Analog power supply 2.5V 31 D5 D igital output CMOS output (2.5V/3.3V) 8 AGND Analog ground 0V 32 D4 D igital output CMOS output (2.5V/3.3V) 9 IN Q Q channel analog input 1Vpp 33 D3 D igital output CMOS output (2.5V/3.3V) 10 AGND Analog ground 0V 34 D2 D igital output CMOS output (2.5V/3.3V) 11 IN BQ Q channel inverted analog input 1Vpp 35 D1 D igital output CMOS output (2.5V/3.3V) 12 AGND Analog ground 0V 36 D0(LSB) Least Significant Bit output CMOS output (2.5V/3.3V) 13 RE FPQ Q channel top reference voltage 1V 37 NC N on connected 14 REFMQ Q channel bottom reference voltage 0V 38 NC N on connected 15 INCM Q Q channel input common mode 0.5V 39 VCCB E D igital Buffer power supply 16 AGND Analog ground 0V 40 GNDBE D igital buffer ground 0V 17 AVCC Analog power supply 2.5V 41 VCCB I D igital Buffer power supply 2.5V 18 DV CC Digital power supply 2.5V 42 VCCB I D igital Power Supply 2.5V 19 D GND Digital ground 0V 43 OEB Output Enable input 2.5V/3.3V CMOS input Clock input 2.5V CMOS input 44 AVCC Analog power supply 2.5V Channel selection 2.5V CMOS input 45 AVCC Analog power supply 2.5V I channel input common mode 0.5V 2.5V/3.3V - See Application Note 20 CLK 21 SELECT 22 D GND Digital ground 0V 46 IN CMI 23 DV CC Digital power supply 2.5V 47 RE FMI I channel bottom reference voltage 0V 24 GND BI Digital buffer ground 0V 48 REFP I I channel top reference v oltage 1V 3/19 TSA1005-40 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25°C (unless otherwise specified) OPERATING CONDITIONS Symbol Parameter Typ Max Unit AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCBE External Digital buffer Supply voltage 2.25 2.5 3.5 V VCCBI Internal Digital buffer Supply voltage 2.25 2.5 2.7 V Forced top voltage reference 1) 0.6 0.88 1.4 V Forced bottom reference voltage 1) 0 0 0.4 V Forced input common mode voltage 0.2 0.46 1 V VREFPI VREFPQ VREFMI VREFMQ INCMI INCMQ 1) Min Condition VRefP-VRefM>0.3V ANALOG INPUTS Symbol Parameter Test conditions VIN-VINB Full scale reference voltage Cin Input capacitance Req Equivalent input resistor BW Analog Input Bandwidth ERB Effective Resolution Bandwidth Min Typ Max Unit 0.3 2.0 2.8 Vpp Vin@Full Scale, Fs=40Msps 7 pF 1.6 KΩ 1000 MHz 70 MHz DIGITAL INPUTS AND OUTPUTS Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock and Select inputs VIL Logic ”0” voltage VIH Logic ”1” voltage 2.0 2.5 V OEB inpu t VIL Logic ”0” voltage VIH Logic ”1” voltage 0 0.25 x VCCBE 0.75 x VCCBE VCCBE V V Digital Outputs VOL Logic ”0” voltage Iol=10µA VOH Logic ”1” voltage Ioh=10µA IOZ High Impedance leakage current OEB set to VIH CL Output Load Capacitance 4/19 0 0.9 x VCCBE VCCBE -1.67 0 0.1 x VCCBE V V 1.67 µA 15 pF TSA1005-40 CONDITIONS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V Tamb = 25°C (unless otherwise specified) REFERENCE VOLTAGE Symbol VREFPI VREFPQ VINCMI VINCMQ Parameter Test conditions Min Typ Max Unit Top internal reference voltage 0.81 0.88 0.94 V Input common mode voltage 0.41 0.46 0.50 V POWER CONSUMPTION Symbol Parameter Min Typ Max Unit ICCA Analog Supply current 50 mA ICCD Digital Supply Current 4 mA ICCBE Digital Buffer Supply Current (10pF load) 6 mA ICCBI Digital Buffer Supply Current 274 uA Power consumption in normal operation mode 150 mW Thermal resistance (TQFP48) 80 °C/W Pd Rthja ACCURACY Symbol Parameter Min Typ Max Unit OE Offset Error LSB GE Gain Error % DNL Differential Non Linearity ±0.5 LSB INL Integral Non Linearity ±0.7 LSB - Monotonicity and no missing codes Guaranteed MATCHING BETWEEN CHANNELS Symbol Parameter Min Typ Max Unit 1 % GM Gain match 0.04 OM Offset match 0.5 LSB PHM Phase match 1 dg XTLK Crosstalk rejection 85 dB 5/19 TSA1005-40 Static parameter: Integral Non Linearity Fs=40MSPS; Icca=45mA; Fin=10MHz 2 1.5 INL (LSBs) 1 0.5 0 -0.5 -1 -1.5 -2 0 200 400 600 800 1000 800 1000 Output Code Static parameter: Differential Non Linearity Fs=40MSPS; Icca=45mA; Fin=10MHz 1 0.8 DNL (LSBs) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 200 400 600 Output Code Linearity vs. Fin Fs=40MHz; Icca=45mA Distortion vs. Fin Fs=40MHz; Icca=45mA 9 ENOB_I ENOB_Q 80 8 70 SNR_Q SINAD_Q 7 60 6 50 SNR_I SINAD_I 5 40 4 0 20 40 Fin (MHz) 60 Dynamic parameters (dBc) 90 30 6/19 0 10 ENOB (bits) Dynamic parameters (dB) 100 -20 -40 THD_I SFDR_I -60 -80 SFDR_Q THD_Q -100 -120 0 20 40 Fin (MHz) 60 TSA1005-40 10 9.5 90 9 ENOB_Q ENOB_I 8.5 80 8 70 7.5 SNR_Q SINAD_Q 7 60 50 40 2.25 6.5 ENOB (bits) Dynamic parameters (dB) 100 6 SNR_I SINAD_I 5.5 Dynamic Parameters (dBc) Distortion vs. AVCC Fs=40MSPS; Icca=45mA; Fin=5MHz Linearity vs. AVCC Fs=40MSPS; Icca=45mA; Fin=5MHz 2.45 2.55 -40 -50 2.65 -70 -80 SFDR_I -90 THD_I -100 -110 2.35 2.45 Linearity vs. DVCC Fs=40MSPS; Icca=45mA; Fin=10MHz 9 ENOB_I 8.5 80 8 7.5 70 SINAD_Q 7 60 6.5 SINAD_I SNR_I 6 5.5 40 2.25 Dynamic Parameters (dBc) ENOB_Q ENOB (bits) Dynamic parameters (dB) 9.5 50 2.45 2.55 0 -20 -40 2.65 -80 -100 THD_I THD_Q 2.35 2.45 10 85 9.5 9 ENOB_Q 8.5 75 8 70 7.5 65 7 SNR_Q 6.5 60 6 55 SINAD_I 5.5 SNR_I 50 2.25 5 2.35 2.45 -40 2.55 VCCBI (V) 2.65 Dynamic Parameters (dBc) 90 SINAD_Q 2.65 Distortion vs. VCCBI Fs=40MSPS; Icca=45mA; Fin=10MHz ENOB (bits) Dynamic parameters (dB) Linearity vs. VCCBI Fs=40MSPS; Icca=45mA; Fin=10MHz ENOB_I 2.55 DVCC (V) DVCC (V) 80 SFDR_I SFDR_Q -60 -120 2.25 5 2.35 2.65 Distortion vs. DVCC Fs=40MSPS; Icca=45mA; Fin=10MHz 10 100 SNR_Q 2.55 AVCC (V) AVCC (V) 90 SFDR_Q THD_Q -60 -120 2.25 5 2.35 -30 -50 THD_Q -60 SFDR_Q -70 -80 -90 THD_I SFDR_I -100 -110 -120 2.25 2.35 2.45 2.55 2.65 VCCBI (V) 7/19 TSA1005-40 90 10 85 9.8 Dynamic Parameters (dBc) Distortion vs. VCCBE Fs=40MSPS; Icca=45mA; Fin=10MHz 9.6 80 ENOB_Q ENOB_I 9.4 75 9.2 70 9 65 8.8 SNR_I SINAD_I 8.6 60 ENOB (bits) Dynamic parameters (dB) Linearity vs. VCCBE Fs=40MSPS; Icca=45mA; Fin=10MHz 8.4 55 SINAD_Q SNR_Q 50 2.25 8.2 -40 -50 3.25 -70 -80 THD_I -90 SFDR_I -100 -110 2.75 Linearity vs. Duty Cycle Fs=40MHz; Icca=45mA; Fin=5MHz Distortion vs. Duty Cycle Fs=40MHz; Icca=45mA; Fin=5MHz Dynamic parameters (dBc) 9.5 90 9 ENOB 8.5 80 8 SNR 7.5 SINAD 7 60 6.5 ENOB (bits) Dynamic parameters (dB) -40 10 100 6 50 5.5 40 5 45 47 49 3.25 VCCBE (V) VCCBE (V) 70 SFDR_Q THD_Q -60 -120 2.25 8 2.75 -30 51 53 -50 SFDR -60 -70 -80 THD -90 -100 -110 -120 55 45 47 Positive Duty Cycle (%) 49 51 53 Positive Duty Cycle (%) Single-tone 8K FFT at 39.7Msps - Q Channel Fin=10MHz; Icca=45mA, Vin@-1dBFS Power spectrum (dB) 0 -20 -40 -60 -80 -100 -120 -140 2 4 6 8 10 12 Frequency (MHz) 8/19 14 16 18 20 55 TSA1005-40 DEFINITIONS OF SPECIFIED PARAMETERS STATIC PARAMETERS Signal to Noise Ratio (SNR) Static measurements are performed through method of histograms on a 2MHz input signal, sampled at 40Msps, which is high enough to fully characterize the test frequency response. The input level is +1dBFS to saturate the signal. The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Differential Non Linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. DYNAMIC PARAMETERS Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 40Msps. The input level is -1dBFS to measure the linear behavior of the converter. All the parameters are given without correction for the full scale amplitude performance except the calculated ENOB parameter. Spurious Free Dynamic Range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise and Distortion Ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS) SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/ FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. 9/19 TSA1005-40 APPLICATION NOTE DETAILED INFORMATION The TSA1005-40 is a dual-channel, 10-bit resolution analog to digital converter based on a pipeline structure and the latest deep sub micron CMOS process to achieve the best performances in terms of linearity and power consumption. Each channel achieves 10-bit resolution through the pipeline structure. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled on both channels on the rising edge of the clock. The output data is valid on the rising edge of the clock for I channel and on the falling edge of the clock for Q channel. The digital data out from the different stages must be time delayed depending on their order of conversion. Then a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The structure has been specifically designed to accept differential signals. In this case, you will obtain the best performances. Nevertheless, single-ended signals can drive the ADC with few linearity degradation. The TSA1005-20 is pin to pin compatible with the dual 10bits/40Msps TSA1005, the dual 12bits/ 20Msps TSA1204 and the dual 12bits/40Msps TSA1203. COMPLEMENTARY FUNCTIONS Some functionalities have been added in order to simplify as much as possible the application board. These operational modes are described as followed. Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data are then present on the output with a very short Ton delay. Therefore, this allows the chip select of the device. The timing diagram summarizes this functionality. In order to remain in the normal operating mode, this pin should be grounded through a low value of resistor. SELECT The digital data out from each ADC core are multiplexed together to share the same output bus. This prevents from increasing the number of pins and enables to keep the same package as single channel ADC like TSA1002. The selection of the channel information is done through the ”SELECT” pin. When set to high level (VIH), the I channel data are present on the bus D0-D9. When set to low level (VIL), the Q channel data are on the output bus D0-D9. Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D9; I channel on the rising edge of the clock and Q channel on the falling edge of the clock. (see timing diagram page 2). REFERENCES AND COMMON MODE CONNECTION VREFM must be always connected externally. Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. VREFM pins are connected externally to the Analog Ground while VREFP (respectively INCM) are set to their internal voltage of 0.88V (respectively 0.46V). It is recommended to decouple the VREFP and INCM in order to minimize low and high frequency noise (refer to Figure 1) Figure 1 : Internal reference and common mode setting VIN 330pF 10nF 4.7 uF 330pF 10nF 4.7uF VREFP TSA1005 VINB INCM VREFM 10/19 TSA1005-40 External reference and common mode Each of the voltages VREFP and INCM can be fixed externally to better fit to the application needs (Refer to table ’OPERATING CONDITIONS’ page 4 for min/max values). The VREFP, VREFM voltages set the analog dynamic at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). Using internal references, the dynamic range is 1.8V. The INCM is the mid voltage of the analog input signal. might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1Vpp amplitude input signal, so the resultant differential amplitude is 2Vpp. Figure 3 : Differential input configuration with transformer Analog source ADT1-1 1:1 VIN 50Ω 33pF VINB It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821 or TS4041-1.2 Vref leads to optimum performances when configured as shown on Figure 2 . Figure 2 : External reference setting 1kΩ 330pF 10nF 4.7uF VCCA VREFP VIN TSA1005 VINB VREFM TS821 TS4041 INCM 330pF 10nF 470nF Figure 4 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. Figure 4 : AC-coupled differential input external reference 50Ω VIN 10nF 100kΩ 33pF common mode DRIVING THE ANALOG INPUT TSA1005 I or Q ch. 50Ω INCM 100kΩ TSA1005 VINB 10nF Differential inputs The TSA1005-40 has been designed to obtain optimum performances when being differentially driven. An RF transformer is a good way to achieve such performances. Figure 3 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. It determines the DC component of the analog signal. As being an high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You 11/19 Figure 5 shows a DC-coupled configuration with forced VREFP and INCM to the 1V DC analog input while VREFM is connected to ground; we achieve a 2Vpp differential amplitude. Figure 5 : DC-coupled 2Vpp differential analog input analog AC+DC DC VREFP VIN TSA1005 VINB analog VREFM INCM DC VREFP-VREFM = 1 V 330pF 10nF 4.7uF TSA1005-40 Single-ended input configuration The single-ended input configuration of the TSA1005-40 requires particular biasing and driving. The structure being fully differential, care has to be taken in order to properly bias the inputs in single-ended mode. Figure 6 summarizes the link from the differential configuration to the single-ended one; a wrong configuration is also presented. - With differential driving, both inputs are centered around the INCM voltage. - The transition to single-ended configuration implies to connect the unused input (VINB for instance) to the DC component of the single input (VIN) and also to the input common mode in order to be well balanced. The mid-code is achieved at the crossing between VIN and VINB, therefore inputs are conveniently biased. - Unlikely other structures of converters in which the unused input can be grounded; in our case it will end with unbalanced inputs and saturation of the internal amplifiers leading to a non respect of the output codes. Figure 6 : Input dynamic range for the various configurations Differential configura tion Single-ended configuration: balanced inputs Single-end ed configuration: unbalanced input s +FS : code 1023 +FS + offset : code > 1023 +FS : code 1023 VIN - VINB VIN - VINB VIN - VINB VIN VINB VIN INCM 0 : code 511 INCM INCM VIN 0 : code 511 -FS : code 0 -FS + offset : code > 0 -FS : code 0 Ao + ac Ao + ac Ao + ac VIN VINB VINB INCM Ao Ao + ac VIN VINB INCM INCM Ao Wrong configuratio n ! Ao The applications requiring single-ended inputs can be configured like reported on Figure 7 for an AC-coupled input or on Figure 8 for a DC-coupled input. VIN Figure 7 : AC-coupled Single-ended input Signal source 10nF In the case of AC-coupled analog input, the analog inputs VIN and VINB are biased to the same voltage that is the common mode voltage of the circuit (INCM). The INCM and reference voltages may remain at their internal level but can also be fixed externally. In the case of DC-coupled analog input with 1V DC signal, the DC component of the analog input VIN 100kΩ 50Ω INCM 33pF TSA1005 100kΩ VINB set the common mode voltage. As an example figure 8, VREFP and INCM are set to the 1V DC 12/19 TSA1005-40 Figure 8 : DC-coupled 2Vpp analog input The figure 9 sums up the relevant data. Figure 9 : analog current consumption optimization depending on Rpol value 250 100 AC+DC VIN DC VREFM INCM 330pF 200 80 TSA1005 VINB VREFP-VREFM = 1 V 90 VREFP Icca (mA) Analog 70 150 60 ICCA 50 100 40 30 10nF 4.7uF Rpol (kOhms) analog input while VREFM is connected to ground; we achieve a 2Vpp differential amplitude. 50 20 10 RPOL 0 0 5 15 25 Dynamic characteristics, while not being as remarkable as for differential configuration, are still of very good quality. 35 45 55 Fs (MHz) APPLICATION Clock input Layout precautions The TSA1005-40 performance is very dependant on your clock input accuracy, in terms of aperture jitter; the use of low jitter crystal controlled oscillator is recommended. The duty cycle must be between 45% and 55%. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is recommended to always keep the circuit clocked, even at the lowest specified sampling frequency of 0.5Msps, before applying the supply voltages. Power consumption So as to optimize both performance and power consumption of the TSA1005-40 according the sampling frequency, a resistor is placed between IPOL and the analog Ground pins. Therefore, the total dissipation is adjustable from 35Msps up to 50Msps. The TSA1005-40 will combine highest performances and lowest consumption at 40Msps when Rpol is equal to 30kΩ. This value is nevertheless dependant on application and environment. At lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performances. 13/19 To use the ADC circuits in the best manner at high frequencies, some precautions have to be taken for power supplies: - First of all, the implementation of 4 separate proper supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital part is mandatory to prevent noise from coupling onto the input signal. The best compromise is to connect from one part AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the power supplies AVCC, DVCC and VCCBI must be separated from the VCCBE one. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. - Proper termination of all inputs and outputs must be incorporated with output termination resistors; then the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. - To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output TSA1005-40 capacitance, buffers or latches close to the output pins will relax this constraint. - Choose component sizes as small as possible (SMD). Digital Interface application Thanks to its wide external buffer power supply range, the TSA1005-40 is perfectly suitable to plug in to 2.5V low voltage DSPs or digital interfaces as well as to 3.3V ones. Medical Imaging application Driven by the demand of the applications requiring nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs. As a typical system diagram shows figure 10, a narrow input beam of acoustic energy is sent into a living body via the transducer and the energy reflected back is analyzed. Figure 10 : Medical imaging application HV TX amps The transducer is a piezoelectric ceramic such as zirconium titanate. The whole array can reach up to 512 channels. The TX beam former, amplified by the HV TX amps, delivers up to 100V amplitude excitation pulses with phase and amplitude shifts. The mux and T/R switch is a two way input signal transmitter/ output receiver. To compensate for skin and tissues attenuation effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the amplification of low voltage signals to the ADC input range. Differential output structure with low noise and very high linearity are mandatory factors. These applications need high speed, low power and high performance ADCs. 10-12 bit resolution is necessary to lower the quantification noise. As multiple channels are used, a dual converter is a must for room saving issues. The input signal is in the range of 2 to 20MHz (mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization. The next RX beam former and processing blocks enable the analysis of the outputs channels versus the input beam. TX beamformer Mux and T/R switches ADC RX beamformer TGC amplifie r Processing and disp lay 14/19 TSA1005-40 EVAL1005/BA evaluation board The EVAL1005/BA is a 4-layer board with high decoupling and grounding level. The schematic of the evaluation board is reported figure 14 and its top overlay view figure 13.The characterization of the board has been made with a fully ADC devoted test bench as shown on Figure 11. The analog input signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements have been made with: - SFSR=1dB for static parameters. - SFSR=-1dB for dynamic parameters. Figure 11 : Analog to Digital Converter characterization bench HP8644 Data Vin Sine Wave Generator ADC evaluation board Logic Analyzer PC Clk Clk HP8133 Pulse Generator HP8644 Sine Wave Generator Operating conditions of the evaluation board: Find below the connections to the board for the power supplies and other pins: board notation board notation connection internal external voltage (V) voltage (V) AV AVCC 2.5 AG AGND 0 RPI REFPI RMI REFMI CMI INCMI 0.46 0.2 to 1 RPQ REFPQ 0.89 0.6 to 1.4 RMQ REFMQ CMQ INCMQ DV DVCC 2.5 DG DGND 0 15/19 0.89 0.6 to 1.4 0 to 0.4 0 to 0.4 0.46 0.2 to 1 connection internal external voltage (V) voltage (V) GB1 GNDBI 0 VB1 VCCBI 2.5 GB2 GNDBE 0 VB2 VCCBE 2.5/3.3 GB3 GNDB3 0 VB3 VCCB3 2.5 Care should be taken for the evaluation board considering the fact that the outputs of the converter are 2.5V/3.3V (VB2) tolerant whereas the 74LCX573 external buffers are operating up to 2.5V. The ADC outputs on the connector J6 are D11 (MSB) to D2 (LSB). TSA1005-40 Single and Differential Inputs: The ADC board components are mounted to test the TSA1005-40 with single analog input; the ADT1-1WT transformer enables the differential drive into the converter; in this configuration, the resistors RSI6, RSI7, RSI8 for I channel (respectively RSQ6, RSQ7, RSQ8 for Q one) are connected as short circuits whereas RSI5, RSI9 (respectively RSQ5, RSQ9) are open circuits. The other way is to test it via JI1 and JI1B differential inputs. So, the resistances RSI5, RSI9 for I channel (respectively RSQ5, RSQ9 for Q one) are connected as short circuits whereas RSI6, RSI7, RSI8 (respectively RSQ6, RSQ7, RSQ8 for Q one) are open circuits. With the strap connected: - to the upper connectors, the I channel at the output is selected. - horizontally, the Q channel at the output is selected. - to the lower connectors, both channels are selected, relative to the clock edge. Figure 12 : mode select SELECT I channel SELECT Grounding consideration So as to better reject noise on the board, connect on the bottom overlay AG (AGND), DG(DGND), GB1(GNDBI) together from one part, and GB2(GNDBE) with GB3(GNDB3) from the other part. Q channel I/Q channels CLK DGND DVCC schematic board Mode select So as to evaluate a single channel or the dual ones, you have to connect on the board the relevant position for the SELECT pin. Consumption adjustment Before any characterization, care should be taken to adjust the Rpol (Raj1) and therefore Ipol value in function of your sampling frequency. Figure 13 : Printed circuit of evaluation board. 16/19 1 JQ1B InQB JI1B InIB 0 RQ19 50 RQ1 50 3 3 RSQ61 0 RI19 50 RI1 50 RSI6 1 0 AVCC 0 NC RSQ9 4RSQ8 T2-AT1-1WT 0 0 NC RSQ7 TQ2 6 0 2 RSQ5 ANALOGIC VCC GND JA 0 NC RSI9 4 RSI8 T2-AT1-1WT0 2 RSI7 + 0NM 0NM 0 NC TI2 6 RSI5 R22 R21 C41 C42 47µF10µF 0NM R23 CI9 C4 470nF 10nF JQ2 VREFQ 330pF CQ8 NM 33pF CQ10 CQ9 CQ6 CQ1 330pF C2 NM 33pF 470nF 10nF C3 CI6 330pF CI8 CI1 470nF 10nF CI10 0NM R24 CI31 1K R2 330pF CI30 470nF 10nF 330pF CI12 C52 10nF C14 330pF C51 330pF C53 470nF AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND ADC DUAL10B C36 47µF C23 10µF C22 470nF C21 10nF C20 330pF AVCC DVCC C32 47µF C31 10µF C13 470nF C11 10nF C10 330pF J27 2 1 DIGITAL JD CON2 C5 CLK 100nF J4 50 R3 DVCC SW1 CD3 330pF CD2 10nF 330pF 470nF 10nF DVcc 36 35 34 33 32 31 30 29 28 27 26 25 10µF R5 50 J25 CKDATA C35 VCCB2 47µF C19 470nF C18 10nF C17 330pF C29 Ra 330pF 10nF C25 470nF C27 VCCB2 C28 2 1 CON2 VCCB2 J26 D0(LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9(MSB) VCCBE GNDBE CD1 470nF 1 2 3 4 5 6 7 8 9 10 11 12 330pF CI11 47µF C43 10µF VCCB1 C44 C15 10nF AVCC IN S2 Vcc D GNDS1 STG719 CQ13 CQ12 CQ11 470nF 10nF CI13 REFP REFM INCM CQ32 CQ31 CQ30 Raj1 47K 470nF 10nF CI32 47K R11 U1 R12 47K S5 SW-SPST VCCB1 VCCB2 S4 SW-SPST C16 470nF + JI2 VREFI + CC ND + REFP REFM INCM 48 47 46 45 44 43 42 41 40 39 38 37 REFPI REFMI INCMI AVCC AVCC OEB VCCBI VCCBI GNDBE VCCBE NC NC 17/19 + REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI J17 BUFPOW 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 470nF 10nF 330pF C39 C26 47µF C37 C34 C33 C40 C38 330pF 10nF 470nF 74LCX573 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 74LCX573 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE VCCB2 GndB1 VccB1 GndB2 VccB2 GndB3 VccB3 VCCB1 VCCB3 + 13 14 15 16 17 18 19 20 21 22 23 24 NM: non soudé 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 Normal mode Test mode Switch S5 Open Short VCCB3 OEB Mode Normal mode High Impedance output mode Switch S4 Open Short analoginput with transformer (default) single input differential input CLK D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RS5 RS6 RS7 RS8 RS9 C C C C C C C J6 CLK GND D11 GND (MSB) D10 GND D9 GND D8 GND D7 GND D6 GND D5 GND D4 GND D3 GND D2 GND (LSB) D1 GND D0 GND TSA1005-40 Figure 14 : TSA1005-40 Evaluation board schematic + TSA1005-40 Figure 15 : Printed circuit board - List of components Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC R24 0NC 0NC R23 R21 0NC R22 0NC 1K R2 R12 47K 47K R11 Raj1 200K C23 C41 C29 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 trimmer CQ11 330pF 10µF 1210 CI8 330pF 10µF 1210 C14 330pF 10µF 1210 CI30 330pF Footprint Name 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 C26 C20 C33 C25 CI1 CQ1 C34 C42 C35 C44 C36 C32 C37 CQ10 C28 CI10 CQ32 CQ13 CI32 C13 C53 C16 C3 C22 CI13 C38 CD1 C19 Part Type 330pF 330pF 330pF 330pF 33pF 33pF 47µF 47µF 47µF 47µF 47µF 47µF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 805 connector 805 805 NC: non soldered 805 18/19 TSA1005 PACKAGE MECHANICAL DATA 48 PINS - PLASTIC PACKAGE A A2 e 48 A1 37 0,10 mm .004 inch 36 12 25 SEATING PLANE E c 24 L D3 D1 D L1 13 E1 E3 B 1 K 0,25 mm .010 inch GAGE PLANE Millimeters Inches Dim. Min. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.05 1.35 0.17 0.09 0.45 Typ. 1.40 0.22 9.00 7.00 5.50 0.50 9.00 7.00 5.50 0.60 1.00 Max. Min. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.75 0.018 Typ. 0.055 0.009 0.354 0.276 0.216 0.0197 0.354 0.276 0.216 0.024 0.039 Max. 0.063 0.006 0.057 0.011 0.008 0.030 0° (min.), 7° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infring ement of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change witho ut notice. This publ ication supersedes and replaces all information previously supplied. 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