UC2842/3/4/5 UC3842/3/4/5 CURRENT MODE PWM CONTROLLER . .. .. . .. . .. OPTIMIZED FOR OFF-LINE AND DC TO DC CONVERTERS LOW START-UP CURRENT (< 1 mA) AUTOMATIC FEED FORWARD COMPENSATION PULSE-BY-PULSE CURRENT LIMITING ENHANCED LOAD RESPONSE CHARACTERISTICS UNDER-VOLTAGE LOCKOUT WITH HYSTERESIS DOUBLE PULSE SUPPRESSION HIGH CURRENT TOTEM POLE OUTPUT INTERNALLY TRIMMED BANDGAP REFERENCE 500 KHz OPERATION LOW RO ERROR AMP DESCRIPTION TheUC3842/3/4/5family of controlICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal externalparts count.Internallyimplementedcircuits include undervoltagelockout featuring start-up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, Minidip SO14 logic to insure latched operation, a PWM comparatorwhich also providescurrentlimit control,and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in theoff-state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842 and UC3844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843 and UC3845 are 8.5 V and 7.9 V. The UC3842 and UC3843 can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844 and UC3845 by the additionof an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGRAM (toggle flip flop used only in U3844 and UC3845) October 1998 1/11 UC2842/3/4/5-UC3842/3/4/5 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vi Supply Voltage (low impedance source) Vi Supply Voltage (Ii < 30mA) IO Output Current EO Output Energy (capacitive load) Value Unit 30 V Self Limiting ±1 5 Analog Inputs (pins 2, 3) – 0.3 to 6.3 µJ V 10 mA Error Amplifier Output Sink Current Ptot Power Dissipation at Tamb ≤ 50 °C (minidip, DIP-14) Ptot Power Dissipation at Tamb ≤ 25 °C (SO14) Tstg Storage Temperature Range TL Lead Temperature (soldering 10s) A 1 W 725 mW – 65 to 150 °C 300 °C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. PIN CONNECTIONS (top views) SO14 Minidip ORDERING NUMBERS T ype Min idip SO14 UC2842 UC3843 UC2844 UC2845 UC2842N UC2843N UC2844N UC2845N UC2842D UC2843D UC2844D UC2845D UC3842 UC3843 UC3844 UC3845 UC3842N UC3843N UC3844N UC3845N UC3842D UC3843D UC3844D UC3845D THERMAL DATA Symbol R th j-amb 2/11 Description Thermal Resistance Junction-ambient. max. Min id ip SO14 Unit 100 165 °C UC2842/3/4/5-UC3842/3/4/5 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC2824X; 0 < Tamb < 70°C for UC384X; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbo l Parameter T est Cond ition s UC284X UC384X Uni t Min. T yp. Max. Min. Typ . Max. REFERENCE SECTION VREF 4.95 5.00 5.05 4.90 5.00 5.10 V Output Voltage Tj = 25°C Io = 1mA ∆V REF Line Regulation 12V ≤ Vi ≤ 25V 6 20 6 20 mV ∆V REF Load Regulation 1 ≤ Io ≤ 20mA 6 25 6 25 mV ∆VREF/∆T Temperature Stability (Note 2) 0.2 0.4 0.2 0.4 mV/°C Total Output Variant Line, Load, Temperature (2) 5.18 V Output Noise Voltage 10Hz ≤ f ≤ 10KHz Tj = 25°C (2) 50 Long Term Stability Tamb = 125°C, 1000Hrs (2) 5 eN ISC Output Short Circuit 4.9 -30 5.1 4.82 µV 50 25 -100 -180 5 -30 25 -100 -180 mV mA OSCILLATOR SECTION fs Initial Accuracy Tj = 25°C (6) 47 52 57 1 47 52 57 0.2 1 KHz Voltage Stability 12 ≤ Vi ≤ 25V 0.2 Temperature Stability TMIN ≤ Tamb ≤ TMAX (2) 5 5 % V4 Amplitude VPIN4 Peak to Peak 1.7 1.7 V V2 Input Voltage Ib Input Bias Current AVOL 2 ≤ Vo ≤ 4V 65 90 65 90 dB B Unity Gain Bandwidth (2) 0.7 1 0.7 1 MHz SVR Supply Voltage Rejection 12V ≤ Vi ≤ 25V 60 70 60 70 dB Io Output Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 6 2 6 V Io Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -0.8 -0.5 -0.8 mA VOUT High VPIN2 = 2.3V; RL = 15KΩ to Ground 5 6 5 6 V VOUT Low VPIN2 = 2.7V; RL = 15KΩ to Pin 8 % ERROR AMP SECTION VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 -0.3 -1 0.7 1.1 -0.3 -2 V µA 0.7 1.1 V CURRENT SENSE SECTION GV Gain (3 & 4) 2.85 3 3.15 2.8 3 3.2 V/V V3 Maximum Input Signal VPIN1 = 5V (3) 0.9 1 1.1 0.9 1 1.1 V SVR Supply Voltage Rejection 12 ≤ Vi ≤ 25V (3) Ib Input Bias Current -2 -10 -2 -10 µA Delay to Output 150 300 150 300 ns ISINK = 20mA 0.1 0.4 0.1 0.4 V ISINK = 200mA 1.5 2.2 1.5 2.2 V 70 70 dB OUTPUT SECTION IOL IOH Output Low Level Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V ISOURCE = 200mA 12 13.5 12 13.5 V tr Rise Time Tj = 25°C CL = 1nF (2) 50 150 50 150 ns tf Fall Time Tj = 25°C CL = 1nF (2) 50 150 50 150 ns 3/11 UC2842/3/4/5-UC3842/3/4/5 ELECTRICAL CHARACTERISTICS (continued) Symbo l Parameter T est Cond ition s UC284X UC384X Min. T yp. Max. Min. T yp. Max. Unit UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on X842/4 15 16 17 14.5 16 17.5 V X843/5 7.8 8.4 X842/4 9 10 9.0 7.8 11 8.5 8.4 9 V 10 11.5 V X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V X842/3 93 97 100 93 97 100 % X844/5 46 48 50 47 48 50 % 0 % PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0 TOTAL STANDBY CURRENT Ist Start-up Current Ii Operating Supply Current V iz Zener Voltage 0.5 1 0.5 1 mA VPIN2 = VPIN3 = 0V 11 20 11 20 mA Ii = 25mA 34 N otes : 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : ∆ VPIN1 A= ; 0 ≤ VPIN3 ≤ 0.8 V ∆ VPIN3 5. Adjust V i above the start threshold before setting at 15 V. 6. Output frequency equals oscillator frequency for the UC3842 and UC3843. Output frequency is one half oscillator frequency for the UC3844 and UC3845. 4/11 34 V UC2842/3/4/5-UC3842/3/4/5 Figure 1 : Error Amp Configuration. Error amp can source or sink up to 0.5mA Figure 2 : Under Voltage Lockout. During Under-Voltage Lockout, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to groundwith a bleederresistor to preventactivating the power switch with extraneous leakage currents. Figure 3 : Current Sense Circuit . Peak current (is) is determined by the formula 1.0 V IS max ≈ RS A small RC filter may be required to suppress switch transients. 5/11 UC2842/3/4/5-UC3842/3/4/5 Figure 4. Figure 5 : Deadtime vs. CT (RT > 5KΩ). for RT > 5KΩ f = 1.72 RTCT Figure 6 : Timing Resistance vs. Frequency. Figure 8 : Error Amplifier Open-loop Frequency Response. 6/11 Figure 7 : Output Saturation Characteristics. UC2842/3/4/5-UC3842/3/4/5 Figure 9 : Open Loop Test Circuit. High peak currents associatedwith capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ potentiometerareused to sampletheoscillator waveform and apply an adjustable ramp to pin 3. Figure 10 : Shutdown Techniques. Shutdown of the UC2842 can be accomplished by two methods; either raise pin 3 above1V or pull pin 1 below a voltage two diode drops above ground. Either method cause the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shut- down conditionat pins 1 and/or3 is removed. In one example, an externally latched shutdown may be accomplishedby addingan SCR which will be reset by cyclingVi belowthe lowerUVLOthreshold.At this point the referenceturns off, allowing the SCR to reset. 7/11 UC2842/3/4/5-UC3842/3/4/5 Figure 11 : Off-line Flyback Regulator. Power Supply Specifications 1. Input Voltage : 95 VAC to 130 VAC (50 Hz/60 Hz) 2. Line Isolation : 3750 V 3. Switching Frequency : 40 KHz 4. Efficiency @ Full Load : 70 % 5. Output Voltage : A. + 5 V, ± 5 % : 1 A to 4 A load Ripple voltage : 50 mV P-P Max. B. + 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max. C. – 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage : 100 mV P-P Max. Figure 12 : Slope Compensation. A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50 %. 8/11 Note that capacitor, C, forms a filter with R2 to supress the leading edge switch spikes. UC2842/3/4/5-UC3842/3/4/5 mm DIM. MIN.. TYP. A a1 inch MAX.. MIN.. TYP.. MAX.. 1.75 0.1 0.25 a2 0.069 0.004 0.009 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.020 45° (typ.) D (1) 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.68 0.027 8° (max.) SO14 (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 9/11 UC2842/3/4/5-UC3842/3/4/5 mm DIM. MIN. A TYP. inch MAX. MIN. 3.3 TYP. MAX. 0.130 a1 0.7 B 1.39 1.65 0.055 0.065 B1 0.91 1.04 0.036 0.041 b b1 0.028 0.5 0.38 0.020 0.5 D 0.015 0.020 9.8 0.386 E 8.8 0.346 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 7.1 0.280 I 4.8 0.189 L Z 10/11 3.3 0.44 OUTLINE AND MECHANICAL DATA 0.130 1.6 0.017 Minidip 0.300” 0.063 UC2842/3/4/5-UC3842/3/4/5 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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