STMICROELECTRONICS VNP7N04FI

VND7N04/VND7N04-1
VNP7N04FI/K7N04FM

”OMNIFET”:
FULLY AUTOPROTECTED POWER MOSFET
T YPE
VND7N04
VND7N04-1
VNP7N04F I
VNK7N04F M
V c lamp
42
42
42
42
V
V
V
V
R DS(on)
0.14
0.14
0.14
0.14
Ω
Ω
Ω
Ω
I l im
7
7
7
7
A
A
A
A
3
■
■
■
■
■
■
■
■
■
LINEAR CURRENT LIMITATION
THERMAL SHUT DOWN
SHORT CIRCUIT PROTECTION
INTEGRATED CLAMP
LOW CURRENT DRAWN FROM INPUT PIN
DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
ESD PROTECTION
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VND7N04, VND7N04-1, VNP7N04FI and
VNK7N04FM are monolithic devices made using
STMicroeletronics VIPower M0 Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications. Built-in
thermal shut-down, linear current limitation and
overvoltage clamp protect the chip in harsh
BLOCK DIAGRAM
February 2000
3
2
1
1
IPAK
TO-251
DPAK
TO-252
3
1
ISOWATT220
2
SOT82-FM
enviroments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
1/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Value
DPAK
IP AK
V DS
Drain-source Voltage (V in = 0)
V in
Unit
ISOW AT T220
SOT -82FM
Internally Clamped
V
Input Voltage
18
V
ID
Drain Current
Internally Limited
A
IR
Reverse DC O utput Current
-7
A
2000
V
V esd
Electrostatic Discharge (C= 100 pF,
R=1.5 KΩ)
P tot
Total Dissipation at T c = 25 C
Tj
Tc
T stg
o
60
Operating Junction T emperature
Case O perating T emperature
Storage Temperature
24
9
W
Internally Limited
o
C
Internally Limited
o
C
-55 to 150
o
C
THERMAL DATA
DPAK/IPAK
ISOW AT T220
SO T82-FM
R t hj-ca se Thermal Resistance Junction-case
Max
3.75
5.2
14
o
C/W
R t hj-a mb Thermal Resistance Junction-ambient
Max
100
62.5
100
o
C/W
ELECTRICAL CHARACTERISTICS (-40 < Tj < 125 oC unless otherwise specified)
OFF
Symb ol
Parameter
Test Cond ition s
V CLAMP
Drain-source Clamp
Voltage
I D = 200 mA
V CL TH
Drain-source Clamp
Threshold Voltage
I D = 2 mA
V I NCL
Input-Source Reverse
Clamp Voltage
I in = -1 mA
I DSS
Zero Input Voltage
Drain Current (V in = 0)
V DS = 13 V
V DS = 25 V
V in = 0
V in = 0
I I SS
Supply Current from
Input Pin
V DS = 0 V
Vin = 10 V
V in = 0
V in = 0
Min.
Typ .
Max.
Un it
32
42
52
V
31
V
-1.1
-0.25
V
75
200
µA
µA
250
550
µA
Typ .
Max.
Un it
3
V
A
A
0.14
0.28
Ω
Ω
A
A
0.28
0.56
Ω
Ω
ON (∗)
Symb ol
Parameter
Test Cond ition s
Min.
ID + Ii n = 1 mA
0.8
V IN(th)
Input Threshold
Voltage
V DS = Vin
R DS( on)
Static Drain-source On
Resistance
V i n = 10 V I D = 3.5
ID = 3.5
Vi n = 5 V
-40 < T j < 25 oC
V i n = 10 V I D = 3.5
ID = 3.5
Vi n = 5 V
o
T j = 125 C
2/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
ELECTRICAL CHARACTERISTICS (continued)
DYNAMIC
Symb ol
g fs (∗)
C oss
Parameter
Test Cond ition s
Forward
Transconductance
V DS = 13 V
I D = 3.5 A
Output Capacitance
V DS = 13 V
f = 1 MHz
Min.
Typ .
2
5
Vin = 0
Max.
Un it
S
250
500
pF
Typ .
Max.
Un it
SWITCHING (**)
Symb ol
Parameter
Test Cond ition s
Min.
t d(on)
tr
t d(of f)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall T ime
V DD = 15 V
V gen = 10 V
(see figure 3)
Id = 3.5 A
R gen = 10 Ω
50
60
130
50
150
180
300
200
ns
ns
ns
ns
t d(on)
tr
t d(of f)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall T ime
V DD = 15 V
V gen = 10 V
(see figure 3)
Id = 3.5 A
R gen = 1000 Ω
140
0.4
2.5
1
500
1.1
7
4
ns
µs
µs
µs
Turn-on Current Slope
V DD = 15 V
V i n = 10 V
Total Input Charge
V DD = 12 V
(di/dt) on
Qi
ID = 3.5 A
R gen = 10 Ω
ID = 3.5 A
V i n = 10 V
50
A/µs
18
nC
SOURCE DRAIN DIODE
Symb ol
Parameter
Test Cond ition s
V SD (∗)
Forward O n Voltage
I SD = 3.5 A
t r r (∗∗)
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 3.5 A
di/dt = 100 A/µs
Tj = 25 oC
V DD = 30 V
(see test circuit, figure 5)
Q r r (∗∗)
I RRM (∗∗)
Min.
Typ .
V in = 0
Max.
Un it
1.7
V
40
ns
0.2
µC
3.6
A
PROTECTION
Symb ol
I lim
Parameter
Test Cond ition s
Min.
Typ .
Max.
Un it
VDS = 13 V
V DS = 13 V
4
4
7
7
11
11
A
A
13
15
20
25
µs
µs
Drain Current Limit
V i n = 10 V
Vi n = 5 V
t dl im (∗∗)
Step Response
Current Limit
V i n = 10 V
Vi n = 5 V
T jsh (∗∗)
Overtemperature
Shutdown
150
o
C
T j rs (∗∗)
Overtemperature Reset
135
o
C
I gf (∗∗)
Fault Sink Current
V i n = 10 V
Vi n = 5 V
E as (∗∗)
Single Pulse
Avalanche Energy
starting T j = 25 C
V DD = 20 V
V i n = 10 V R gen = 1 KΩ L = 30 mH
50
20
VDS = 13 V
V DS = 13 V
o
0.4
mA
mA
J
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(∗∗) Parameters guaranteed by design/characterization
3/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
PROTECTION FEATURES
During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (Iiss) flows into the Input pin in order to
supply the internal circuitry.
The device integrates:
- OVERVOLTAGE
CLAMP
PROTECTION:
internally set at 42V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current Id to Ilim whatever the Input
pin voltage. When the current limiter is active,
the device operates in the linear region, so
power dissipation may exceed the capability of
the heatsink. Both case and junction
temperatures increase, and if this phase lasts
long enough, junction temperature may reach
the overtemperature threshold Tjsh.
4/14
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing
the chip temperature and are not dependent on
the input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast, accurate detection of the junction
temperature. Overtemperature cutout occurs at
minimum 150oC. The device is automatically
restarted when the chip temperature falls
below 135oC.
- STATUS FEEDBACK: In the case of an
overtemperature fault condition, a Status
Feedback is provided through the Input pin.
The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit (with a small increase in RDS(on)).
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
Thermal Impedance For DPAK / IPAK
Thermal Impedance For ISOWATT220
Derating Curve
Output Characteristics
Transconductance
Static Drain-Source On Resistance vs Input
Voltage
5/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
Static Drain-Source On Resistance
Static Drain-Source On Resistance
Input Charge vs Input Voltage
Capacitance Variations
Normalized Input Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
6/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Turn-off Drain-Source Voltage Slope
Switching Time Resistive Load
7/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
Switching Time Resistive Load
Switching Time Resistive Load
Current Limit vs Junction Temperature
Step Response Current Limit
Source Drain Diode Forward Characteristics
8/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
Fig. 1: Unclamped Inductive Load Test Circuits
Fig. 2: Unclamped Inductive Waveforms
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Input Charge Test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 6: Waveforms
9/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.20
2.40
0.087
0.094
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
C
0.45
0.60
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
0.398
L2
0.8
0.031
L4
0.60
1.00
0.024
0.039
V2
0o
8o
0o
0o
P032P_B
10/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
TO-251 (IPAK) MECHANICAL DATA
DIM.
mm
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.20
2.40
0.087
0.094
A1
0.90
1.10
0.035
0.043
A3
0.70
1.30
0.028
0.051
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
B3
0.85
B5
B6
C
0.033
0.30
0.012
0.95
0.45
0.60
0.037
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.237
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
15.90
16.30
0.626
0.642
L
9.00
9.40
0.354
0.370
L1
0.80
1.20
0.031
L2
V1
0.80
10
o
1.00
0.047
0.031
10
0.039
o
P032N_E
11/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
ISOWATT220 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.4
0.7
0.015
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
28.6
30.6
1.126
1.204
L4
9.8
10.6
0.385
0.417
L6
15.9
16.4
0.626
0.645
L7
9
9.3
0.354
0.366
Ø
3
3.2
0.118
0.126
B
D
A
E
L3
L3
L6
F
F1
L7
F2
H
G
G1
¯
1 2 3
L2
12/14
L4
P011G
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
SOT-82FM MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.85
3.05
1.122
1.200
A1
1.47
1.67
0.578
0.657
b
0.40
0.60
0.157
0.236
b1
1.4
1.6
0.551
0.630
b2
1.3
1.5
0.511
0.590
c
0.45
0.6
0.177
0.236
D
10.5
10.9
4.133
4.291
e
2.2
2.8
0.866
1.102
E
7.45
7.75
2.933
3.051
L
15.5
15.9
6.102
6.260
L1
1.95
2.35
0.767
0.925
P032R
13/14
VND7N04/VND7N04-1/VNP7N04FI/VNK7N04FM
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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