STMICROELECTRONICS VNQ810M13TR

VNQ810M
®
M
QUAD CHANNEL HIGH SIDE DRIVER
TYPE
VNQ810M
RDS(on)
150 mΩ (*)
IOUT
0.6 A (*)
VCC
36 V
(*) Per each channel
CMOS COMPATIBLE INPUTS
OPEN DRAIN STATUS OUTPUTS
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■
■
■
REVERSE BATTERY PROTECTION (**)
DESCRIPTION
The VNQ810M is a quad HSD formed by
assembling two VND810M chips in the same SO28 package. The VND810M is a monolithic device
made by using STMicroelectronics VIPower M0-3
Technology, intended for driving any kind of load
with one side connected to ground.
Active VCC pin voltage clamp protects the device
SO-28 (DOUBLE ISLAND)
ORDER CODES
PACKAGE
SO-28
TUBE
VNQ810M
T&R
VNQ810M13TR
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart protects the device against overload. The
current limitation threshold is aimed at detecting
the 21W/12V standard bulb as an overload fault.
The device detects open load condition both in on
and off state . Output shorted to VCC is detected
in the off state. Device automatically turns off in
case of ground pin disconnection.
ABSOLUTE MAXIMUM RATING
Symbol
VCC
- VCC
- Ignd
IOUT
- IOUT
IIN
ISTAT
VESD
EMAX
Ptot
Tj
Tstg
Parameter
DC Supply Voltage
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
Reverse DC Output Current
DC Input Current
DC Status Current
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
Value
41
-0.3
-200
Internally Limited
-6
+/- 10
+/- 10
Unit
V
V
mA
A
A
mA
mA
- INPUT
4000
V
- STATUS
4000
V
- OUTPUT
5000
V
- VCC
Maximum Switching Energy
5000
V
174
mJ
6.25
Internally Limited
-55 to 150
W
°C
°C
(L=310mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=0.9A)
Power dissipation (per island) at Tlead=25°C
Junction Operating Temperature
Storage Temperature
(**) See application schematic at page 9
July 2004
Rev. 1
1/21
VNQ810M
BLOCK DIAGRAM
VCC1,2
Vcc
OVERVOLTAGE
CLAMP
UNDERVOLTAGE
GND1,2
CLAMP 1
OUTPUT1
INPUT1
DRIVER 1
CLAMP 2
STATUS1
CURRENT LIMITER 1
LOGIC
DRIVER 2
OUTPUT2
OVERTEMP. 1
OPENLOAD ON 1
CURRENT LIMITER 2
INPUT2
OPENLOAD OFF 1
OPENLOAD ON 2
STATUS2
OPENLOAD OFF 2
OVERTEMP. 2
VCC3,4
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND3,4
CLAMP 3
OUTPUT3
INPUT3
DRIVER 3
CLAMP 4
STATUS3
CURRENT LIMITER 3
LOGIC
DRIVER 4
OUTPUT4
OVERTEMP. 3
OPENLOAD ON 3
CURRENT LIMITER 4
INPUT4
OPENLOAD OFF 3
OPENLOAD ON 4
STATUS4
OPENLOAD OFF 4
OVERTEMP. 4
2/21
VNQ810M
CURRENT AND VOLTAGE CONVENTIONS
IS3,4
IS1,2
VCC1,2
VCC3,4
VCC3,4
VF1 (*)
VCC1,2
IIN1
ISTAT1
VIN1
IIN2
VSTAT1
ISTAT2
VIN2
IIN3
VSTAT2
ISTAT3
VIN3
VSTAT3
IIN4
VIN4 ISTAT4
VSTAT4
INPUT1
IOUT1
STATUS1
OUTPUT1
VOUT1
IOUT2
INPUT2
OUTPUT2
STATUS2
VOUT2
IOUT3
INPUT3
OUTPUT3
STATUS3
IOUT4
INPUT4
OUTPUT4
STATUS4
GND3,4
VOUT3
VOUT4
GND1,2
IGND3,4
IGND1,2
(*) VFn = VCCn - VOUTn during reverse battery condition
CONFIGURATION DIAGRAM (TOP VIEW) & SUGGESTED CONNECTIONS FOR UNUSED AND N.C.
PINS
VCC1,2
1
28
VCC1,2
GND 1,2
OUTPUT1
INPUT1
OUTPUT1
STATUS1
OUTPUT1
STATUS2
OUTPUT2
INPUT2
OUTPUT2
VCC1,2
OUTPUT2
VCC3,4
OUTPUT3
GND 3,4
OUTPUT3
INPUT3
OUTPUT3
STATUS3
OUTPUT4
STATUS4
OUTPUT4
INPUT4
VCC3,4
Connection / Pin
Floating
To Ground
OUTPUT4
14
Status
X
15
N.C.
X
X
VCC3,4
Output
X
Input
X
Through 10KΩ resistor
3/21
VNQ810M
THERMAL DATA (Per island)
Symbol
Parameter
Rthj-lead
Thermal Resistance Junction-lead per chip
Rthj-amb
Thermal Resistance Junction-ambient (one chip ON)
Rthj-amb
Thermal Resistance Junction-ambient (two chips ON)
Value
Unit
20
°C/W
60 (1)
44 (2)
°C/W
(1)
31 (2)
°C/W
46
(1)
When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all V CC pins.
Horizontal mounting and no artificial air flow.
(2)
When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35µm thick) connected to all V CC pins.
Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)
POWER OUTPUTS (Per each channel)
Symbol
VCC (**)
VUSD (**)
VOV (**)
RON
Parameter
Operating Supply Voltage
Undervoltage Shut-down
Overvoltage Shut-down
On State Resistance
Test Conditions
Min
5.5
3
36
IOUT=0.5A; Tj=25°C
150
Unit
V
V
V
mΩ
IOUT=0.5A; VCC> 8V
12
300
40
mΩ
µA
12
25
µA
5
7
50
0
5
3
mA
µA
µA
µA
µA
Typ
30
Max
Unit
µs
Off State; VCC=13V; VIN=VOUT=0V
IS (**)
Supply Current
Off State; VCC=13V; VIN=VOUT=0V;
Tj =25°C
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1)
IL(off2)
IL(off3)
IL(off4)
Off
Off
Off
Off
State
State
State
State
Output Current
Output Current
Output Current
Output Current
VIN=VOUT=0V
VIN=0V; VOUT =3.5V
VIN=VOUT=0V; VCC=13V; Tj =125°C
VIN=VOUT=0V; VCC=13V; Tj =25°C
Typ
13
4
0
-75
Max
36
5.5
SWITCHING (Per each Channel) (VCC=13V)
Symbol
td(on)
Parameter
Turn-on Delay Time
td(off)
Turn-off Delay Time
Test Conditions
RL=26Ω from VIN rising edge to VOUT =1.3V
RL=26Ω from VIN falling edge to
VOUT =11.7V
dVOUT/dt(on) Turn-on Voltage Slope
RL=26Ω from VOUT =1.3V to VOUT=10.4V
dVOUT/dt(off) Turn-off Voltage Slope
RL=26Ω from VOUT =11.7V to VOUT=1.3V
Min
µs
30
See
relative
diagram
See
relative
diagram
V/µs
V/µs
LOGIC INPUT (Per each channel)
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
(**) Per island
4/21
1
Parameter
Input Low Level
Low Level Input Current
Input High Level
High Level Input Current
Input Hysteresis Voltage
Input Clamp Voltage
Test Conditions
VIN = 1.25V
Min
Typ
1
3.25
VIN = 3.25V
IIN = 1mA
IIN = -1mA
Max
1.25
10
0.5
6
6.8
-0.7
8
Unit
V
µA
V
µA
V
V
V
VNQ810M
ELECTRICAL CHARACTERISTICS (continued)
VCC - OUTPUT DIODE
Symbol
VF
Parameter
Forward on Voltage
Test Conditions
-IOUT=0.53A; Tj=150°C
Min
Typ
Max
0.6
Unit
V
Test Conditions
ISTAT = 1.6 mA
Normal Operation; VSTAT= 5V
Min
Typ
Max
0.5
10
Unit
V
µA
100
pF
8
V
STATUS PIN (Per each channel)
Symbol
VSTAT
ILSTAT
CSTAT
Parameter
Status Low Output Voltage
Status Leakage Current
Status Pin Input
Capacitance
VSCL
Status Clamp Voltage
Normal Operation; VSTAT= 5V
6
ISTAT =1mA
ISTAT =-1mA
6.8
-0.7
V
PROTECTIONS (Per each channel) (see note 1)
Symbol
TTSD
TR
Thyst
tSDL
Parameter
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
Status Delay in Overload
Conditions
Ilim
Current limitation
Vdemag
Test Conditions
Min
150
135
7
Typ
175
0.9
5.5V < VCC < 36V
Turn-off Output Clamp
Voltage
IOUT =0.5A
Unit
°C
°C
°C
20
µs
1.4
A
1.4
A
15
Tj>TTSD
0.7
Max
200
VCC-41 VCC-48 VCC-55
V
Note 1: To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used
together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.
OPENLOAD DETECTION (per each channel)
Symbol
IOL
tDOL(on)
VOL
tDOL(off)
Parameter
Openload ON State
Test Conditions
VIN=5V
Detection Threshold
Openload ON State
Detection Delay
Openload OFF State
Voltage Detection
Threshold
Openload Detection Delay
at Turn Off
Min
Typ
Max
Unit
20
40
80
mA
200
µs
3.5
V
1000
µs
IOUT=0A
VIN=0V
1.5
OPENLOAD STATUS TIMING (with external pull-up)
VOUT > VOL
2.5
OVERTEMP STATUS TIMING
IOUT < IOL
Tj > TTSD
VINn
VINn
VSTATn
VSTATn
tSDL
tDOL(off)
tSDL
tDOL(on)
5/21
2
VNQ810M
Switching time Waveforms
vOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VINn
td(on)
td(off)
t
TRUTH TABLE
CONDITIONS
Normal Operation
Current Limitation
Overtemperature
Undervoltage
Overvoltage
Output Voltage > VOL
Output Current < IOL
6/21
INPUT
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
OUTPUT
L
H
L
X
X
L
L
L
L
L
L
H
H
L
H
STATUS
H
H
H
(Tj < TTSD) H
(Tj > TTSD) L
H
L
X
X
H
H
L
H
H
L
VNQ810M
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
ISO T/R 7637/1
Test Pulse
I
1
2
3a
3b
4
5
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
I
C
C
C
C
C
C
II
TEST LEVELS
III
IV
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
7/21
VNQ810M
Figure 1: Waveforms
NORMAL OPERATION
INPUTn
OUTPUT VOLTAGEn
STATUSn
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUTn
OUTPUT VOLTAGEn
STATUSn
undefined
OVERVOLTAGE
VCC<VOV
VCC
VCC>VOL
INPUTn
OUTPUT VOLTAGEn
STATUSn
OPEN LOAD with external pull-up
INPUTn
VOUT>VOL
OUTPUT VOLTAGEn
VOL
STATUSn
OPEN LOAD without external pull-up
INPUTn
OUTPUT VOLTAGEn
STATUSn
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
OUTPUT CURRENTn
STATUSn
8/21
1
VNQ810M
APPLICATION SCHEMATIC
+5V +5V
+5V
VCC1,2
VCC3,4
Rprot
STATUS1
Rprot
INPUT1
Dld
Rprot
STATUS2
Rprot
INPUT2
Rprot
STATUS3
µC
OUTPUT1
OUTPUT2
OUTPUT3
Rprot
INPUT3
Rprot
STATUS4
OUTPUT4
Rprot
INPUT4
GND1,2
GND3,4
RGND
DGND
VGND
+5V +5V
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / 2(IS(on)max ).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor
or several devices have to share the same resistor then
the ST suggests to utilize Solution 2.
9/21
VNQ810M
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
10/21
same applies if the device will be subject to transients on
the VCC line that are greater than the ones shown in the
ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between
the leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
VNQ810M
OPEN LOAD DETECTION IN OFF STATE
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled
high (up to several mA), the pull-up resistor RPU should
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
positive supply voltage (VPU) like the +5V line used to
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
1) no false open load indication when load is connected:
in this case we have to avoid VOUT to be higher than
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
be connected to a supply that is switched OFF when the
module is in standby.
The values of VOLmin, VOLmax and IL(off2) are available in
the Electrical Characteristics section.
Open Load detection in off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
RL
GROUND
11/21
VNQ810M
High Level Input Current
Off State Output Current
IL(off1) (uA)
Iih (uA)
1.6
5
1.44
4.5
Off state
Vcc=36V
Vin=Vout=0V
1.28
1.12
Vin=3.25V
4
3.5
0.96
3
0.8
2.5
0.64
2
0.48
1.5
0.32
1
0.16
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
Tc (ºC)
75
100
125
150
175
Tc (°C)
Input Clamp Voltage
Status Leakage Current
Vicl (V)
Ilstat (uA)
8
0.05
7.8
Iin=1mA
7.6
0.04
7.4
Vstat=5V
7.2
0.03
7
0.02
6.8
6.6
6.4
0.01
6.2
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Status Low Output Voltage
Status Clamp Voltage
Vscl (V)
Vstat (V)
8
0.8
7.8
0.7
Istat=1mA
Istat=1.6mA
7.6
0.6
7.4
0.5
7.2
7
0.4
6.8
0.3
6.6
0.2
6.4
0.1
6.2
6
0
-50
-25
0
25
50
75
Tc (°C)
12/21
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VNQ810M
On State Resistance Vs VCC
On State Resistance Vs Tcase
Ron (mOhm)
Ron (mOhm)
400
300
275
350
Iout=1A
Vcc=8V; 13V & 36V
300
250
Tc= 150°C
225
250
200
Iout=1A
175
200
150
150
Tc= 25°C
125
100
100
Tc= - 40°C
50
75
0
50
-50
-25
0
25
50
75
100
125
150
175
5
10
15
20
25
30
35
40
Vcc (V)
Tc (°C)
Openload On State Detection Threshold
Input High Level
Iol (mA)
Vih (V)
60
3.6
55
3.4
Vcc=13V
Vin=5V
50
3.2
45
3
40
2.8
35
30
2.6
25
2.4
20
2.2
15
2
10
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Tc (°C)
Input Low Level
Input Hysteresis Voltage
Vil (V)
Vhyst (V)
2.6
1.5
1.4
2.4
1.3
2.2
1.2
2
1.1
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
13/21
VNQ810M
Overvoltage Shutdown
Openload Off State Voltage Detection Threshold
Vov (V)
Vol (V)
50
5
48
4.5
46
4
44
3.5
42
3
40
2.5
38
2
36
1.5
34
1
32
0.5
Vin=0V
30
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
75
100
125
150
175
Tc (°C)
Turn-on Voltage Slope
Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
1000
500
900
450
Rl=26Ohm
Vcc=13V
Rl=13Ohm
800
400
700
350
600
300
500
250
400
200
300
150
200
100
100
50
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Ilim (A)
2
1.8
1.6
Vcc=13V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
Tc (°C)
-50
-25
0
25
50
75
Tc (°C)
ILIM Vs Tcase
14/21
50
100
125
150
175
100
125
150
175
VNQ810M
Maximum turn off current versus load inductance
ILM AX (A)
10
A
1
B
C
0.1
1
10
100
1000
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at T Jstart=100ºC
C= Repetitive Pulse at T Jstart=125ºC
Conditions:
VCC=13.5V
Values are generated with R L=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
15/21
VNQ810M
SO-28 DOUBLE ISLAND THERMAL DATA
SO-28 Double island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
Thermal calculation according to the PCB heatsink area
Chip 1
ON
OFF
ON
ON
Chip 2
OFF
ON
ON
ON
Tjchip1
RthA x Pdchip1 + Tamb
RthC x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
(RthA x Pdchip1) + RthC x Pdchip2 + Tamb
Tjchip2
Note
RthC x Pdchip1 + Tamb
RthA x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
Pdchip1=Pdchip2
(RthA x Pdchip2) + RthC x Pdchip1 + T amb Pdchip1≠Pdchip2
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_am b
(°C/W)
70
60
50
RthA
40
RthB
30
20
RthC
10
0
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1
2
3
4
5
PCB Cu heatsink area (cm ^2)/island
6
7
VNQ810M
SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(°C/W)
100
0,5 cm ^2/is land
3 cm ^2/is land
6 cm ^2/is land
10
One channel ON
1
Two channels
ON on same chip
0.1
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
time(s)
Thermal fitting model of a four channels HSD
in SO-28
Tj_1
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd1
Tj_2
C13
R13
C14
R14
Pd2
R17
Tj_3
R18
C7
C8
C9
R7
R8
R9
C10
C11
C12
Pd3
Tj_4
C15
R15
R10
C16
R16
Pd4
T_amb
R11
R12
Pulse calculation formula
Z TH δ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Thermal Parameter
Area/island (cm2)
R1=R7=R13=R15 (°C/W)
R2=R8=R14=R16 (°C/W)
R3=R9 (°C/W)
R4=R10 (°C/W)
R5=R11 (°C/W)
R6=R12 (°C/W)
C1=C7=C13=C15 (W.s/°C)
C2=C8=C14=C16 (W.s/°C)
C3=C9 (W.s/°C)
C4=C10 (W.s/°C)
C5=C11 (W.s/°C)
C6=C12 (W.s/°C)
R17=R18 (°C/W)
0.5
0.35
1.8
4.5
11
15
30
0.0001
7.00E-04
6.00E-03
0.2
1.5
5
150
6
13
8
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VNQ810M
SO-28 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
inch
MAX.
TYP.
2.65
MAX.
0.104
a1
0.10
0.30
0.004
0.012
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
17.7
E
10.00
e
18.1
0.697
10.65
0.393
1.27
e3
0.713
0.419
0.050
16.51
0.650
F
7.40
7.60
L
0.40
1.27
S
18/21
MIN.
8 (max.)
0.291
0.299
0.016
0.050
VNQ810M
SO-28 TUBE SHIPMENT (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
28
700
532
3.5
13.8
0.6
All dimensions are in mm.
A
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
16.4
60
22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
All dimensions are in mm.
16
4
12
1.5
1.5
7.5
6.5
2
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
19/21
VNQ810M
REVISION HISTORY
Date
Revision
Description of Changes
- Minor changes
- Current and voltage convention update (page 3).
- “Configuration diagram (top view) & suggested connections for unused and n.c. pins”
insertion (page 3).
Jul 2004
1
- 6 cm2 Cu condition insertion in Thermal Data table (page 4).
- VCC - OUTPUT DIODE section update (page 5).
- PROTECTIONS note insertion (page 5)
- Revision History table insertion (page 20).
- Disclaimers update (page 21).
20/21
1
VNQ810M
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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