Preliminary Revised August 2001 74LCX32646 Low Voltage 32-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) General Description Features The LCX32646 contains thirty-two non-inverting bidirectional registered bus transceivers with 3-STATE outputs, providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 32-bit operation.The DIRn inputs determine the direction of data flow through the device. The CPABn and CPBAn inputs load data into the registers on the LOW-toHIGH transition (see Functional Description). ■ 5V tolerant inputs and outputs The LCX32646 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX32646 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V–3.6V VCC specifications provided ■ 5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA Output Drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human Body Model > 2000V Machine Model > 200V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX32646GX (Note 2) Package Number BGA114A (Preliminary) Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500635 www.fairchildsemi.com 74LCX32646 Low Voltage 32-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) August 2001 74LCX32646 Preliminary Connection Diagram Pin Descriptions Pin Names Pin Assignment for FBGA Description 1A0 - 1A15 Side A Inputs or 3-STATE Outputs 2A0 - 2A15 1B0 - 1B15 Side B Inputs or 3-STATE Outputs 2B0 - 2B15 OEn Output Enable Inputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs DIRn Direction Control Inputs NC No Connect FBGA Pin Assignments (Top Thru View) www.fairchildsemi.com 2 1 2 A 1A0 SAB1 3 4 B 1A2 1A1 DIR1 OE1 1B1 1B2 C 1A4 1A3 GND GND 1B3 1B4 D 1A6 1A5 VCC VCC 1B5 1B6 E 1A8 1A7 GND GND 1B7 1B8 F 1A10 1A9 GND GND 1B9 1B10 G 1A12 1A11 VCC VCC 1B11 1B12 H 1A13 1A14 GND GND 1B14 1B13 J 1A15 SAB2 SBA2 1B15 K NC CPAB3 OE2 CPBA3 NC CPAB1 CPBA1 CPAB2 CPBA2 DIR2 5 6 SBA1 1B0 L 2A0 SAB3 DIR3 OE3 SBA3 2B0 M 2A2 2A1 GND GND 2B1 2B2 N 2A4 2A3 VCC VCC 2B3 2B4 P 2A6 2A5 GND GND 2B5 2B6 R 2A8 2A7 GND GND 2B7 2B8 T 2A10 2A9 VCC VCC 2B9 2B10 GND GND U 2A12 2A11 V 2A13 2A14 W 2A15 SAB4 CPAB4 CPBA4 DIR4 OE4 2B11 2B12 2B14 2B13 SBA4 2B15 Preliminary (Note 3) Inputs OE1 DIR1 H X H X H X L H L H L H Data I/O (Note 4) CPAB1 CPBA1 SAB1 SBA1 1A0–7 1B0–7 Input Input Output Operation Mode H or L H or L X X X X X X X X L X X L X X H X A Register to Bn (Stored Mode) X H X Clock An Data into A Register and Output to Bn X L X L X H B Register to An (Stored Mode) X H Clock Bn into B Register and Output to An X H or L L H L L L L X L L X L L X X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition X X H or L Isolation Clock An Data into A Register Clock Bn Data Into B Register An to Bn — Real Time (Transparent Mode) Input Output Clock An Data to A Register Bn to An — Real Time (Transparent Mode) Output Input Clock Bn Data into B Register Note 3: Data I/O paths (1A and 1B: 0 - 7) is shown. This also applies to data I/O (1A and 1B: 8 - 15) and #2 control pins, to data (2A and 2B: 0 - 7) and #3 control pins, to data (2A and 2B: 8 - 15) and #4 control pins. Note 4: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 3 www.fairchildsemi.com 74LCX32646 Truth Table 74LCX32646 Preliminary Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Preliminary 74LCX32646 Logic Diagrams (Continued) Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 5 www.fairchildsemi.com 74LCX32646 Preliminary Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples shown below demonstrate the four fundamental bus-management functions that can be performed for data I/O 1A and 1B: 0 - 7. The direction control (DIRn) determines which bus will receive data when OEn is LOW. In the isolation mode (OEn HIGH), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OE1 DIR1 L L CPAB1 CPBA1 SAB1 X X X SBA1 OE1 DIR1 L L H Transfer Storage Data to A or B CPAB1 CPBA1 SAB1 X X L SBA1 X Storage OE1 DIR1 SBA1 OE1 DIR1 CPAB1 CPBA1 SAB1 SBA1 L L X H or L X H L H H H or L X H X L X H X H X X L www.fairchildsemi.com CPAB1 CPBA1 SAB1 6 X X X X L X L X X X X Preliminary Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 6) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 7) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Unused inputs and I/Os must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 Units V V 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = V IH or VIL IOFF Power-Off Leakage Current VI or VO = 5.5V 7 www.fairchildsemi.com 74LCX32646 Absolute Maximum Ratings(Note 5) 74LCX32646 Preliminary DC Electrical Characteristics Symbol Parameter (Continued) TA = −40°C to +85°C VCC Conditions (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 8) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 8: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 5.2 1.5 6.0 1.5 6.2 5.2 1.5 6.0 1.5 6.2 6.0 1.5 7.0 1.5 7.2 1.5 7.0 1.5 7.2 1.5 7.0 1.5 7.2 7.0 1.5 7.2 8.5 1.5 9.8 Units fMAX Maximum Clock Frequency 170 tPHL Propagation Delay 1.5 tPLH Bus to Bus 1.5 tPHL Propagation Delay 1.5 tPLH Clock to Bus 1.5 6.0 tPHL Propagation Delay 1.5 6.0 tPLH Select to Bus 1.5 6.0 1.5 tPZL Output Enable Time 1.5 7.5 1.5 1.5 7.5 1.5 8.5 1.5 9.8 Output Disable Time 1.5 6.5 1.5 7.5 1.5 7.8 1.5 6.5 1.5 7.5 1.5 7.8 tS Setup Time 2.5 tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tPZH tPLZ tPHZ ns 2.5 3.0 ns ns ns ns ns ns Dynamic Switching Characteristics Symbol VOLP VOLV VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, F = 10 MHz 20 pF www.fairchildsemi.com Conditions 8 Preliminary 74LCX32646 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 9 www.fairchildsemi.com 74LCX32646 Preliminary Schematic Diagram Generic for LCX Family www.fairchildsemi.com 10 Preliminary 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com 74LCX32646 Low Voltage 32-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted