DG540/541/542 Wideband/Video “T” Switches Features Benefits Applications Wide Bandwidth: 500 MHz Low Crosstalk: –85 dB High Off-Isolation: –80 dB @ 5 MHz “T” Switch Configuration TTL Logic Compatible Fast Switching—tON: 45 ns Low rDS(on): 30 Flat Frequency Response High Color Fidelity Low Insertion Loss Improved System Performance Reduced Board Space Reduced Power Consumption Improved Data Throughput RF and Video Switching RGB Switching Local and Wide Area Networks Video Routing Fast Data Acquisition ATE Radar/FLR Systems Video Multiplexing Description The DG540/541/542 are high performance monolithic wideband/video switches designed for switching RF, video and digital signals. By utilizing a “T” switch configuration on each channel, these devices achieve exceptionally low crosstalk and high off-isolation. The crosstalk and off-isolation of the DG540 are further improved by the introduction of extra GND pins between signal pins. To achieve TTL compatibility, low channel capacitances and fast switching times, the DG540 family is built on the Siliconix proprietary D/CMOS process. Each switch conducts equally well in both directions when on. Functional Block Diagrams and Pin Configurations DG540 DG540 IN2 D1 D2 GND GND S1 S2 V– V+ GND GND S4 S3 GND GND D4 D3 IN4 IN3 PLCC IN1 Dual-In-Line Truth Table S1 GND V– GND S4 GND Logic Switch S2 0 OFF V+ 1 ON GND S3 Logic “0” 0.8 V Logic “1” 1 2V Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70055. Siliconix S-53694—Rev. E, 28-May-97 1 DG540/541/542 Functional Block Diagrams and Pin Configurations (Cont’d) DG541 DG542 Dual-In-Line and SOIC IN1 IN2 IN1 IN2 D1 D2 D1 D2 S1 S2 GND GND V– V+ S1 S2 GND GND V– V+ S4 S3 S4 S3 D4 D3 GND GND IN4 IN3 D4 D3 0 OFF 0 OFF ON 1 ON 1 ON OFF Logic “0” 0.8 V Logic “1” 2 V Logic “0” 0.8 V Logic “1” 2 V Ordering Information Temp Range Package Part Number DG540 –40toto85 _C –40 85_C –55 to 125_C 20-Pin Plastic DIP DG540DJ 20-Pin PLCC DG540DN 20-Pin Sidebraze DG540AP DG540AP/883 DG541 –40 to 85_C –55 to 125_C 16-Pin Plastic DIP DG541DJ 16-Pin Narrow SOIC DG541DY 16-Pin Sidebraze DG541AP DG541AP/883 DG542 –40 to 85_C –55 to 125_C 2 16-Pin Plastic DIP DG542DJ 16-Pin Narrow SOIC DG542DY 16-Pin Sidebraze DG542AP DG542AP/883 Siliconix S-53694—Rev. E, 28-May-97 DG540/541/542 Absolute Maximum Ratings V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to +0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V+) +0.3 V or 20 mA, whichever occurs first VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) +14 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . 20 mA Current, S or D (Pulsed 1 ms, 10% duty cycle max) . . . . . . . . . . 40 mA Storage Temperature (AP Suffix) . . . . . . . . . . . . . . –65 to 150_C (DJ, DN, DY Suffixes) . . . . . –65 to 125_C Power Dissipation (Package)a 16-Pin Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Pin Narrow Body SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin PLCCd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-, 20-Pin Sidebraze DIPe . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 800 mW 640 mW 800 mW 900 mW Notes: a. All leads welded or soldered to PC Board. b. Derate 6.5 mW/_C above 25_C c. Derate 7 mW/_C above 25_C d. Derate 10 mW/_C above 75_C e. Derate 12 mW/_C above 75_C Schematic Diagram (Typical Channel) V+ GND VREF S IN – + D V– Figure 1. Siliconix S-53694—Rev. E, 28-May-97 3 DG540/541/542 Specificationsa Test Conditions Unless Specified Parameter Symbol V V– V = –33 V V+ = 15 V, VINH = 2 V, VINL = 0.8 Vf VANALOG V– = –5 V, V+ = 12 V Tempb Typc A Suffix D Suffixes –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Range Drain-Source On-Resistance rDS(on) rDS(on) Match DrDS(on) IS = –10 mA,, VD = 0 V Full –5 5 –5 5 Room Full 30 60 100 60 75 Room 2 6 6 Source Off Leakage Current IS(off) VS = 0 V, VD = 10 V Room Full –0.05 –10 –500 10 500 –10 –100 10 100 Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Room Full –0.05 –10 –500 10 500 –10 –100 10 100 Channel On Leakage Current ID(on) VS = VD = 0 V Room Full –0.05 –10 –1000 10 1000 –10 –100 10 100 V W nA Digital Control Input Voltage High VINH Full Input Voltage Low VINL Full 2 2 0.8 IIN VIN = GND or V+ Room Full 0.05 On State Input Capacitancee CS(on) VS = VD = 0 V Room 14 20 20 Off State Input Capacitancee CS(off) VS = 0 V Room 2 4 4 CD(off) VD = 0 V Room 2 4 4 BW RL = 50 W , See Figure 5 Room 500 DG540 DG541 Room Full 45 70 130 70 130 DG542 Room Full 55 100 160 100 160 DG540 DG541 Room Full 20 50 85 50 85 DG542 Room Full 25 60 85 60 85 Room –25 DG540 Room –80 DG541 Room –60 DG542 Room –75 Room –85 Room Full 3.5 Room Full –3.2 Input Current –1 –20 1 20 V 0.8 –1 –20 1 20 mA Dynamic Characteristics Off State Output Capacitancee Bandwidth Turn On Time Turn Off Time Charge Injection Off Isolation All Hostile Crosstalk tON RL = 1 kW W CL = 35 pF p 50% to 90% See Figure 2 tOFF Q OIRR XTALK(AH) CL = 1000 pF, VS = 0 V See Figure 3 RIN = 75 W RL = 75 W f = 5 MHz See Figure 4 RIN = 10 W , RL = 75 W f = 5 MHz, See Figure 6 pF MHz ns pC dB Power Supplies Positive Supply Current I+ Negative Supply Current I– All Channels On or Off 6 9 –6 –9 6 9 –6 –9 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. 4 Siliconix S-53694—Rev. E, 28-May-97 mA DG540/541/542 Typical Characteristics Supply Curent vs. Temperature 6 ID(off), IS(off) vs. Temperature 100 nA 5 10 nA 4 3 I S(off) , I D(off) – Leakage I+ I (mA) 2 1 IGND 0 –1 –2 I– –3 1 nA 100 pA 10 pA 1 pA –4 0.1 pA –5 –55 –35 –15 25 45 65 Temperature (_C) 85 105 125 125_C 100 80 25_C 60 –55_C 40 25 50 75 Temperature (_C) V+ Constant 20 V– Constant 40 40 38 38 V– = –5 V 36 V+ = 12 V 34 34 32 32 V+ = 15 V 30 1 3 5 7 9 20 20 VD – Drain Voltage (V) 0 10 11 12 13 14 15 16 V– – Negative Supply (V) V+ – Positive Supply (V) On Capacitance 22 V– = –1 V 18 –5 –4 –3 –2 –1 11 V– = –3 V 30 18 –1 Off Isolation –110 –100 20 –90 18 –80 ISO (dB) 16 C (pF) 125 42 36 0 –3 100 V+ = 10 V rDS(on) – Drain-Source On-Resistance ( 120 0 42 V+ = 15 V V– = –3 V 140 –25 –55 rDS(on) vs. Drain Voltage 160 rDS(on) – Drain-Source On-Resistance ( 5 14 12 DG540 –70 DG542 –60 –50 DG541 –40 10 –30 8 –20 –10 6 0 2 4 6 8 10 VD – Drain Voltage (V) Siliconix S-53694—Rev. E, 28-May-97 12 14 1 10 100 f – Frequency (MHz) 5 DG540/541/542 Typical Characteristics (Cont’d) Off Isolation vs. Frequency and Load Resistance (DG540) All Hostile Crosstalk –100 –90 –110 –100 RL = 75 –80 –80 1 k XTALK (dB) OIRR (dB) –70 –60 10 k –50 –40 DG542 –70 –60 DG541 –50 –30 –40 –20 –30 –10 –20 –10 0 1 10 40 100 10 1 100 f – Frequency (MHz) f – Frequency (MHz) Charge Injection vs. VS Switching Times vs. Temperature (DG540/541) 90 80 30 70 20 60 Time (ns) 10 Q (pC) DG540 –90 180 0 –10 tON 50 40 30 –20 tOFF 20 CL = 1000 pF –30 10 0 –40 –3 –2 –1 0 1 2 3 4 5 6 7 8 –55 –25 VS – Source Voltage (V) 0 25 50 75 100 125 Temperature (_C) Switching and Break-Before-Make Time vs. Temperature (DG542) Operating Supply Voltage Range 20 90 80 18 V+ – Positive Supply (V) tON 70 Time (ns) 60 tBBM 50 40 tOFF 30 20 16 Operating Voltage Area 14 12 10 0 10 –55 –25 0 25 50 Temperature (_C) 6 75 100 125 0 –1 –2 –3 –4 –5 –6 V– – Negative Supply (V) Siliconix S-53694—Rev. E, 28-May-97 DG540/541/542 Test Circuits +15 V D S Logic Input VO IN GND tr <20 ns tf <20 ns 3V V+ CL 35 pF RL 1 kW V– Switch Input 50% VS 90% Switch Output –3 V 0 tON tOFF CL (includes fixture and stray capacitance) RL VO = VS RL + rDS(on) Figure 2. Switching Time DVO +15 V Rg V+ S VO D VO IN Vg CL 1000 pF 3V GND V– INX ON OFF ON DVO = measured voltage error due to charge injection The charge injection in coulombs is DQ = CL x DVO –3 V Figure 3. Charge Injection +15 V +15 V C C V+ S VS VO D Rg = 75 W RL 75 W IN 0 V, 2.4 V GND V– –3 V Off Isolation = 20 log C = RF Bypass C V+ S VS VO D Rg = 50 W 0 V, 2.4 V RL 50 W IN GND V– C –3 V VS VO Figure 4. Off Isolation Siliconix S-53694—Rev. E, 28-May-97 Figure 5. Bandwidth 7 DG540/541/542 Test Circuits (Cont’d) C +15 V V+ S1 10 W 2.4 V D1 VO RL 75 W INX S2 D2 S3 D3 S4 D4 GND RL RL V– RL C –15 V V OUT X TALK(AH) 20 log 10 V IN Figure 6. All Hostile Crosstalk Applications Device Description The DG540/541/542 family of wideband switches offers true bidirectional switching of high frequency analog or digital signals with minimum signal crosstalk, low insertion loss, and negligible non-linearity distortion and group delay. Built on the Siliconix D/CMOS process, these “T” switches provide excellent off-isolation with a bandwidth of around 500 MHz (350 MHz for DG541). Silicon-gate D/CMOS processing also yields fast switching speeds. An on-chip regulator circuit maintains TTL input compatibility over the whole operating supply voltage range, easing control logic interfacing. Circuit layout is facilitated by the interchangeability of source and drain terminals. Frequency Response A single switch on-channel exhibits both resistance [rDS(on)] and capacitance [CS(on)]. This RC combination has 8 an attenuation effect on the analog signal – which is frequency dependent (like an RC low-pass filter). The –3-dB bandwidth of the DG540 is typically 500 MHz (into 50 W). This measured figure of 500 MHz illustrates that the switch channel can not be represented by a two stage RC combination. The on capacitance of the channel is distributed along the on-resistance, and hence becomes a more complex multi stage network of R’s and C’s making up the total rDS(on) and CS(on). See Application Note AN502 for more details. Off-Isolation and Crosstalk Off-isolation and crosstalk are affected by the load resistance and parasitic inter-electrode capacitances. Higher off-isolation is achieved with lower values of RL. However, low values of RL increase insertion loss requiring gain adjustments down the line. Stray capacitances, even a fraction of 1 pF, can cause a large crosstalk increase. Good layout and ground shielding techniques can considerably improve your ac circuit performance. Siliconix S-53694—Rev. E, 28-May-97 DG540/541/542 Applications (Cont’d) Power Supplies 3. A useful feature of the DG54X family is its power supply flexibility. It can be operated from a single positive supply (V+) if required (V– connected to ground). Capacitors should have good high frequency characteristics - tantalum bead and/or monolithic ceramic types are adequate. Suitable decoupling capacitors are 1Ć to 10ĆmF tantalum bead, plus 10Ć to 100ĆnF ceramic. Note that the analog signal must not exceed V– by more than –0.3 V to prevent forward biasing the substrate p-n junction. The use of a V– supply has a number of advantages: 1. 2. +15 V + It allows flexibility in analog signal handling, i.e., with V- = -5 V and V+ = 12 V; up to 5ĆV ac signals can be controlled. The value of on capacitance [CS(on)] may be reduced. A property known as `the bodyĆeffect' on the DMOS switch devices causes various parametric effects to occur. One of these effects is the reduction in CS(on) for an increasing V body-source. Note, however, that to increase Vnormally requires V+ to be reduced (since V+ to V- = 21 V max.). Reduction in V+ causes an increase in rDS(on), hence a compromise has to be achieved. It is also useful to note that optimum video linearity performance (e.g., differential phase and gain) occurs when V- is around -3 V. C1 C2 V+ S1 D1 S2 D2 DG540 S3 D3 S4 D4 GNDs V– C1 = 10 mF Tantalum C2 = 0.1 mF Ceramic C1 C2 + –3 V 3. V- eliminates the need to bias the analog signal using potential dividers and large coupling capacitors. Figure 7. Supply Decoupling Decoupling Board Layout It is an established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG54X is adversely affected by poor decoupling of power supply pins. Also, of even more significance, since the substrate of the device is connected to the negative supply, adequate decoupling of this pin is essential. PCB layout rules for good high frequency performance must be observed to achieve the performance boasted by the DG540. Some tips for minimizing stray effects are: Rules: 1. Decoupling capacitors should be incorporated on all power supply pins (V+, V-). (See Figure 7.) 2. They should be mounted as close as possible to the device pins. Siliconix S-53694—Rev. E, 28-May-97 1. Use extensive ground planes on double sided PCB, separating adjacent signal paths. Multilayer PCB is even better. 2. Keep signal paths as short as practically possible, with all channel paths of near equal length. 3. Careful arrangement of ground connections is also very important. Star connected system grounds eliminate signal current flowing through ground path parasitic resistance from coupling between channels. 9 DG540/541/542 Applications (Cont’d) Figure 8 shows a 4-channel video multiplexer using a DG540. +15 V V+ CH1 CH2 75 Si582 75 + A=2 CH3 75 CH4 – 75 DIS 250 DG540 V– 75 250 –3 V TTL Channel Select Figure 8. 4 by 1 Video Multiplexing Using the DG540 Figure 9 shows an RGB selector switch using two DG542s. +15 V V+ R1 75 Red Out R2 75 G1 75 Green Out G2 75 DG542 V– –3 V +15 V Si584 V+ B1 75 Blue Out B2 75 Sync 1 75 Sync Out Sync 2 75 DG542 RGB Source Select V– –3 V Figure 9. RGB Selector Using Two DG542s 10 Siliconix S-53694—Rev. E, 28-May-97