DG535/536 Vishay Siliconix 16-Channel Wideband Video Multiplexers DESCRIPTION FEATURES The DG535/536 are 16-channel multiplexers designed for routing one of 16 wideband analog or digital input signals to a single output. They feature low input and output capacitance, low on-resistance, and n-channel DMOS “T” switches, resulting in wide bandwidth, low crosstalk and high “off” isolation. In the on state, the switches pass signals in either direction, allowing them to be used as multiplexers or as demultiplexers. • • • • • • • On-chip address latches and decode logic simplify microprocessor interface. Chip Select and Enable inputs simplify addressing in large matrices. Single-supply operation and a low 75 µW power consumption vastly reduces power supply requirements. BENEFITS Theses devices are built on a proprietary D/CMOS process which creates low-capacitance DMOS FETs and high-speed, low-power CMOS logic on the same substrate. For more information please refer to Vishay Siliconix Application Note AN501 (FaxBack document number 70608). • • • • • Crosstalk: - 100 dB at 5 MHz 300 MHz Bandwidth Low Input and Output Capacitance Low Power: 75 µW Low rDS(on): 50 Ω On-Board Address Latches Disable Output Pb-free Available RoHS* COMPLIANT High Video Quality Reduced Insertion Loss Reduced Input Buffer Requirements Minimizes Power Consumption Simplifies Bus Interface APPLICATIONS • • • • • • Video Switching/Routing High Speed Data Routing RF Signal Multiplexing Precision Data Acquisition Crosspoint Arrays FLIR Systems FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION 28 S9 2 27 S10 GND S7 3 26 S11 6 5 4 3 2 S6 4 25 S12 DIS S5 5 24 S13 7 39 S6 CS 8 38 GND S14 CS 9 37 S7 EN 10 36 GND A0 11 35 S8 34 GND 33 S9 7 22 S15 S2 8 21 S16 S1 9 20 D DIS 10 19 V+ CS 11 18 ST CS 12 17 A3 16 A2 15 A1 Latches/Decoders/Drivers EN 13 A0 14 Top View GND GND S5 GND S4 S3 GND S2 GND Latches/ Decoders/ Drivers A1 12 A2 13 A3 14 32 GND ST 15 31 S10 V+ 16 30 GND D 17 29 S11 18 19 20 21 22 23 24 25 26 27 28 GND S3 GND S12 23 1 44 43 42 41 40 S14 GND S13 6 S15 GND S4 PLCC/Cerquad S1 S8 DG536 DG535 S16 GND 1 GND GND Dual-In-Line Top View * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70070 S-71241–Rev. E, 25-Jun-07 www.vishay.com 1 DG535/536 Vishay Siliconix ORDERING INFORMATION Temperature Range Package Part Number DG535DJ DG535DJ-E3 28-Pin Plastic DIP - 40 to 85 °C DG536DN DG536DN-E3 44-Pin PLCC TRUTH TABLE EN CS CS STa A3 A2 A1 A0 Channel Selected Disableb 0 X X X 0 X X X 1 1 X X X X None High Z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 Maintains previous switch condition 1 1 0 1 X X X Logic "0" = VAL ≤ 4.5 V Logic "1" = VAH ≥ 10.5 V X = Do not Care 0 Low Z High Z or Low Z Notes: a. Strobe input (ST) is level triggered. b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected. ABSOLUTE MAXIMUM RATINGS Parameter V+ to GND Digital Inputs VS, VD Current (any terminal) Continuous Current (S or D) Pulsed 1 ms 10 % duty cycle (A Suffix) Storage Temperature (D Suffix) Power Dissipation (Package)a 28-Pin Plastic DIPb 28-Pin Sidebrazec 44-Pin PLCCd 44-Pin Cerquade Limit - 0.3 to + 18 (GND - 0.3) to (V+) + 2 or 20 mA, whichever occurs first (GND - 0.3) to (V+) + 2 or 20 mA, whichever occurs first 20 40 - 65 to 150 - 65 to 125 625 1200 450 825 Unit V mA °C mW Notes: a. All leads soldered or welded to PC board. b. Derate 8.6 mW/°C above 75 °C. c. Derate 16 mW/°C above 75 °C. d. Derate 6 mW/°C above 75 °C. e. Derate 11 mW/°C above 75 °C. www.vishay.com 2 Document Number: 70070 S-71241–Rev. E, 25-Jun-07 DG535/536 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V Parameter Analog Switch Symbol Analog Signal Rangee Drain-Source On-Resistance Resistance Match VANALOG rDS(on) ΔrDS(on) CS = 4.5 V, VA = 4.5 or 10.5 Vf Typc Full IS = - 1 mA, VD = 3 V, EN = 10.5 V Sequence Each Switch On Source Off Leakage Current IS(off) VS = 3 V, VD = 0 V, EN = 4.5 V Drain On Leakage Current ID(on) VS = VD = 3 V, EN = 10.5 V RDISABLE IDISABLE = 1 mA, EN = 10.5 V Disable Output Tempb Room Full Room Room Full Room Full Room Full A Suffix - 55 to 125 °C D Suffix - 40 to 85 °C Minc Maxc Minc 0 10 0 55 - 10 - 100 - 10 - 1000 100 90 120 9 10 100 10 1000 200 250 - 10 - 100 - 10 - 100 Maxc Unit 10 V 90 120 9 10 100 - 10 - 100 200 250 Ω nA Ω Digital Control Input Voltage High VAIH Full Input Voltage Low VAIL Full Room Full Full Address Input Current IAI Address Input Capacitance CA VA = GND or V+ 10.5 < 0.01 -1 - 100 10.5 4.5 1 100 -1 - 100 4.5 1 100 V µA pF 5 Dynamic Characteristics On State Input Capacitance e Off State Input Capacitancee Off State Output Capacitancee CS(on) CS(off) CD(off) Multiplexer Switching Time tTRANS Break-Before-Make Interval tOPEN VD = V S = 3 V VS = 3 V VD = 3 V PLCC Room 32 Cerquad Room 35 DIP PLCC Room Room 40 2 Cerquad Room 5 DIP Room 3 PLCC Room 8 Cerquad Room 12 DIP Room 9 45 55 8 55 8 pF 20 Full See Figure 4 45 20 300 Full 25 300 25 EN, CS, CS, ST, tON tON See Figure 2 and 3 Full 300 300 EN, CS, CS, ST, tOFF tOFF See Figure 2 Full 150 150 Charge Injection Single-Channel Crosstalk Chip Disabled Crosstalk Adjacent Input Crosstalk All Hostile Crosstalke Bandwidth Document Number: 70070 S-71241–Rev. E, 25-Jun-07 Q XTALK(SC) XTALK(CD) XTALK(AI) XTALK(AH) BW See Figure 5 Room - 35 Room - 100 RIN = 75 Ω, RL = 75 Ω f = 5 MHz See Figure 9 Cerquad Room - 93 DIP Room - 60 RIN = RL = 75 Ω, f = 5 MHz EN = 4.5 V See Figure 8 PLCC Room - 85 Cerquad Room - 84 RIN = 10 Ω, RL = 10 kΩ f = 5 MHz See Figure 10 DIP PLCC Room Room - 60 - 92 Cerquad Room - 87 DIP Room - 72 RIN = 10 Ω, RL = 10 kΩ f = 5 MHz See Figure 7 PLCC Room - 74 Cerquad Room - 74 DIP Room - 60 Room 500 PLCC RL = 50 Ω, See Figure 6 ns pC dB - 60 - 60 MHz www.vishay.com 3 DG535/536 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V Symbol CS = 4.5 V, VA = 4.5 or 10.5 Vf Tempb Typc Positive Supply Current I+ V+ Room Full Full 5 Supply Voltage Range Any One Channge I Selected with All Logic Inputs at GND or V+ Parameter Power Supplies Minimum Input Timing Requirements tSW Strobe Pulse Width A0, A1, A2, A3 CS, CS, EN Data Valid to Strobe tDW A0, A1, A2, A3 CS, CS, EN Data Valid after Strobe tWD A Suffix - 55 to 125 °C D Suffix - 40 to 85 °C Minc Maxc Minc Maxc 10 50 100 16.5 10 50 100 16.5 Full 200 200 Full 100 100 Unit See Figure 1 µA V ns Full 50 50 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VA = input voltage to perform proper function. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 300 V+ = +15 V GND = 0 V 360 r DS(on) – Drain-Source On-Resistance (Ω) r DS(on) – Drain-Source On-Resistance (Ω) 400 320 280 240 125 °C 200 160 120 25 °C 80 - 55 °C 40 0 GND = 0 V TA = 25 °C 270 240 210 8V 180 12 V 150 15 V 120 90 60 30 0 0 2 4 6 8 VD – Drain Voltage (V) rDS(on) vs. VD and Temperature www.vishay.com 4 10 0 2 4 6 8 10 VD – Drain Voltage (V) rDS(on) vs. VD and Power Supply Voltage Document Number: 70070 S-71241–Rev. E, 25-Jun-07 DG535/536 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 14 10 9 GND = 0 V TA = 25 °C 8 10 7 125 °C 6 8 I+ (µA) V th (V) GND = 0 V 12 5 4 25 °C 6 3 4 - 55 °C 2 2 1 0 0 10 8 12 14 16 18 10 11 12 V+ – Positive Supply (V) Logic Input Switching Threshold vs. Supply Voltage (V+) 14 15 16 17 18 Supply Current vs. Supply Voltage and Temperature 1 µA 1 µA V+ = + 15 V GND = 0 V VD = V S = 3 V 100 nA V+ = + 15 V GND = 0 V 100 nA 10 nA I S, I D – Leakage I D(on) – Leakage 13 V+ – Positive Supply (V) 1 nA 100 pA 10 pA ID(off) 10 nA IS(off) 1 nA 100 pA 10 pA 1 pA 1 pA - 55 - 35 - 15 5 25 45 65 85 105 125 - 55 - 35 - 15 5 Temperature (°C) 25 45 65 85 105 125 Temperature (°C) ID(on) vs. Temperature Leakage Current vs. Temperature 0 - 120 DG536 RIN = 10 Ω - 100 -4 Insertion Loss (dB) X TALK(AI) (dB) DG536 - 80 DG536 RIN = 75 Ω - 60 DG535 RIN = 10 Ω - 40 -8 - 3 dB Points - 12 Test Circuit See Figure 6 RL = 50 Ω - 16 - 20 DG535 Test Circuit See Figure 10 - 20 0 0.1 1 10 f – Frequency (MHz) Adjacent Input Crosstalk vs. Frequency Document Number: 70070 S-71241–Rev. E, 25-Jun-07 100 1 10 100 1000 f – Frequency (MHz) - 3 dB Bandwidth Insertion Loss vs. Frequency www.vishay.com 5 DG535/536 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted - 160 - 160 Test Circuit See Figure 8 - 140 - 100 DG536 RL = 75 Ω - 80 X TALK(AH) (dB) X TALK(CD) (dB) DG536 RIN = 10 Ω RL = 10 kΩ - 120 - 120 DG536 RL = 50 Ω DG535 RL = 75 Ω - 60 - 100 DG536 RIN = 75 Ω RL = 75 Ω - 80 - 60 - 40 - 40 - 20 - 20 DG535 RIN = 10 Ω RL = 10 kΩ 0 0 0.1 1 10 100 0.1 1 10 100 f – Frequency (MHz) f – Frequency (MHz) Chip Disable Crosstalk vs. Frequency All Hostile Crosstalk vs. Frequency - 160 160 Test Circuit See Figures 2, 3, 4 140 Test Circuit See Figure 9 RIN = 75 Ω RL = 75 Ω - 140 tON - 120 100 X TALK(SC) (dB) 120 Switching Time (ns) Test Circuit See Figure 7 - 140 tBBM 80 60 tOFF 40 - 100 DG536 - 80 - 60 DG535 - 40 - 20 20 0 0 - 55 - 35 - 15 5 25 45 65 85 105 125 0.1 1 Temperature (°C) 10 100 f – Frequency (MHz) Single Channel Crosstalk vs. Frequency tON, tOFF and Break-Before-Make vs. Temperature INPUT TIMING REQUIREMENTS 15 V ST 7.5 V 0V tSW tDW tWD 15 V 10.5 V 10.5 V 4.5 V 4.5 V CS, A0, A1, A2, A3 CS, EN 0V Figure 1. www.vishay.com 6 Document Number: 70070 S-71241–Rev. E, 25-Jun-07 DG535/536 Vishay Siliconix TEST CIRCUITS + 15 V + 15 V V+ ST A0 A1 A2 A3 Logic Input Address Logic Input tr < 20 ns tf < 20 ns CS 15 V 50 % EN or CS 0V +3V S16 S1 - S15 90 % EN or CS CS GND VO D 1 kΩ Signal Output 35 pF tON tOFF Figure 2. EN, CS, CS, Turn On/Off Time + 15 V + 15 V Address Logic Input tr < 20 ns tf < 20 ns V+ EN, CS A1, A2, A3 S2 - S15 Address Input 50 % 0V +3V S1 15 V 15 V 0V A0 ST Logic Input VO D GND CS 1 kΩ tON(ST) VOUT 90 % 35 pF 0V Figure 3. Strobe ST Turn On Time + 15 V + 15 V +3V Address Logic Input tr < 20 ns tf < 20 ns V+ EN CS ST A0 A1 A2 A3 S1 S16 S2 thru S15 15 V 50 % 0V Switch Output 90 % S16 Turning On S1 Turning Off D GND VO tBBM CS 1 kΩ 35 pF tTRANS Figure 4. Transition Time and Break-Before-Make Interval Document Number: 70070 S-71241–Rev. E, 25-Jun-07 www.vishay.com 7 DG535/536 Vishay Siliconix TEST CIRCUITS + 15 V + 15 V + 15 V V+ A0, A1, A2, A3 ST EN D S16 +3V Logic Input VO CL 1000 pF CS GND + 15 V + 15 V CS V+ S2 thru S15 EN CS ST CS S1 Signal Generator (75 Ω) ΔVOUT VOUT D GND CS A0 to A3 VO RL 50 W ΔVOUT is the measured voltage error due to charge injection. The charge injection in Coulombs is Q = CL x ΔV OUT Figure 6. Bandwidth Figure 5. Charge Injection All Channels Off Channel 1 On S1 S1 S2 S2 S3 S3 RIN S4 S4 S5 S5 S6 S6 S7 S7 S8 S8 VO S9 S10 S10 S11 RL S12 S13 S13 S14 S14 S15 S15 S16 S16 VO X TALK(AH) = 20 log 10 V Figure 7. All Hostile Crosstalk www.vishay.com 8 S11 RL S12 V VO S9 V VO X TALK(CD) = 20 log10 V Figure 8. Chip Disabled Crosstalk Document Number: 70070 S-71241–Rev. E, 25-Jun-07 DG535/536 Vishay Siliconix TEST CIRCUITS Channel 1 On S1 S2 RIN S3 S4 S5 S6 S7 S8 RIN 10 Ω VO S9 VSn–1 S10 S11 V Sn–1 RL VSn S12 Sn S13 VSn+1 S14 S15 Sn+1 RIN 10 Ω S16 RL 10 kΩ Notes: 1. Any individual channel between S2 and S16 can be selected 2. X TALK(SC) = 20 log10 VO V X TALK(AI) = 20 log10 is scanned sequentially from S 2 to S 16 V Sn – 1 V Sn or 20 log10 V Sn + 1 V Sn Figure 10. Adjacent Input Crosstalk Figure 9. Single Channel Crosstalk PIN DESCRIPTION Symbol S1 thru S16 D DIS CS, CS, EN A0 thru A3 Description Analog inputs/outputs Multiplexer output/demultiplexer input Open drain low impedance to analog ground when any channel is selected Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system Binary address inputs to determine which channel is selected ST Strobe input that latches A0, A1, A2, A3, CS, CS, EN V+ Positive supply voltage input GND Analog signal ground and most negative potential All ground pins should be connected externally to ensure dynamic performance Document Number: 70070 S-71241–Rev. E, 25-Jun-07 www.vishay.com 9 DG535/536 Vishay Siliconix DETAILED DESCRIPTION The DG535/536 are 16-channel single-ended multiplexers with on-chip address logic and control latches. The multiplexer connects one of sixteen inputs (S1, S2 through S16) to a common output (D) under the control of a 4-bit binary address (A0 to A3). The specific input channel selected for each address is given in the Truth Table. All four address inputs have on-chip data latches which are controlled by the Strobe (ST) input. These latches are transparent when Strobe is high but they maintain the chosen address when Strobe goes low. To facilitate easy microprocessor control in large matrices a choice of three independent logic inputs (EN, CS and CS) are provided on chip. These inputs are gated together (see Figure 11) and only when EN = CS = 1 and CS = 0 can an output switch be selected. This necessary logic condition is then latched-in when Strobe (ST) goes low. Signal IN SW1 Signal OUT SW3 SW2 Signal GND Figure 12. “T” Switch Arrangement The two second level series switches further improve crosstalk and help to minimize output capacitance. The DIS output can be used to signal external circuitry. DIS is a high impedance to GND when no channel is selected and a low impedance to GND when any one channel is selected. CS Latch CS A1 Latch EN A2 Latch Decode Logic A0 Latch The DG535/536 have extensive applications where any high frequency video or digital signals are switched or routed. Exceptional crosstalk and bandwidth performance is achieved by using n-channel DMOS FETs for the “T” and series switches. Gate Drain Source A3 Latch n+ ST Figure 11. CS, CS, EN, ST Control Logic n+ p pSubstrate GND Break-before-make switching prevents momentary shorting when changing from one input to another. The devices feature a two-level switch arrangement whereby two banks of eight switches (first level) are connected via two series switches (second level) to a common DRAIN output. In order to improve crosstalk all sixteen first level switches are configured as “T” switches (see Figure 12). With this method SW2 operates out of phase with SW1 and SW3. In the on condition SW1 and SW3 are closed with SW2 open whereas in the off condition SW1 and SW3 are open and SW2 closed. In the off condition the input to SW3 is effectively the isolation leakage of SW1 working into the on-resistance of SW2 (typically 200 Ω). www.vishay.com 10 Figure 13. Cross-Section of a Single DMOS Switch It can clearly be seen from Figure 13 that there exists a PN junction between the substrate and the drain/source terminals. Should a signal which is negative with respect to the substrate (GND pin) be connected to a source or drain terminal, then the PN junction will become forward biased and current will flow between the signal source and GND. This effective shorting of the signal source to GND will not necessarily cause any damage to the device, provided that the total current flowing is less than the maximum rating, (i.e., 20 mA). Document Number: 70070 S-71241–Rev. E, 25-Jun-07 DG535/536 Vishay Siliconix DETAILED DESCRIPTION Since no PN junctions exist between the signal path and V+, positive overvoltages are not a problem, unless the breakdown voltage of the DMOS drain terminal (see Figure 13) (+ 18 V) is exceeded. Positive overvoltage conditions must not exceed + 18 V with respect to the GND pin. If this condition is possible (e.g. transients in the signal), then a diode or Zener clamp may be used to prevent breakdown. An alternative method is to offset the supply voltages (see Figure 15). The overvoltage conditions described may exist if the supplies are collapsed while a signal is present on the inputs. If this condition is unavoidable, then the necessary steps outlined above should be taken to protect the device Level shifting of the logic signals may be necessary using this offset supply arrangement. Decoupling would have to be applied to the negative supply to ensure that the substrate is well referenced to signal ground. Again the capacitors should be of a type offering good high frequency characteristics. + 12 V DC Biasing To avoid negative overvoltage conditions and subsequent distortion of ac analog signals, dc biasing may be necessary. Biasing is not required, however, in applications where signals are always positive with respect to the GND or substrate connection, or in applications involving multiplexing of low level (up to ± 200 mV) signals, where forward biasing of the PN substrate-source/drain terminals would not occur. Biasing can be accomplished in a number of ways, the simplest of which is a resistive potential divider and a few dc blocking capacitors as shown in Figure 14. C1 100 µF/16 V Tantalum R1 + S V+ C2 + R2 DG536 GND S V+ DG536 D Analog Signal OUT GND Decoupling Capacitors + -3V Figure 15. DG536 with Offset Supply TTL to CMOS level shifting is easily obtained by using a MC14504B. Circuit Layout + 15 V Analog Signal IN Analog Signal IN D Analog Signal OUT Good circuit board layout and extensive shielding is essential for optimizing the high frequency performance of the DG536. Stray capacitances on the PC board and/or connecting leads will considerably degrade the ac performance. Hence, signal paths must be kept as short as practically possible, with extensive ground planes separating signal tracks. 100 µF/16 V Tantalum Figure 14. Simple Bias Circuit R1 and R2 are chosen to suit the appropriate biasing requirements. For video applications, approximately 3 V of bias is required for optimal differential gain and phase performance. Capacitor C1 blocks the dc bias voltage from being coupled back to the analog signal source and C2 blocks the dc bias from the output signal. Both C1 and C2 should be tantalum or ceramic disc type capacitors in order to operate efficiently at high frequencies. Active bias circuits are recommended if rapid switching time between channels is required. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70070. Document Number: 70070 S-71241–Rev. E, 25-Jun-07 www.vishay.com 11 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1