UTC-IC BT169

UTC BT169
SCR
DESCRIPTION
The UTC BT169 is glass passivated, sensitive gate
thyristors in a plastic envelope, intended for use in
general purpose switching and phase control
applications. These devices are intended to be
interfaced directly to microcontrollers, logic integrated
circuits and other low power gate trigger circuits.
1
TO-92
1:CATHODE
2:GATE
3:ANODE
QUICK REFERENCE DATA
PARAMETER
Repetitive peak off-state voltages
SYMBOL
MAX(B)
MAX(D)
MAX(E)
MAX(G)
UNIT
VDRM, VRRM
200
400
500
600
V
IT(AV)
0.5
0.5
0.5
0.5
A
IT(RMS)
0.8
0.8
0.8
0.8
A
ITSM
8
8
8
8
A
Average on-state current
RMS on-state current
Non-repetitive peak on-state current
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Repetitive peak off-state voltages :
Average on-state current
RMS on-state current
Non-repetitive peak on-state current
I2t for fusing
Repetitive rate of rise of on-state current
after triggering
SYMBOL
CONDITIONS
VDRM,VRRM
MIN
MAX
UNIT
B:200
D:400
E:500
G:600
V
IT(AV)
Half sine wave;
Tlead<=83°C
0.5
A
IT(RMS)
All conduction angles
0.8
A
ITSM
t=10ms
t=8.3ms
half sine wave;
Tj=25°C prior to surge
8
9
A
I2t
t=10ms
0.32
A2 S
DIT/dt
ITM=2A;IG=10mA;
dIG/dt=100mA/µs
50
A/µs
A
Peak gate current
IGM
1
Peak gate voltage
VGM
5
V
Peak reverse gate voltage
VRGM
5
V
UTC
UNISONIC TECHNOLOGIES CO., LTD.
1
UTC BT169
SCR
PARAMETER
SYMBOL
Peak gate power
CONDITIONS
MIN
PGM
Average gate power
PG(AV)
Storage temperature
Tstg
Operating junction temperature
Over any 20 ms period
-40
Tj
MAX
UNIT
2
W
0.1
W
150
°C
125
°C
MAX
UNIT
60
K/W
THERMAL RESISTANCES
PARAMETER
SYMBOL
Thermal resistance junction to lead
Rth j-lead
Thermal resistance junction to
ambient
Rth j-a
CONDITIONS
MIN
pcb mounted;
lead length=4mm
TYP
150
K/W
ELECTRICAL CHARACTERISTICS (Tj=25°C unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IGT
Latching current
Holding current
MIN
TYP
MAX
UNIT
VD=12V;IT=10mA;gate
open circuit
50
200
µA
IL
VD=12V;IGT=0.5mA;
RGK=1kΩ
2
6
mA
IH
VD=12V;IGT=0.5mA;
RGK=1kΩ
2
5
mA
VT
IT=1A
1.2
1.35
V
VGT
VD=12V;IT=10mA;
gate open circuit
VD=VDRM(max) ;IT=10mA ;
Tj=125°C; gate open circuit
0.5
0.8
V
0.1
mA
STATIC
Gate trigger current
On-state voltage
Gate trigger voltage
Off-state leakage current
0.2
0.3
ID,IR
VD=VDRM(max) ;VR=VRRM(m
ax) ;Tj=125°C;RGK=1kΩ
0.05
dVD/dt
VDM=67% VDRM(max);
Tj=125°C; exponential
waveform;RGK=1kΩ
25
V/µs
Gate controlled turn-on time
tgt
ITM=2A;VD=VDRM(max);
IG=10mA;dIG/dt=0.1A/µs
2
µs
Circuit commutated turn-off time
tq
VD=67% VDRM(max) ;
Tj=125°C;ITM=1.6A;VR=35V
;dITM/dt=30A/µs;
VD/dt=2V/µs;RGK=1kΩ
100
µs
DYNAMIC
Ciritical rate of rise of off-state
voltage
UTC
UNISONIC TECHNOLOGIES CO., LTD.
2
UTC BT169
SCR
Ptot / W
0.8
conduction
angle
degrees
30
60
90
120
180
0.7
0.6
0.5
0.4
ITSM / A
Tc(max) / C
form
factor
a
4
2.8
2.2
1.9
1.57
77
a=1.57
83
1.9
95
ITSM
T
time
Tj initial=25¢XC max
6
101
4
4
107
0.2
113
0.1
119
0
125
0.1
IT
8
89
2.2
2.8
0.3
0
10
0.2
0.3
0.4
IF(AV) / A
0.5
0.6
0.7
FIG.1 Maximum on-state dissipation, P tot , versus average
on-state current, I T(AV) , where a=form factor=I T(RMS) / IT(AV)
2
0
1
10
100
1000
Number of half cycles at 50Hz
FIG.4 Maximnum permissible non-repetitive peak on-state current
ITSM , versus number of cycles, for sinusoidal currents, f = 50Hz.
IT(RMS) / A
ITSM / A
2.0
1000
1.5
100
IT
1.0
ITSM
10
T
0.5
time
Tj initial=25¢XC max
1
10µs
100µs
1ms
10ms
T/s
FIG.2 Maximum permissible non-repetitive peak on-state current
ITSM ,versus pulse width tp,for sinusoidal currents, t p <=10ms.
IT(RMS) / A
1.0
0
0.01
0.8
1.0
10
surge duration / s
FIG.5 Maximum permissible repetitive rms on-state current I T(RMS) ,
versus surge duration, for sinusoidal currents, f= 50Hz; Tlead<=83¢XC
1.6
83¢XC
0.1
VGT(Tj)
VGT(25¢XC)
1.4
0.6
1.2
1.0
0.4
0.8
0.2
0
-50
0.6
0
50
100
Tlead / C
FIG.3 Maximum permissible rms current I
lead temperature, Tlead
UTC
150
T(RMS)
, versus
0.4
-50
0
50
100
150
Tj / C
FIG.6 Normalised gate trigger voltage V GT (Tj)/V GT( 25¢XC),
versus junction temperature Tj
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UTC BT169
3.0
SCR
IGT(Tj)
VGT(25¢XC)
IT / A
5
2.5
Tj=125¢XC - - Tj= 25¢XC
4
Vo=1.067V
Rs=0.187Ω
2.0
typ
max
3
1.5
2
1.0
0.5
1
0
-50
0
50
Tj / C
100
0
150
FIG.7 Normalised gate trigger current GT
I (Tj)/IGT(25¢XC),
versus junction temperature Tj
0
1.0
VT / V
1.5
2.0
FIG.10 Typical and maximum on-state characteristic.
Zth j-lead (K/W)
100
IL(Tj)
IL(25¢XC)
0.5
3.0
2.5
10
2.0
1
1.5
1.0
PD
0
-50
0
50
Tj / C
100
150
FIG.8 Normalised latching current L(I Tj)/IL(25¢XC),versus
junction temperature Tj, RGK= 1KΩ
3.0
tp
0.1
0.5
t
0.01
10us 0.1ms 1ms
10ms
tp / s
0.1s
1s
10s
FIG.11 Transient thermal impedance Zth j-lead, versus pulse width tp.
IH(Tj)
IH(25¢XC)
dVD/dt(V/us)
1000
2.5
2.0
100
RGK=1KΩ
1.5
1.0
10
0.5
0
1
-50
0
50
100
150
Tj / C
FIG.9 Normalised holding current HI (Tj)/IH(25¢XC),versus
junction temperature Tj, RGK=1KΩ
UTC
0
0
50
150
Tj / C
FIG.12 Typical, critical rate of rise of off-state voltage,
dVD/dt versus junction temperature Tj.
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