FXLA101 Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Features Description Bi-Directional Interface between Two Levels: from 1.1V to 3.6V Fully Configurable: Inputs and Outputs Track VCC Outputs Switch to 3-State if Either VCC is at GND Control Input (/OE) Referenced to VCCA Voltage ESD Protection Exceeds: - 8kV HBM (per JESD22-A114 & Mil Std 883e 3015.7) - 2kV CDM (per ESD STM 5.3) Non-Preferential Power-Up; Either VCC May Be Powered Up First Power-Off Protection Bus-Hold on Data Inputs Eliminates the Need for Pull-Up Resistors; Do Not Use Pull-Up Resistors on A or B Ports Packaged in MicroPak™ 6 (1.00mm x 1.45mm) Direction Control Not Necessary 100Mbps Throughput when Translating Between 1.8V and 2.5V The FXLA101 is a configurable dual-voltage supply translator for both uni-directional and bi-directional voltage translation between two logic levels. The device allows translation between voltages as high as 3.6V to as low as 1.1V. The A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional voltage translation over a variety of voltage levels: 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The device remains in three-state as long as either VCC=0V, allowing either VCC to be powered up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The /OE input, when HIGH, disables both the A and B ports by placing them in a 3-state condition. The /OE input is supplied by VCCA. The FXLA101 supports bi-directional translation without the need for a direction control pin. The two ports of the device have auto-direction sense capability. Either port may sense an input signal and transfer it as an output signal to the other port. Applications Cell Phones, PDAs, Digital Cameras, Portable GPS Ordering Information Part Number Top Mark FXLA101L6X XK FXLA101FHX XK Operating Temperature Range © 2009 Fairchild Semiconductor Corporation FXLA101 • Rev. 1.0.4 -40 to 85°C Package 6-Lead MicroPak™1.00mm x 1.45mm Package 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch Packing Method 5K Units Tape and Reel www.fairchildsemi.com FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing March 2012 Figure 1. Pin Configuration (Top Through View) Pin Definitions Pin # Name Description 1 VCCA A-Side Power Supply 2 GND Ground 3 A A Side Input or 3-State Output 4 B B Side Input or 3-State Output 5 /OE Output Enable Input 6 VCCB B Side Power supply © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Pin Configuration www.fairchildsemi.com 2 Figure 2. Functional Diagram Function Table Control Outputs /OE L Normal Operation H 3-State H = HIGH Logic Level L = LOW Logic Level © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Functional Diagram www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO (2) IIK IOK IOH/IOL ICC TSTG PD ESD Conditions Output Voltage DC Input Diode Current DC Output Diode Current Min. Max. VCCA -0.5 4.6 VCCB -0.5 4.6 I/O Ports A and B -0.5 4.6 Control Input (/OE) -0.5 4.6 Output 3-State -0.5 4.6 Output Active (An) -0.5 VCCA +0.5 Output Active (Bn) -0.5 VCCB +0.5 VI<0V -50 VO<0V -50 VO>VCC +50 DC Output Source/Sink Current -50 DC VCC or Ground Current (per Supply Pin) Storage Temperature Range -65 Power Dissipation Human Body Model, JESD22-A114 V V V mA mA +50 mA ±100 mA +150 °C 4.5 mW B Port I/O to GND 12 A Port I/O to GND 8 Charged Device Model, JESD22-C101 Unit kV 2 Notes: 1. IO absolute maximum ratings must be observed. 2. All unused inputs and input/outputs must be held at VCCi or GND. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Power Supply VIN Input Voltage TA Operating Temperature, Free Air dt/dV ΘJA Minimum Input Edge Rate Thermal Resistance © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 Conditions Operating VCCA or VCCB Ports A and B Control Input (/OE) VCCA/B = 1.1 to 3.6V Min. Max. Unit 1.1 3.6 V 0 3.6 V 0 VCCA V -40 +85 °C 10 ns/V Micropak-6 350 Micropak2-6 560 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Absolute Maximum Ratings °C/W www.fairchildsemi.com 4 FXL translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (/OE) is designed to track the VCCA supply. A pull-up resistor tying /OE to VCCA should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down. The size of the pull-up resistor is based upon the current-sinking capability of the device driving the /OE pin. The recommended power-down sequence is: 1. 2. 3. Pull-Up/Pull-Down Resistors Do not use pull-up or pull-down resistors. This device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. The current through these resistors may exceed the hold drive, II(HOLD) and/or II(OD) bus-hold currents. The bus-hold feature eliminates the need for extra resistors. The recommended power-up sequence is: 1. 2. 3. Apply power to the first VCC. Apply power to the second VCC. Drive the /OE input LOW to enable the device. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 Drive /OE input HIGH to disable the device. Remove power from either VCC. Remove power from other VCC. FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Power-Up/Power-Down Sequence www.fairchildsemi.com 5 TA=-40 to 85°C. Symbol Parameter Conditions Data Inputs An Control Pin /OE VIHA VCCB (V) Data Inputs Bn Min. 2.70 to 3.60 2.00 2.30 to 2.70 1.60 1.65 to 2.30 1.10 to 3.60 .65xVCCA 1.40 to 1.65 .65xVCCA 1.10 to 1.40 High-Level Input Voltage VIHB VCCA (V) Typ. .90xVCCA 2.70 to 3.60 2.00 2.30 to 2.70 1.60 1.10 to 3.60 1.65 to 2.30 .65xVCCB 1.40 to 1.65 .65xVCCB 1.10 to 1.40 .90xVCCB V .80 2.30 to 2.70 Data Inputs An Control Pin /OE VILB VOHA VOHB VOLA VOLB .35xVCCA 1.40 to 1.65 .35xVCCA Data Inputs Bn .80 2.30 to 2.70 .70 .35xVCCB 1.40 to 1.65 .35xVCCB 1.10 to 1.40 .10xVCCB High-Level Output Voltage(3) IOH=-4µA 1.10 to 3.60 1.10 to 3.60 VCCA - .40 IOH=-4µA 1.10 to 3.60 1.10 to 3.60 VCCB - .40 Low-Level Output Voltage(3) IOL=4µA 1.10 to 3.60 1.10 to 3.60 .4 IOL=4µA 1.10 to 3.60 1.10 to 3.60 .4 3.00 V .10xVCCA 2.70 to 3.60 1.10 to 3.60 1.65 to 2.30 VIN=0.80V II(HOLD) .70 1.65 to 2.30 1.10 to 3.60 1.10 to 1.40 Low-Level Input Voltage Units V 2.70 to 3.60 VILA Max. 3.00 75.0 V V VIN=2.00V 3.00 3.00 -75.0 VIN=0.7V 2.30 2.30 45.0 VIN=1.60V 2.30 2.30 -45.0 Bus-Hold Input Minimum VIN=0.57V Drive Current VIN=1.07V 1.65 1.65 25.0 1.65 1.65 -25.0 VIN=0.49V 1.40 1.40 11.0 VIN=0.91V 1.40 1.40 -11.0 VIN=0.11V 1.10 1.10 4.0 VIN=0.99V 1.10 1.10 -4.0 V µA FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing DC Electrical Characteristics Continued on following page… © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 6 TA=-40 to 85°C. Symbol II(ODH) II(ODL) II IOFF IOZ ICCA/B ICCZ Parameter Bus-Hold Input Overdrive High Current(4) Bus-Hold Input Overdrive Low (5) Current Input Leakage Current Power-Off Leakage Current 3-State Output Leakage Quiescent Supply Current(6, 7) ICCA Quiescent Supply Current ICCB Conditions VCCA (V) VCCB (V) Min. Max. 3.60 3.60 450.00 2.70 2.70 300.00 1.95 1.95 200.00 1.60 1.60 120.00 1.40 1.40 80.00 3.60 3.60 -450.00 2.70 2.70 -300.00 1.95 1.95 -200.00 1.60 1.60 -120.00 1.40 1.40 -80.00 1.10 to 3.60 3.60 ±1.0 An VO=0V to 3.6V 0 3.6 ±2.0 Bn VO=0V to 3.6V 3.60 0 ±2.0 An, Bn VO=0V or 3.6V, /OE=VIH 3.6 3.60 ±5.0 An VO=0V or 3.6V, /OE=GND 3.60 0 ±5.0 Bn VO=0V or 3.6V, /OE=GND 0 3.60 ±5.0 Data Inputs An, Bn Data Inputs An, Bn Control Inputs /OE, VI=VCCA or GND Units µA µA µA µA VI=VCCI or GND; IO=0, /OE=GND 1.10 to 3.60 1.10 to 3.60 10.0 µA VI=VCCI or GND; IO=0, /OE=VIH 1.10 to 3.60 1.10 to 3.60 10.0 µA VI=VCCB or GND; IO=0 B-to-A Direction, /OE=GND 0 VI=VCCA or GND; IO=0 A-to-B Direction 1.10 to 3.60 0 10.0 VI=VCCA or GND; IO=0, A-to-B Direction, /OE=GND 1.10 to 3.60 0 -10.0 VI=VCCB or GND; IO=0 B-to-A Direction 0 1.10 to 3.60 -10.0 µA µA 1.10 to 3.60 10.0 Notes: 3. This is the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic Output Electrical Characteristics table. 4. An external drive must source at least the specified current to switch LOW-to-HIGH. 5. An external drive must source at least the specified current to switch HIGH-to-LOW. 6. VCCI is the VCC associated with the input side. 7. Reflects current per supply, VCCA or VCCB. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 µA FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing DC Electrical Characteristics (Continued) www.fairchildsemi.com 7 A Port (An) Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C Symbol Parameter VCCA=3.0V to 3.6V Typ. Max. VCCA=2.3V to 2.7V Typ. VCCA=1.65V to 1.95V Max. Typ. Max VCCA=1.4V to 1.6V Typ. VCCA=1.1V to 1.3V Max. Typ. Units trise Output Rise Time A Port(9) 3.0 3.5 4.0 5.0 7.5 ns tfall Output Fall Time A (10) Port 3.0 3.5 4.0 5.0 7.5 ns IOHD Dynamic Output Current (9) High -11.4 -7.5 -4.7 -3.2 -1.7 mA IOLD Dynamic Output Current Low(10) +11.4 +7.5 +4.7 +3.2 +1.7 mA VCCB=1.1V to 1.3V Units B Port (Bn) Output Load: CL=15pF, RL ≥ MΩ (CI/O=5pF), TA=-40 to 85°C Symbol Parameter VCCB=3.0V to 3.6V Typ. Max. VCCB=2.3V to 2.7V Typ. VCCB=1.65V to 1.95V Max. Typ. Max VCCB=1.4V to 1.6V Typ. Max. Typ. trise Output Rise (9) Time B Port 3.0 3.5 4.0 5.0 7.5 ns tfall Output Fall Time B (10) Port 3.0 3.5 4.0 5.0 7.5 ns IOHD Dynamic Output Current (9) High -12.0 -7.9 -5.0 -3.4 -1.8 mA IOLD Dynamic Output Current Low(10) +12.0 +7.9 +5.0 +3.4 +1.8 mA FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Dynamic Output Electrical Characteristic Notes: 8. Dynamic output characteristics are guaranteed, but not tested. 9. See Figure 7. 10. See Figure 8. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 8 VCCA = 3.0V to 3.6V, TA=-40 to 85°C Symbol tPLH,tPHL Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.2 4.0 0.3 4.2 0.5 5.4 0.6 6.8 6.9 ns B to A 0.2 4.0 0.2 4.1 0.3 5.0 0.5 6.0 4.5 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (11) B Port 0.5 0.5 0.5 1.0 1.0 ns VCCB=1.1V to 1.3V Units VCCA = 2.3V to 2.7V, TA=-40 to 85°C Symbol tPLH,tPHL Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.2 4.1 0.4 4.5 0.5 5.6 0.8 6.9 7.0 ns B to A 0.3 4.2 0.4 4.5 0.5 5.5 0.5 6.5 4.8 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (11) B Port 0.5 0.5 0.5 1.0 1.0 ns VCCB=1.1V to 1.3V Units VCCA = 1.65V to 1.95V, TA=-40 to 85°C Symbol tPLH,tPHL Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.3 5.0 0.5 5.5 0.8 6.7 0.9 7.5 7.5 ns B to A 0.5 5.4 0.5 5.6 0.8 6.7 1.0 7.0 5.4 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (11) B Port 0.5 0.5 0.5 1.0 1.0 ns Note: 11. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10). Skew is guaranteed, but not tested. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing AC Characteristics www.fairchildsemi.com 9 VCCA = 1.4V to 1.6V, TA=-40 to 85°C Symbol tPLH,tPHL VCCB=3.0V to 3.6V Parameter VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.5 6.0 0.5 6.5 1.0 7.0 1.0 8.5 7.9 ns B to A 0.6 6.8 0.8 6.9 0.9 7.5 1.0 8.5 6.1 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (12) B Port 1.0 1.0 1.0 1.0 1.0 ns Units VCCA = 1.1V to 1.3V, TA=-40 to 85°C Symbol tPLH,tPHL tPZL,tPZH tSKEW VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Typ. Typ. Typ. Typ. Typ. A to B 4.6 4.8 5.4 6.2 9.2 ns B to A 6.8 7.0 7.4 7.8 9.1 ns 1.7 1.7 1.7 1.7 1.7 µs 1.0 1.0 1.0 1.0 1.0 ns Parameter /OE to A, /OE to B (12) A Port, B Port Note: 12. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10). Skew is guaranteed, but not tested. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing AC Characteristics (Continued) www.fairchildsemi.com 10 TA=-40 to 85°C. VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Min. Min. Min. Min. Typ. VCCA=3.00V to 3.60V 140 120 100 80 40 Mbps VCCA=2.30V to 2.70V 120 120 100 80 40 Mbps VCCA=1.65V to 1.95V 100 100 80 60 40 Mbps VCCA=1.40V to 1.60V 80 80 60 60 40 Mbps Typ. Typ. Typ. Typ. Typ. 40 40 40 40 40 VCCA VCCA=1.10V to 1.30V Units Mbps Notes: 13. Maximum data rate is guaranteed, but not tested. 14. Maximum data rate is specified in megabits per second (see Figure 9). It is equivalent to two times the F-toggle frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz. Capacitance Symbol CIN Parameter Conditions Input Capacitance Control Pin (/OE) An CI/O Input/Output Capacitance Cpd Power Dissipation Capacitance © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 Bn VCCA=VCCB=GND VCCA=VCCB=3.3V, /OE=VCCA VCCA=VCCB=3.3V, VI=0V or VCC, f=10MHz TA=+25°C Typical Units 3 pF 4 5 25 pF pF FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Maximum Data Rate www.fairchildsemi.com 11 hold.” “Static Mode” is when only the bus hold drives the channel. The bus hold can be over ridden in the event of a direction change. The strong driver allows the FXLA101 to quickly charge and discharge capacitive transmission lines during dynamic mode. Static mode conserves power, where ICC is typically < 5µA. The FXLA101 I/O architecture benefits the end user, beyond level translation, in the following three ways: Auto Direction without an external direction pin. Drive Capacitive Loads. Automatically shifts to a higher current drive mode only during “Dynamic Mode” or HL / LH transitions. Bus Hold Minimum Drive Current Lower Power Consumption. Automatically shifts to low-power mode during “Static Mode” (no transitions), lowering power consumption. Specifies the minimum amount of current the bus hold driver can source/sink. The bus hold minimum drive current (IIHOLD) is VCC dependent and guaranteed in the DC Electrical tables. The intent is to maintain a valid output state in a static mode, but that can be overridden when an input data transition occurs. The FXLA101 does not require a direction pin. Instead, the I/O architecture detects input transitions on both side and automatically transfers the data to the corresponding output. For example, for a given channel, if both A and B side are at a static LOW, the direction has been established as A B, and a LH transition occurs on the B port; the FXLA101 internal I/O architecture automatically changes direction from A B to B A. Bus Hold Input Overdrive Drive Current Specifies the minimum amount of current required (by an external device) to overdrive the bus hold in the event of a direction change. The bus hold overdrive (IIODH, IIODL) is VCC dependent and guaranteed in the DC Electrical tables. During HL / LH transitions, or “Dynamic Mode,” a strong output driver drives the output channel in parallel with a weak output driver. After a typical delay of approximately 10ns – 50ns, the strong driver is turned off, leaving the weak driver enabled for holding the logic state of the channel. This weak driver is called the “bus © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 Dynamic Output Current The strength of the output driver during LH / HL transitions is referenced on page 8, Dynamic Output Electrical Characteristics, IOHD, and IOLD. FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing I/O Architecture Benefit www.fairchildsemi.com 12 VCC TEST SIGNAL DUT C1 R1 Figure 3. Test Circuit Table 1. Table 2. AC Test Conditions Test Input Signal Output Enable Control tPLH, tPHL Data Pulses 0V tPZL 0V HIGH to LOW Switch tPZH VCCI HIGH to LOW Switch AC Load VCCO C1 R1 1.2V± 0.1V 15pF 1MΩ 1.5V± 0.1V 15pF 1MΩ 1.8V ± 0.15V 15pF 1MΩ 2.5V ± 0.2V 15pF 1MΩ 3.3V ± 0.3V 15pF 1MΩ DATA IN Vmi VCCI GND tpxx tpxx DATA OUT Vmo VCCO Figure 4. Waveform for Inverting and Non-Inverting Functions FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing Test Diagrams Notes: 15. Input tR = tF = 2.0ns, 10% to 90%. 16. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 13 Notes: 17. Input tR = tF = 2.0ns, 10% to 90%. 18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Figure 6. 3-State Output High Enable Time for Low Voltage Logic Notes: 19. Input tR = tF = 2.0ns, 10% to 90%. 20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Table 3. Test Measure Points Symbol VMI VDD (21) VCCI /2 VMO VCCo /2 VX 0.9 x VCCo VY 0.1 x VCCo FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing Figure 5. 3-State Output Low Enable Time for Low Voltage Logic Note: 21. VCCI=VCCA for control pin /OE or VMI=(VCCA/2). © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 14 VOH 80% x VCCO VOUT 20% x VCCO VOL Time IOHD ≈ (CL + CI / O ) × ΔVOUT (20% − 80%) • VCCO = (CL + CI / O ) × Δt t RISE Figure 7. Active Output Rise Time and Dynamic Output Current High VOH tfall 80% x VCCO VOUT 20% x VCCO VOL Time IOLD ≈ (CL + CI / O ) × ΔVOUT (80% − 20%) • VCCO = (CL + CI / O ) × Δt t FALL Figure 8. Active Output Fall Time and Dynamic Output Current Low tW VCCI DATA IN VCCI/2 VCCI/2 GND Maximum Data Rate, f = 1/tW Figure 9. Maximum Data Rate VCCO DATA OUTPUT Vmo FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing trise Vmo GND tskew tskew VCCO DATA OUTPUT Vmo Vmo GND Figure 10. Output Skew Time Note: 22. tSKEW = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 15 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW 0.075 X 45 CHAMFER DETAIL A PIN 1 TERMINAL (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing Physical Dimensions Figure 11. 6-Lead MicroPakTM 1.00mm x 1.45mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 www.fairchildsemi.com 16 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X Figure 12. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specification Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 Tape Section Cavity Number Leader (Start End) 125 (Typical) Cavity Status Cover Type Status Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 17 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing 18 www.fairchildsemi.com © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4