FXMAR2102 Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Features Description Bi-Directional Interface between Any Two Levels: 1.65V to 5.5V No Direction Control Needed The FXMAR2102 is a high-performance configurable dual-voltage-supply translator for bi-directional voltage translation over a wide range of input and output voltages levels. The FXMAR2102 also works in a pushpull environment. I2C-Bus® Isolation Internal 10K Pull-Up Resistors System GPIO Resources Not Required when OE Tied to VCCA A/B Port VOL = 175mV (Typical), VIL = 150mV, IOL = 6mA Open-Drain Inputs / Outputs Supports I2C Clock Stretching & Multi-Master Outputs Switch to 3-State if Either VCC is at GND ESD Protection Exceeds: - B Port: 8kV HBM ESD (vs. GND & vs. VCCB) - All Pins: 4kV HBM ESD (per JESD22-A114) - 2kV CDM (per JESD22-C101) Works in Push Pull Environment Accommodates Standard-Mode and Fast-Mode I2C-Bus Devices Fully Configurable: Inputs and Outputs Track VCC It is intended for use as a voltage translator between I2C-Bus® compliant masters and slaves. Internal 10KΩ pull-up resistors are provided. The device is designed so the A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional A/B-port voltage translation between any two levels from 1.65V to 5.5V. VCCA can equal VCCB from 1.65V to 5.5V. Either VCC can be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The two ports of the device have automatic directionsense capability. Either port may sense an input signal and transfer it as an output signal to the other port. Non-Preferential Power-Up; Either VCC Can Power-Up First Tolerant Output Enable: 5V Packaged in 8-Terminal Leadless MicroPak™ (1.6mm x 1.6mm) and Ultrathin MLP (1.2mm x 1.4mm) Ordering Information Part Number FXMAR2102L8X FXMAR2102UMX Operating Temperature Range Top Mark -40 to +85°C BU © 2010 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 0.0.7 Package 8-Lead MicroPak™, 1.6mm Wide 8-Lead Ultrathin MLP, 1.2mm x 1.4mm Packing Method 5000 Units on Tape and Reel www.fairchildsemi.com FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications October 2011 OE VCCB Dynamic Driver (with Time Out) 10K Internal Direction Generator & Ctrl VbiasB Vbias A B A VCCA 10K Internal Direction Generator & Ctrl Dynamic Driver (with Time Out) Figure 1. Block Diagram, 1 of 2 Channels © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Block Diagram www.fairchildsemi.com 2 VCCB B0 B1 OE 7 6 5 8 GND 4 1 2 3 V CCA A0 A1 Figure 2. MicroPak™ (Top-Through View) Figure 3. UMLP (Top-Through View) Pin Definitions Pin # Name Description 1 VCCA 2, 3 A0, A1 A-Side Inputs or 3-State Outputs 4 GND Ground 5 OE 6, 7 B1, B0 B-Side Inputs or 3-State Outputs 8 VCCB B-Side Power Supply A-Side Power Supply Output Enable Input Truth Table Control Outputs OE(1) LOW Logic Level 3-State HIGH Logic Level Normal Operation FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Pin Configuration Note: 1. If the OE pin is driven LOW, the FXMAR2102 is disabled and the A0, A1, B0, and B1 pins (including dynamic drivers) are forced into 3-state and all four 10K internal pull-up resisters are decoupled from their respective VCC. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 3 Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. –0.5 7.0 A Port –0.5 7.0 B Port –0.5 7.0 Control Input (OE) –0.5 7.0 An Outputs 3-State –0.5 7.0 Bn Outputs 3-State –0.5 7.0 An Outputs Active –0.5 VCCA + 0.5V Bn Outputs Active –0.5 VCCB + 0.5V VCCA, VCCB Supply Voltage VIN VO DC Input Voltage Output Voltage (2) IIK DC Input Diode Current IOK DC Output Diode Current IOH / IOL At VIN < 0V Units V V –50 At VO < 0V –50 At VO > VCC +50 DC Output Source/Sink Current –50 mA mA +50 mA ICC DC VCC or Ground Current per Supply Pin ±100 mA PD Power Dissipation 0.129 mW +150 °C TSTG ESD At 400KHz Storage Temperature Range Electrostatic Discharge Capability –65 Human Body Model, B-Port Pins 8 Human Body Model, All Pins (JESD22-A114) 4 Charged Device Mode, JESD22-C101 2 kV Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Absolute Maximum Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Units 1.65 5.50 V A-Port 0 5.5 B-Port 0 5.5 Control Input (OE) 0 VCCA VCCA, VCCB Power Supply Operating VIN Input Voltage(3) 8-Lead MicroPak™ 279 8-Lead Ultrathin MLP 302 JA Thermal Resistance TA Free Air Operating Temperature –40 V C°/W +85 °C Note: 3. All unused inputs and I/O pins must be held at VCCI or GND. VCCI is the VCC associated with the input side. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 4 Power-Up / Power-Down Sequencing FXM translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (OE) is designed to track the VCCA supply. A pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/-down. The size of the pull-down resistor is based upon the current-sinking capability of the device driving the OE pin. The recommended power-up sequence is: 1. Apply power to the first VCC. 2. Apply power to the second VCC. 3. Drive the OE input HIGH to enable the device. The recommended power-down sequence is: 1. Drive OE input LOW to disable the device. 2. Remove power from either VCC. 3. Remove power from the other VCC. Note: 4. Alternatively, the OE pin can be hardwired to VCCA to save GPIO pins. If OE is hardwired to VCCA, either VCC can be powered up or down first. Application Circuit FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Functional Description Figure 4. Application Circuit © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 5 Due to I2C’s open-drain topology, I2C masters and slaves are not push/pull drivers. Logic LOWs are “pulled down” (Isink), while logic HIGHs are “let go” (3-state). For example, when the master lets go of SCL (SCL always comes from the master), the rise time of SCL is largely determined by the RC time constant, where R = RPU and C = the bus capacitance. If the FXMAR2102 is attached to the master [on the A port] and there is a slave on the B port, the Npassgates act as a low-resistive short between both ports until either of the port’s VCC/2 thresholds are reached. After the RC time constant has reached the VCC/2 threshold of either port, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the LOW-to-HIGH (LH) direction, accelerating the rising edge. The resulting rise time resembles the scope shot in Figure 5. Effectively, two distinct slew rates appear in rise time. The first slew rate (slower) is the RC time constant of the bus. The second slew rate (much faster) is the dynamic driver accelerating the edge. The FXMAR2102 has open-drain I/Os and includes a total of four 10K・ internal pull-up resistors (RPU) on each of the four data I/O pins, as shown in Figure 4. If a pair of data I/O pins (An/Bn) is not used, both pins should disconnected, eliminating unwanted current flow through the internal RPUs. External RPUs can be added to the I/Os to reduce the total RPU value, depending on the total bus capacitance. The designer is free to lower the 2 total pull-up resistor value to meet the maximum I C 2 edge rate per the I C specification (UM10204 rev. 03, 2 June 19, 2007). For example, according to the I C specification, the maximum edge rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns. If the bus capacitance is approaching the maximum 400pF, a lower total RPU value helps keep the rise time below 300ns (Fast Mode). Likewise, the I2C specification also specifies a minimum Serial Clock Line High Time of 600ns during Fast Mode (400KHz). Lowering the total RPU also helps increase the SCL High Time. If the bus capacitance approaches 400pF, it may make sense to use the FXMA2102, which does not contain internal RPUs. Then calculate the ideal external RPU value. If both the A and B ports of the translator are HIGH, a high-impedance path exists between the A and B ports because both the Npassgates are turned off. If a master or slave device decides to pull SCL or SDA LOW, that device’s driver pulls down (Isink) SCL or SDA until the edge reaches the A or B port VCC/2 threshold. When either the A or B port threshold is reached, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the HIGH-to-LOW (HL) direction, accelerating the falling edge. Note: 2 5. Section 7.1 of the I C specification provides an excellent guideline for pull-up resistor sizing. Theory of Operation The FXMAR2102 is designed for high-performance level 2 shifting and buffer / repeating in an I C application. Figure 1 shows that each bi-directional channel contains two series-Npassgates and two dynamic drivers. This hybrid architecture is highly beneficial in an I2C application where auto-direction is a necessity. For example, during the following three I2C protocol events: Clock Stretching Slave’s ACK Bit (9th bit = 0) following a Master’s th Write Bit (8 bit = 0) Clock Synchronization and Multi-Master Arbitration the bus direction needs to change from master-to-slave to slave-to-master without the occurrence of an edge. If 2 there is an I C translator between the master and slave 2 in these examples, the I C translator must change direction when both A and B ports are LOW. The Npassgates can accomplish this task very efficiently because, when both A and B ports are LOW, the Npassgates act as a low-resistive short between the A and B ports. FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Application Information Figure 5. Waveform C: 600pF, Total RPU: 2.2K © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 6 The I2C specification mandates a maximum VIL (IOL of 3mA) of VCC • 0.3 and a maximum VOL of 0.4V. If there is a master on the A port of an I2C translator with a VCC 2 of 1.65V and a slave on the I C translator B port with a VCC of 3.3V, the maximum VIL of the master is (1.65V x 0.3) 495mV. The slave could legally transmit a valid logic LOW of 0.4V to the master. VOL: FXMAR2102 vs. Device B, VIL = 0.4V 0.65 0.6 VOL (V): 0.55 Device B VIL = 0.4V 0.5 FXMAR2102 VIL = 0.4V 0.45 0.4 0 2 4 6 IOL (mA): 8 10 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications If the I2C translator’s channel resistance is too high, the voltage drop across the translator could present a VIL to the master greater than 495mV. To complicate matters, the I2C specification states that 6mA of IOL is recommended for bus capacitances approaching 400pF. More IOL increases the voltage drop across the I2C translator. The I2C application benefits when I2C translators exhibit low VOL performance. Figure 6 depicts typical FXMAR2102 VOL performance vs. the competition, given a 0.4V VIL. VOL vs. IOL Figure 6. Device Comparison © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 7 The FXMAR2102 supports I2C-Bus® isolation for the following conditions: Bus isolation if bus clear VCC to GND If slave #2 is a camera that is suddenly removed from 2 the I C bus, resulting in VCCB transitioning from a valid VCC (1.65V – 5.5V) to 0V; the FXMAR2102 automatically forces SCL and SDA on both its A and B ports into 3-state. Once VCCB has reached 0V, full I2C communication between the master and slave #1 remains undisturbed. Bus isolation if either VCC goes to ground Bus Clear Because the I2C specification defines the minimum SCL frequency of DC, the SCL signal can be held LOW 2 forever; however. This condition shuts down the I C bus. 2 The I C specification refers to this condition as “Bus Clear.” In Figure 7; if slave #2 holds down SCL forever, the master and slave #1 are not able to communicate because the FXMAR2102 passes the SCL stuck-LOW condition from slave #2 to slave #1 and as the master. Figure 7. Bus Isolation © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications However, if the OE pin is pulled LOW (disabled), both ports (A and B) are 3-stated. This results in the FXMAR2102 isolating slave #2 from the master and slave #1, allowing full communication between the master and slave #1. 2 I C Bus Isolation www.fairchildsemi.com 8 TA = –40°C to +85°C. Symbol Parameter VIHA High Level Input Voltage A Conditions VCCA (V) VCCB (V) Min. Data Inputs An 1.65–5.50 1.65–5.50 VCCA – 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.7 x VCCA VCCB – 0.4 Typ. Max. Units V VIHB High Level Input Data Inputs Bn Voltage B 1.65–5.50 1.65–5.50 Data Inputs An 1.65–5.50 1.65–5.50 0.4 VILA Low Level Input Voltage A Control Input OE 1.65–5.50 1.65–5.50 0.3 x VCCA 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 ±1.0 µA 5.50 ±2.0 VILB Low Level Input Data Inputs Bn Voltage B VOL Low Level Output Voltage IL IOFF IOZ V VIL = 0.15V IOL = 6mA Input Leakage Current Control Input OE, VIN = VCCA or GND Power-Off Leakage Current An VIN or VO = 0V to 5.5V 0 Bn VIN or VO = 0V to 5.5V 5.50 0 ±2.0 An, Bn VO = 0V to 5.5V, OE = VIL 5.50 5.50 ±2.0 An VO = 0V to 5.5V, OE = Don’t Care 5.50 0 ±2.0 Bn VO = 0V to 5.5V, OE = Don’t Care 0 5.50 ±2.0 3-State Output Leakage(7) V µA µA ICCA/B Quiescent Supply Current(8,9) VIN = VCCI or Floating, IO = 0 1.65–5.50 1.65–5.50 5.0 µA ICCZ Quiescent Supply (8) Current VIN = VCCI or GND, IO = 0, OE = VIL 1.65–5.50 1.65–5.50 5.0 µA Quiescent Supply Current(7) VIN = 5.5V or GND, IO = 0, OE = Don’t Care, Bn to An 0 1.65–5.50 –2.0 ICCA 1.65–5.50 0 2.0 Quiescent Supply (7) Current VIN = 5.5V or GND, IO = 0, OE = Don’t Care, An to Bn 1.65–5.50 0 –2.0 ICCB 0 1.65–5.50 2.0 RPU Resistor Pull-up VCCA & VCCB Sides Value 1.65–5.50 1.65–5.50 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications DC Electrical Characteristics µA µA 10 Notes: 6. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical Characteristics. 7. “Don’t Care” indicates any valid logic level. 8. VCCI is the VCC associated with the input side. 9. Reflects current per supply, VCCA or VCCB. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 9 Output Rise / Fall Time(10) Output load: CL = 50pF, RPU = NC, push / pull driver, and TA = -40°C to +85°C. VCCO(11) Symbol trise tfall Parameter 4.5 to 5.5V 3.0 to 3.6V (12) Output Rise Time; A Port, B Port (13) Output Fall Time; A Port, B Port 2.3 to 2.7V 1.65 to 1.95V Units Typ. Typ. Typ. Typ. 3 4 5 7 ns 1 1 1 1 ns Notes: 10. Output rise and fall times guaranteed by design simulation and characterization; not production tested. 11. VCCO is the VCC associated with the output side. 12. See Figure 12. 13. See Figure 13. ( ) Maximum Data Rate 14 Output load: CL = 50pF, RPU = NC, push / pull driver, and TA = -40°C to +85°C. VCCB VCCA Direction 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V Units Minimums 4.5V to 5.5V 3.0V to 3.6V 2.3V to 2.7V 1.65V to 1.95V A to B 50 50 40 30 B to A 50 50 40 40 A to B 50 50 40 19 B to A 50 50 40 40 A to B 40 40 30 19 B to A 40 40 30 30 A to B 40 40 30 19 B to A 30 30 19 19 Note: 14. F-toggle guaranteed by design simulation; not production tested. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 MHz MHz MHz MHz FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Dynamic Output Electrical Characteristics www.fairchildsemi.com 10 Output Load: CL = 50pF, RPU = NC, push / pull driver, and TA = -40°C to +85°C. VCCB Symbol Parameter VCCA = 4.5 to 5.5V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(16) VCCA = 3.0 to 3.6V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(16) VCCA = 2.3 to 2.7V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(16) VCCA = 1.65 to 1.95V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(16) 1.65 to 1.95V Units 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V Typ. Max. Typ. Max. Typ. Max. Typ. Max. 1 1 2 2 4 3 3 4 4 5 1 2 3 2 6 3 4 5 5 10 1 3 4 2 5 3 5 6 6 9 1 4 5 5 7 3 7 7 7 15 3 65 5 0.50 5 100 9 1.50 4 65 6 0.50 7 105 10 1.00 5 65 7 0.50 8 105 12 1.00 10 65 9 0.50 15 105 16 1.00 2.0 1.5 2.0 2.0 4.0 4.0 100 5 0.5 5.0 3.0 4.0 4.0 8.0 8.0 115 10 1.5 1.5 1.5 2.0 2.0 5.0 6.0 100 4 0.5 3.0 4.0 4.0 4.0 9.0 9.0 115 8 1.0 1.5 2.0 2.0 2.0 6.0 8.0 100 5 0.5 3.0 6.0 5.0 5.0 11.0 11.0 115 10 1.0 1.5 3.0 3.0 3.0 7.0 10.0 100 9 0.5 3.0 9.0 5.0 5.0 15.0 14.0 115 15 1.0 2.5 1.5 2.0 2.0 5.0 4.0 100 65 0.5 5.0 3.0 5.0 5.0 10.0 8.0 115 110 1.5 2.5 2.0 2.0 2.0 5.0 4.5 100 65 0.5 5.0 4.0 5.0 5.0 10.0 9.0 115 110 1.0 2.0 3.0 2.0 2.0 6.0 5.0 100 65 0.5 4.0 6.0 5.0 5.0 12.0 10.0 115 115 1.0 1.0 5.0 3.0 3.0 9.0 9.0 100 12 0.5 3.0 10.0 6.0 6.0 18.0 18.0 115 25 1.0 4 1.0 5 4 11 6 75 75 0.5 7 2.0 8 8 15 14 115 115 1.5 4 1.0 3 3 11 6 75 75 0.5 7 2.0 7 7 14 14 115 115 1.0 5 1.5 3 3 14 6 75 75 0.5 8 3.0 7 7 28 14 115 115 1.0 5 5.0 3 3 14 9 75 75 0.5 10 10.0 7 7 23 16 115 115 1.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications AC Characteristics(15) ns ns ns ns ns ns Notes: 15. AC characteristics are guaranteed by design and characterization. 16. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 15). Skew is guaranteed; not production tested. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 11 TA = +25°C. Symbol Parameter Conditions Typical Units CIN Input Capacitance Control Pin (OE) VCCA = VCCB = GND 2.2 pF CI/O Input/Output Capacitance, An, Bn VCCA = VCCB = 5.0V, OE = GND 13 pF Figure 8. AC Test Circuit Table 1. Propagation Delay Table(17) Test Input Signal Output Enable Control tPLH, tPHL Data Pulses VCCA tPZL (OE to An, Bn) 0V LOW to HIGH Switch tPLZ (OE to An, Bn) 0V HIGH to LOW Switch Note: 17. For tPZL and tPLZ testing, an external 2.2K pull-up resister to VCCO is required in order to force the I/O pins high while OE is Low because when OE is low, the internal 10K RPUs are decoupled from their respective VCC’s. Table 2. AC Load Table VCCO CL RL 1.8 ±0.15V 50pF NC 2.5 ±0.2V 50pF NC 3.3 ±0.3V 50pF NC 5.0 ±0.5V 50pF NC © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Capacitance www.fairchildsemi.com 12 DATA IN VCCI Vmi tpxx OUTPUT CONTROL GND tpxx DATA OUT VCCO DATA OUT VY VOL Figure 10. 3-STATE Output Low Enable Time(18) Figure 9. Waveform for Inverting and Non-Inverting Functions(18) VCCA Vmi GND tPLZ DATA OUT GND tPZL Vmo OUTPUT CONTROL VCCA Vmi Vx VOL Symbol VCC (19) Vmi VCCI / 2 Vmo VCCO / 2 VX 0.5 x VCCO VY 0.1 x VCCO Figure 11. 3-STATE Output High Enable Time(18) Figure 12. Active Output Rise Time Figure 13.Active Output Fall Time VCCO DATA OUTPUT Vmo Vmo GND tperiod DATA IN VCCI / 2 VCCI / 2 tskew VCCI GND F-toggle rate, f = 1 / tperiod DATA OUTPUT FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Timing Diagrams tskew VCCO Vmo Vmo GND tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 14. F-Toggle Rate Figure 15. Output Skew Time Notes: 18. Input tR = tF = 2.0ns, 10% to 90% at VIN = 1.65V to 1.95V; Input tR = tF = 2.0ns, 10% to 90% at VIN = 2.3 to 2.7V; Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 3.6V only; Input tR = tF = 2.5ns, 10% to 90%, at VIN = 4.5V to 5.5 only. 19. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2). © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 13 0.10 2X C A 1.6 B 1.6 INDEX AREA 0.10 2X C TOP VIEW 0.55 MAX 0.05 0.05 0.00 DETAIL A 8X(0.09) C 8X 0.05 Recommended Landpattern C (0.20) 1.0 2 1 4 (0.1) C 8 0.35 0.25 3X(0.2) 0.35 0.25 0.5 3 4 7 6 5 (0.15) 0.15 8X 0.25 0.10 0.05 C A B C 0.35 0.25 DETAIL A PIN #1 TERMINAL SCALE: 2X BOTTOM VIEW Notes: 1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y.14M-1994 4. PIN 1 FLAG, END OF PACKAGE OFFSET 5. DRAWING FILE NAME: MKT-MAC08AREV4 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Physical Dimensions MAC08AREV4 Figure 16. 8-Lead MicroPak™, 1.6mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape & Reel Format for MicroPak™ Always visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 14 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications Physical Dimensions 0.10 C 1.40 2X A 1.45 0.725 0.40 B 1.25 0.45 1.20 0.625 (7X) 0.35 0.10 C TOP VIEW 0.25 (8X) 2X RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C (0.15) 0.05 C 0.025 0.00 SEATING C PLANE 0.10 DETAIL : A SCALE : 2X 0.40 DETAIL A PIN#1 IDENT NOTES: 0.35 0.25 (7X) 4 A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. DRAWING FILENAME: MKT-UMLP08Arev2. 5 1 8 6 (0.20) BOTTOM VIEW 45° 0.20 SIDE VIEW 2 0.10 0.30 0.25 (8X) 0.15 0.10 0.05 C A B C PACKAGE EDGE LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 SCALE : 2X Figure 17. 8-Lead Ultrathin MLP, 1.2mm x 1.4mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 15 FXMAR2102 — Dual-Supply, 2-Bit Voltage Translator / Isolator for I2C Applications © 2011 Fairchild Semiconductor Corporation FXMAR2102 • Rev. 1.0.0 www.fairchildsemi.com 16