FREESCALE MC68HC08LJ12CFB

Freescale Semiconductor, Inc.
Addendum
HC908LJ12AD/D
Rev. 0, 6/2003
Freescale Semiconductor, Inc...
Addendum to
MC68HC908LJ12
Technical Data
This addendum provides information to the following MCU devices:
•
MC68HLC908LJ12 (see page 1)
•
MC68HC08LJ12 (see page 9)
The entire MC68HC908LJ12 Technical Data, Rev. 2 (Motorola document
number MC68HC908LJ12/D) applies to the these two devices, with exceptions
outlined in this addendum.
Amendments to MC68HC908LJ12/D, Rev. 2, are documented on page 13.
MC68HLC908LJ12
The MC68HLC908LJ12 is a low-voltage version of the MC68HC908LJ12, with
an operating voltage range of 2.4 to 3.3V.
FLASH Memory
The FLASH memory can be read at operating voltages from 2.4 to 3.3V.
Program or erase operations require a minimum operating voltage of 2.7V.
Low-Voltage Inhibit
(LVI)
The LVI module is not designed for the MC68HLC908LJ12. After an MCU
reset, the LVI module is disabled (LVIPWRD = 1 in CONFIG1). The LVIPWRD
bit should be left as logic 1 (the default setting).
Electrical
Specifications
Electrical specifications for the MC68HLC908LJ12 device are given in the
following tables.
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HC908LJ12AD/D
Functional Operating
Range
Table 1. Operating Range
Characteristic
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Operating temperature range
Symbol
Value
Unit
TA
– 40 to +85
°C
Operating voltage range
VDD
2.4 to 2.7
2.7 to 3.3
V
Maximum internal operating
frequency
fOP
2
4
MHz
Operating voltage for FLASH
memory program and erase
operations
VDD
2.7 to 3.3
V
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics (2.4 to 2.7V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –1.0 mA)
All ports
VOH
VDD –0.4
—
—
V
Output low voltage
(ILOAD = 0.8mA) All ports
(ILOAD = 4.0 mA) PTB2–PTB5
(ILOAD = 10.0 mA) PTB0/TxD–PTB1
VOL
—
—
0.4
V
Input high voltage
All ports, RST, IRQ, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, RST, IRQ, OSC1
VIL
VSS
—
0.3 × VDD
V
IDD
—
—
—
—
—
—
—
—
5.2
3.8
2.8
2.3
mA
mA
mA
mA
—
—
—
—
—
—
—
—
200
27
15
1
µA
µA
µA
µA
—
—
± 10
µA
VDD supply current
Run(3), fOP = 2 MHz
with all modules on
with ADC on
with ADC off
Wait(4), fOP = 2 MHz (all modules off)
Stop, fOP = 8 kHz
(5)
25°C (with OSC, RTC, LCD(6), LVI on)
25°C (with OSC, RTC, LCD(6) on)
25°C (with OSC, RTC on)
25°C (all modules off)
Digital I/O ports Hi-Z leakage current
All ports, RST
IIL
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
MC68HLC908LJ12
Table 2. DC Electrical Characteristics (2.4 to 2.7V) (Continued)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COUT
CIN
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
0
—
100
mV
POR rise-time ramp rate(8)
RPOR
0.02
—
—
V/ms
VHI
1.5 × VDD
—
2 × VDD
V
RPU1
RPU2
—
—
25
27
—
—
kΩ
kΩ
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Input current
IRQ
Monitor mode entry voltage (at IRQ pin)
Pullup resistors(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
1. VDD = 2.4 to 2.7 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD.
4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. RPU1 and RPU2 are measured at VDD = 2.6V.
Table 3. DC Electrical Characteristics (2.7 to 3.3V)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage (ILOAD = –1.0 mA)
All ports
VOH
VDD –0.4
—
—
V
Output low voltage
(ILOAD = 0.8mA) All ports
(ILOAD = 4.0 mA) PTB2–PTB5
(ILOAD = 10.0 mA) PTB0/TxD–PTB1
VOL
—
—
0.4
V
Input high voltage
All ports, RST, IRQ, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
All ports, RST, IRQ, OSC1
VIL
VSS
—
0.3 × VDD
V
Addendum to MC68HC908LJ12 Technical Data
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Table 3. DC Electrical Characteristics (2.7 to 3.3V) (Continued)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
IDD
—
—
—
—
—
—
—
—
8
6
5
3.5
mA
mA
mA
mA
—
—
—
—
—
—
—
—
280
38
15
1
µA
µA
µA
µA
VDD supply current
Run(3), fOP = 4 MHz
with all modules on
with ADC on
with ADC off
Wait(4), fOP = 4 MHz (all modules off)
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Stop, fOP = 8 kHz
(5)
25°C (with OSC, RTC, LCD(6), LVI on)
25°C (with OSC, RTC, LCD(6) on)
25°C (with OSC, RTC on)
25°C (all modules off)
Digital I/O ports Hi-Z leakage current
All ports, RST
IIL
—
—
± 10
µA
Input current
IRQ
IIN
—
—
±1
µA
Capacitance
Ports (as input or output)
COUT
CIN
—
—
—
—
12
8
pF
POR re-arm voltage(7)
VPOR
0
—
100
mV
POR rise-time ramp rate(8)
RPOR
0.02
—
—
V/ms
VHI
1.5 × VDD
—
2 × VDD
V
RPU1
RPU2
—
—
25
27
—
—
kΩ
kΩ
Monitor mode entry voltage (at IRQ pin)
Pullup resistors(9)
PTA0–PTA3, PTD4–PTD7 configured as KBI0–KBI7
RST, IRQ
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD.
4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for low current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. RPU1 and RPU2 are measured at VDD = 3V.
Addendum to MC68HC908LJ12 Technical Data
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MC68HLC908LJ12
Oscillator
Characteristics
Table 4. Oscillator Specifications (2.4 to 2.7V)
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Characteristic
Symbol
Min
Typ
Max
Unit
Internal oscillator clock frequency
fICLK
—
See Figure 1.
—
Hz
External reference clock to OSC1(1)
fOSC
dc
—
8M
Hz
Crystal reference frequency(2)
fXCLK
32.768k
4.9152M
Hz
Crystal load capacitance(3)
CL
—
—
—
Crystal fixed capacitance
C1
—
2 × CL (25p)
—
F
Crystal tuning capacitance
C2
—
2 × CL (25p)
—
F
Feedback bias resistor
RB
—
10M
—
Ω
Series resistor(4)
RS
—
100k
—
Ω
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Table 5. Oscillator Specifications (2.7 to 3.3V)
Characteristic
Symbol
Min
Typ
Max
Unit
Internal oscillator clock frequency
fICLK
—
See Figure 1.
—
Hz
External reference clock to OSC1(1)
fOSC
dc
—
16M
Hz
Crystal reference frequency(2)
fXCLK
32.768k
4.9152M
Hz
Crystal load capacitance(3)
CL
—
—
—
Crystal fixed capacitance
C1
—
2 × CL (25p)
—
F
Crystal tuning capacitance
C2
—
2 × CL (25p)
—
F
Feedback bias resistor
RB
—
10M
—
Ω
Series resistor(4)
RS
—
100k
—
Ω
1. No more than 10% duty cycle deviation from 50%.
2. Fundamental mode crystals only.
3. Consult crystal manufacturer’s data.
4. Not Required for high frequency crystals.
Addendum to MC68HC908LJ12 Technical Data
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Internal OSC frequency, fICLK (kHz)
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70
–40°C
60
50
+25°C
40
+85°C
30
20
10
0
2
3
4
Supply Voltage, VDD (V)
5
6
Figure 1. Typical Internal Oscillator Frequency
ADC Electrical
Characteristics
Table 6. ADC Electrical Characteristics (2.4 to 3.3V)
Characteristic
Symbol
VDDA
Min
Max
Unit
2.4
3.3
V
Input range
VADIN
0
VDDA
V
VADIN ≤ VDDA
Resolution
BAD
10
10
bits
1,024 counts
Absolute accuracy
AAD
ADC internal clock
fADIC
32 k
2M
Hz
Includes quantization.
± 1 ADC count = ± 0.5 LSB
tADIC = 1/fADIC
Conversion range
RAD
VREFL
VREFH
V
VREFH
—
VDDA + 0.1
V
VREFL
VSSA – 0.1
—
V
Conversion time
tADC
16
17
Sample time
tADS
5
—
Monotonically
MAD
Zero input reading
ZADI
000
001
HEX
VADIN = VREFL
Full-scale reading
FADI
3FC
3FF
HEX
VADIN = VREFH
Input capacitance
CADI
—
20
pF
Not tested.
Input impedance
RADI
20M
—
Ω
Measured at 5V
VREFH/VREFL
IVREF
—
1.6
mA
Supply voltage
ADC voltage
reference high
ADC voltage
reference low
See Figure 2 and Figure 3.
Notes
VSSA is tied to VSS internally.
tADIC
cycles
tADIC
cycles
Guaranteed
Not tested.
Addendum to MC68HC908LJ12 Technical Data
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35
35
30
30
25
25
ADC Count Error
ADC Count Error
HC908LJ12AD/D
MC68HLC908LJ12
20
15
10
0
0
-5
0.5
1.0
1.5
2.0
2.5
0.0
3.0
0.5
1.0
1.5
2.0
ADC Input Voltage
ADC Input Voltage
(a) VDD = 2.4V at –40°C
(d) VDD = 2.7V at –40°C
35
35
30
30
25
25
ADC Count Error
ADC Count Error
10
5
0.0
20
15
10
5
2.5
3.0
2.5
3.0
2.5
3.0
20
15
10
5
0
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
0.0
3.0
0.5
1.0
1.5
2.0
ADC Input Voltage
ADC Input Voltage
(b) VDD = 2.4V at 25°C
(e) VDD = 2.7V at 25°C
35
35
30
30
25
25
ADC Count Error
ADC Count Error
15
5
-5
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20
20
15
10
5
0
20
15
10
5
0
-5
-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
ADC Input Voltage
ADC Input Voltage
(c) VDD = 2.4V at 85°C
(f) VDD = 2.7V at 85°C
Note: ADC performance increases with increase in operating voltage and temperature.
Figure 2. Typical ADC Accuracy (2.4V and 2.7V)
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35
30
ADC Count Error
25
20
15
10
5
0
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-5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
VDD = 3.0 to 3.3V, at –40 to 85°C
Figure 3. Typical ADC Accuracy (3V and 3.3V)
Memory
Characteristics
At an operating voltage of less than 2.7 V, the FLASH memory can only be
read. Program and erase are achieved at an operating voltage of 2.7 to 3.3V.
The program and erase parameters in the MC68HC908LJ12 Technical Data
are for VDD = 2.7 to 3.3V only.
MC68HLC908LJ12
Order Numbers
Table 7 shows the ordering numbers for the MC68HLC908LJ12.
Table 7. MC68HLC908LJ12 Order Numbers
Package
Operating
Temperature Range
MC68HLC98LJ12CFB
52-pin LQFP
–40 °C to +85 °C
MC68HLC98LJ12CPB
64-pin LQFP
–40 °C to +85 °C
MC68HLC98LJ12CFU
64-pin QFP
–40 °C to +85 °C
MC Order Number (1)
1. The missing “0” in “908” is intentional.
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HC908LJ12AD/D
MC68HC08LJ12
MC68HC08LJ12
The MC68HC08LJ12 is the ROM part equivalent to the MC68HC908LJ12.
Table 8. Summary of MC68HC08LJ12 and MC68HC908LJ12 Differences
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Operating voltages
MC68HC08LJ12
MC68HC908LJ12
—
5.0V ± 10%
3.3V ± 10%
5.0V ± 10%
Memory ($C000–$EFFF)
12,288 bytes ROM
12,288 bytes FLASH
User vectors ($FFD0–$FFFF)
48 bytes ROM
48 bytes FLASH
Registers at $FE08 and $FF09
Not used;
locations are reserved.
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Monitor ROM
($FC00–$FDFF and $FE10–$FFCF)
Used for testing purposes only.
Used for testing and FLASH
programming/erasing.
Available packages
52-pin LQFP
64-pin LQFP
64-pin QFP
52-pin LQFP
64-pin LQFP
64-pin QFP
MCU Block Diagram
Figure 4 shows the block diagram of the MC68HC08LJ12.
Memory Map
The MC68HC08LJ128 has 12,288 bytes of user ROM from $C000 to $EFFF,
and 48 bytes of user ROM vectors from $FFD0 to $FFFF. On the
MC68HC908LJ12 these memory locations are FLASH memory.
Figure 5 shows the memory map of the MC68HC08LJ12.
Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08LJ12.
On the MC68HC908LJ12, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10–$FFCF and $FC00–$FDFF) on
the MC68HC08LJ12 is for device testing only.
Addendum to MC68HC908LJ12 Technical Data
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HC908LJ12AD/D
INTERNAL BUS
PORTA
CONTROL AND STATUS REGISTERS — 96 BYTES
KEYBOARD INTERRUPT
MODULE
PORTB
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7/ADC3
PTA6/ADC2
PTA5/ADC1
PTA4/ADC0
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
PTB7/ADC5
PTB6/ADC4
PTB5/T2CH1‡
PTB4/T2CH0‡
PTB3/T1CH1‡
PTB2/T1CH0‡
PTB1/RxD†
PTB0/TxD†
PORTC
CPU
REGISTERS
DDRA
M68HC08 CPU
PTC7/FP26
PTC6/FP25
PTC5/FP24
PTC4/FP23
PTC3/FP22
PTC2/FP21
PTC1/FP20
PTC0/FP19
10-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
USER ROM — 12,288 BYTES
2-CHANNEL TIMER INTERFACE
MODULE 1
2-CHANNEL TIMER INTERFACE
MODULE 2
USER ROM VECTOR — 48 BYTES
CLOCK GENERATOR MODULE
OSC1
CGMXFC
32.768-kHz OSCILLATOR
SERIAL COMMUNICATIONS
INTERFACE MODULE
(WITH INFRARED
ENCODER/DECODER)
PHASE-LOCKED LOOP
REAL TIME CLOCK
MODULE
* RST
SYSTEM INTEGRATION
MODULE
* IRQ
EXTERNAL INTERRUPT
MODULE
DDRC
OSC2
DDRB
MONITOR ROM — 960 BYTES
LIQUID CRYSTAL DISPLAY
DRIVER MODULE
#
FP1–FP18
BP0–BP2
COMPUTER OPERATING
PROPERLY MODULE
LOW-VOLTAGE INHIBIT
MODULE
VDDA
VDD
POWER
VSS
VREFH
VREFL
SERIAL PERIPHERAL
INTERFACE MODULE
PORTD
POWER-ON RESET
MODULE
FP0/BP3
DDRD
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USER RAM — 512 BYTES
ADC REFERENCE
* Pin contains integrated pullup device.
** Pin contains integrated pullup device if configured as KBI.
† High current sink pin, 15mA.
‡
High current sink pin, 8mA.
# Pins available on 64-pin packages only.
Shaded blocks indicate differences to MC68HC908LJ12
Figure 4. MC68HC08LJ12 Block Diagram
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PTD7/KBI7**
PTD6/KBI6**
PTD5/KBI5**
PTD4/KBI4**
PTD3/SPSCK
PTD2/MOSI
PTD1/MISO
PTD0/SS
#
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HC908LJ12AD/D
MC68HC08LJ12
$0000
↓
$005F
I/O Registers
96 Bytes
$0060
↓
$025F
RAM
512 Bytes
$0260
↓
$BFFF
Unimplemented
48,544 Bytes
$C000
↓
$EFFF
ROM
12,288 Bytes
$F000
↓
$FBFF
Unimplemented
3,072 Bytes
$FC00
↓
$FDFF
Monitor ROM 1
512 Bytes
$FE00
SIM Break Status Register (SBSR)
$FE01
SIM Reset Status Register (SRSR)
$FE02
Reserved
$FE03
SIM Break Flag Control Register (SBFCR)
$FE04
Interrupt Status Register 1 (INT1)
$FE05
Interrupt Status Register 2 (INT2)
$FE06
Interrupt Status Register 3 (INT3)
$FE07
Reserved
$FE08
Reserved
$FE09
Reserved
$FE0A
Reserved
$FE0B
Reserved
$FE0C
Break Address Register High (BRKH)
$FE0D
Break Address Register Low (BRKL)
$FE0E
Break Status and Control Register (BRKSCR)
$FE0F
LVI Status Register (LVISR)
$FE10
↓
$FFCF
Monitor ROM 2
448 Bytes
$FFD0
↓
$FFFF
ROM Vectors
48 Bytes
Figure 5. MC68HC08LJ12 Memory Map
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HC908LJ12AD/D
Electrical
Specifications
Electrical specifications for the MC68HC908LJ12 apply to the MC68HC08LJ12
except for the parameters indicated below.
Functional Operating
Range
Table 9. Operating Range
Characteristic
Operating temperature range
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Operating voltage range
Symbol
Value
Unit
TA
– 40 to +85
°C
VDD
5.0V ± 10%
V
RAM Memory
Characteristics
Table 10. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min.
Max.
Unit
VRDR
1.3
—
V
Notes:
Since MC68HC08LJ12 is a ROM device, FLASH memory electrical characteristics do not apply.
MC68HC08LJ12
Order Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Table 11. MC68HC08LJ12 Order Numbers
Package
Operating
Temperature Range
MC68HC08LJ12CFB
52-pin LQFP
–40 °C to +85 °C
MC68HC08LJ12CPB
64-pin LQFP
–40 °C to +85 °C
MC68HC08LJ12CFU
64-pin QFP
–40 °C to +85 °C
MC Order Number
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AMENDMENTS TO MC68HC908LJ12/D, REV. 2
AMENDMENTS TO MC68HC908LJ12/D, REV. 2
5.0V DC Electrical
Characteristics
Pages 394 and 395, Table 23-4 5.0V DC Electrical Characteristics —
Delete LVI typical values and correct note 6.
From:
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Characteristic
Symbol
Min
Typ
Max
Unit
Low-voltage inhibit, trip falling voltage
VTRIPF
4.00
4.32
4.70
V
Low-voltage inhibit, trip rising voltage
VTRIPR
4.00
4.32
4.70
V
Symbol
Min
Typ
Max
Unit
Low-voltage inhibit, trip falling voltage
VTRIPF
4.00
—
4.70
V
Low-voltage inhibit, trip rising voltage
VTRIPR
4.00
—
4.70
V
Notes:
6. LCD driver configured for high current mode.
To:
Characteristic
Notes:
6. LCD driver configured for low current mode.
3.3V DC Electrical
Characteristics
Pages 396 and 397, Table 23-5 3.3V DC Electrical Characteristics —
Delete LVI typical values and correct note 6.
From:
Characteristic
Symbol
Min
Typ
Max
Unit
Low-voltage inhibit, trip falling voltage
VTRIPF
2.40
2.57
2.88
V
Low-voltage inhibit, trip rising voltage
VTRIPR
2.46
2.63
2.97
V
Symbol
Min
Typ
Max
Unit
Low-voltage inhibit, trip falling voltage
VTRIPF
2.40
—
2.88
V
Low-voltage inhibit, trip rising voltage
VTRIPR
2.46
—
2.97
V
Notes:
6. LCD driver configured for high current mode.
To:
Characteristic
Notes:
6. LCD driver configured for low current mode.
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Oscillator
Characteristics
Page 398, Table 23-8 5.0V Oscillator Specifications and Table 23-9 3.3V
Oscillator Specifications — Replace Internal oscillator clock frequency
values.
From:
Characteristic
Freescale Semiconductor, Inc...
Internal oscillator clock frequency
Characteristic
Internal oscillator clock frequency
To:
Symbol
Min
Typ
Max
Unit
fICLK
46k
47k
48k
Hz
Symbol
Min
Typ
Max
Unit
fICLK
42.8k
43.4k
44k
Hz
See Figure 1 . Typical Internal Oscillator Frequency on page 6 of this
document.
— END —
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— END —
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