FREESCALE MC9S08SV16

Freescale Semiconductor
Data Sheet: Technical Data
MC9S08SV16 Series
Covers: MC9S08SV16 and
MC9S08SV8
Features:
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 2.7 V to 5.5 V across temperature
range of –40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Up to 16 KB flash read/program/erase over full
operating voltage and temperature
– Up to 1024-byte random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Allows clocks to remain enabled to specific peripherals
in stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage;
supporting bus frequencies up to 20 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints)
Document Number: MC9S08SV16
Rev. 2, 7/2009
MC9S08SV16
32-Pin LQFP
873A-03
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes
• Peripherals
– IPC — Interrupt priority controller to provide hardware
based nested interrupt mechanism
– ADC — 12-channel, 10-bit resolution; 2.5 μs
conversion time; automatic compare function;
1.7 mV/°C temperature sensor; internal bandgap
reference channel; operation in stop; optional hardware
trigger; fully functional from 2.7 V to 5.5 V
– TPM — One 6-channel and one 2-channel
timer/pulse-width modulators (TPM) modules;
selectable input capture, output compare, or buffered
edge- or center-aligned PWM on each channel
– MTIM16 — One 16-bit modulo timer
– SCI — One serial communications interface module
with optional 13-bit break; LIN extensions
– SPI — One serial peripheral interface module in 8-bit
data length mode with a receiving data buffer hardware
match function
– IIC — Inter-integrated circuit bus module capable of
operation up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address;
interrupt-driven byte-by-byte data transfer; broadcast
mode; 10-bit addressing
– ACMP — Analog comparator with option to compare to
internal reference
– RTC — Real time counter
– KBI— 8-pin keyboard interrupt module with software
selectable polarity on edge or edge/level modes
• Input/Output
– 30 GPIOs including one output-only pin and one
input-only pin
• Package Options
– 32-pin SDIP
– 32-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
32-Pin SDIP
1376-02
Table of Contents
1
2
3
4
5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . 9
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 9
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 10
5.5 ESD Protection and Latch-Up Immunity. . . . . . . 11
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Supply Current Characteristics. . . . . . . . . . . . . . 18
5.8 External Oscillator (XOSC) and ICS
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 23
6
7
5.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 23
5.9.2 TPM Module Timing. . . . . . . . . . . . . . . . . 24
5.9.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . 25
5.10 Analog Comparator (ACMP) Electricals. . . . . . . 27
5.11 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . 28
5.12 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . 30
5.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . 31
5.13.1Radiated Emissions . . . . . . . . . . . . . . . . . 31
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . 33
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
4/2/2009
Initial public release.
2
7/20/2009
Updated Section 5.13, “EMC Performance.”
Corrected Table 1.
Corrected default trim value to 31.25 kHz.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08SV16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08SV16 Series Data Sheet, Rev. 2
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08SV16 series MCU.
PTA0/KBIP0/ADP0
16-BIT MODULO TIMER
HCS08 CORE
TCLK
PTA1/KBIP1/ADP1
(MTIM16)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-PIN KEYBOARD
INTERRUPT (KBI)
KBI[7:0]
2-CH TIMER/PWM
TPM2CH[1:0]
PORT A
PTA2/KBIP2/ADP2
BDC
CPU
PTA5/IRQ/TCLK/RESET
PTA6/TPM2CH0
RESET
PTA7/TPM2CH1
1 kHz OSC
LVD
INTERRUPT PRIORITY
CONTROLLER (IPC)
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
ON-CHIP ICE AND
DEBUG MODUE (DBG)
SERIAL COMMUNICATION
INTERFACE (SCI)
TxD
RxD
USER FLASH
MC9S08SV16 = 16,384 BYTES
MC9S08SV8 = 8,192 BYTES
6-CH TIMER/PWM
PTB2/KBIP6/ADP6
PORT B
IRQ
PTA4/ACMPO/BKGD/MS
MODULE (TPM2)
IRQ
COP
PTA3/KBIP3/ADP3
PTB4/TPM1CH0
PTB5/TPM1CH1
TPM1CH[5:0]
MODULE (TPM1)
USER RAM
MC9S08SV16 = 1,024 BYTES
MC9S08SV8 = 768 BYTES
PTB3/KBIP7/ADP7
PTB6/XTAL
PTB7/EXTAL
REAL-TIME COUNTER
(RTC)
EXTAL
XTAL
EXTERNAL OSCILLATOR
SOURCE (XOSC)
ALALOG COMPARATOR
(ACMP)
ACMP+
ACMP–
ACMPO
8-BIT SERIAL PERIPHERAL
MOSI
MISO
SPSCK
SS
INTERFACE MODULE(SPI)
VDD
VSS
PTC0/ADP8
PTC1/ADP9
PTC2/ADP10/ACMP+
PORT C
40 MHz INTERNAL CLOCK
SOURCE (ICS)
PTC3/ADP11/ACMP–
PTC4/SS
PTC5/SPSCK
VOLTAGE REGULATOR
PTC6/MOSI
PTC7/MISO
VREFH
VREFL
VDDA
VSSA
12-CH 10-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
ADP[11:0]
PTD0/SCL
INTER-INTEGRATED
CIRCUIT (IIC)
SCL
SDA
NOTE
1. PTA4 is output only when used as port pin.
2. PTA5 is input only when used as port pin.
PORT D
PTD1/SDA
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4/TPM1CH4
PTD5/TPM1CH5
Figure 1. MC9S08SV16 Series Block Diagram
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
3
System Clock Distribution
2
System Clock Distribution
MC9S08SV16 series use ICS module as clock sources. The ICS module can use internal or external clock
source as reference to provide up to 40 MHz CPU clock. The output of ICS module includes,
• OSCOUT— XOSC output provides EXTAL reference clock to ADC and RTC.
• ICSIRCLK — ICS internal clock reference provides clock source of RTC.
• ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides double of the
fixed lock signal to TPMs and MTIM16.
• ICSOUT — ICS CPU clock provides double of bus clock which is basic clock reference of
peripherals.
• ICSLCLK — Alternate BDC clock provides debug signal to BDC module.
The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock
source to TPMs and MTIM16. The on-chip 1 kHz clock can provide clock source of RTC and COP
modules.
TCLK
1 kHz
RTC
COP
TPM2
TPM1
MTIM16
ADC
OSCOUT
ICSIRCLK
ICSFFCLK
÷2
ICSOUT
÷2
FIXED CLOCK (XCLK)
ICS
BUS CLOCK
ICSLCLK
XOSC
CPU
SCI
BDC
FLASH
RAM
SPI
IIC
IPC
EXTAL XTAL
Figure 2. System Clock Distribution Diagram
MC9S08SV16 Series Data Sheet, Rev. 2
4
Freescale Semiconductor
Pin Assignments
3
Pin Assignments
This section shows the pin assignments for the MC9S08SV16 series devices.
PTC5/SPSCK
PTC4/SS
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA4/ACMPO/BKGD/MS
PTD0/SCL
PTD1/SDA
VDD
VSS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPM1CH1
PTD3/TPM1CH3
PTB4/TPM1CH0
PTC3/ADP11/ACMP–
PTC2/ADP10/ACMP+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PTC6/MOSI
PTC7/MISO
PTA0/KBIP0/ADP0
PTD5/TPM1CH5
PTA1/KBIP1/ADP1
PTA2/KBIP2/ADP2
PTA3/KBIP3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PTB2/KBIP6/ADP6
PTD4/TPM1CH4
PTB3/KBIP7/ADP7
PTC0/ADP8
PTC1/ADP9
Figure 3. MC9S08SV16 Series 32-Pin SDIP Package
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
5
PTA0/KBIP0/ADP0
25 PTD5/TPM1CH5
PTC7/MISO
PTC6/MOSI
PTC5/SPSCK
PTC4/SS
PTA5/IRQ/TCLK/RESET
32
31
30
29
28
27
26
PTD2/TPM1CH2
Pin Assignments
PTA4/ACMPO/BKGD/MS 1
PTA3/KBIP3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/KBP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
17 PTB2/KBIP6/ADP6
PTD4/TPM1CH4
PTB3/KBIP7/ADP7
PTC0/ADP8
PTC1/ADP9
PTD3/TPM1CH3 9
PTC3/ADP11/ACMP–
PTB6/XTAL
PTB5/TPM1CH1
PTC2/ADP10/ACMP+
VSS
PTB7/EXTAL
PTA2/KBIP2/ADP2
10
11
12
13
14
15
16
VDD
2
3
4
5
6
7
8
PTB4/TPM1CH0
PTD0/SCL
PTD1/SDA
PTA1/KBIP1/ADP1
24
23
22
21
20
19
18
Figure 4. MC9S08SV16 Series 32-Pin LQFP Package
Table 1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest
Priority
32-SDIP
32-LQFP
Port Pin
I/O
Alt 1
I/O
1
29
PTC5
I/O
SPSCK
I/O
2
30
PTC4
I/O
SS
I/O
3
31
PTA5
I
IRQ
I
4
32
PTD2
I/O
5
1
PTA4
O
ACMPO
O
6
2
PTD0
I/O
SCL
I/O
7
3
PTD1
I/O
SDA
I/O
8
4
--> Highest
Alt 2
I/O
Alt 3
I/O
TCLK
I
RESET
I
MS
I
VDD
I
VSS
I
TPM1CH2 I/O
BKGD
I
9
5
10
6
PTB7
I/O
EXTAL
I
11
7
PTB6
I/O
XTAL
O
12
8
PTB5
I/O
TPM1CH1 I/O
13
9
PTD3
I/O
TPM1CH3 I/O
14
10
PTB4
I/O
TPM1CH0 I/O
MC9S08SV16 Series Data Sheet, Rev. 2
6
Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number
<-- Lowest
32-SDIP
32-LQFP
Port Pin
I/O
15
11
PTC3
16
12
17
18
Alt 1
Priority
Alt 2
I/O
Alt 3
I/O
I/O
ADP11
I
ACMP–
I
PTC2
I/O
ADP10
I
ACMP+
I
13
PTC1
I/O
ADP9
I
14
PTC0
I/O
ADP8
I
19
15
PTB3
I/O
ADP7
I
20
16
PTD4
I/O
21
17
PTB2
I/O
KBIP6
I
ADP6
I
22
18
PTB1
I/O
KBIP5
I
TxD
I/O
ADP5
I
23
19
PTB0
I/O
KBIP4
I
RxD
I
ADP4
I
24
20
PTA7
I/O
KBIP7
I/O
--> Highest
I
TPM1CH4 I/O
TPM2CH1 I/O
25
21
PTA6
I/O
26
22
PTA3
I/O
KBIP3
I
TPM2CH0 I/O
ADP3
I
27
23
PTA2
I/O
KBIP2
I
ADP2
I
28
24
PTA1
I/O
KBIP1
I
ADP1
I
29
25
PTD5
I/O
30
26
PTA0
I/O
KBIP0
I
31
27
PTC7
I/O
MISO
I/O
32
28
PTC6
I/O
MOSI
I/O
TPM1CH5 I/O
ADP0
I
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software must clear out any associated flags before
interrupts are enabled. Table 1 illustrates the priority if multiple modules are
enabled. The highest priority module will have control over the pin.
Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module.
Disable all modules that share a pin before enabling another module.
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
7
Memory Map
4
Memory Map
Figure 5 shows the memory map for the MC9S08SV16 series. On-chip memory in the MC9S08SV16
series of MCUs consist of RAM, flash program memory for nonvolatile data storage, plus I/O and
control/status registers. The registers are divided into two groups:
• Direct-page registers (0x0000 through 0x003F)
• High-page registers (0x1800 through 0x187F)
$0000
$0000
DIRECT PAGE REGISTERS
$003F
$0040
$033F
$0340
RAM 768 BYTES
DIRECT PAGE REGISTERS
$003F
$0040
RAM 1024 BYTES
$043F
$0440
UNIMPLEMENTED
$17FF
$1800
HIGH PAGE REGISTERS
$187F
$1880
UNIMPLEMENTED
$17FF
$1800
HIGH PAGE REGISTERS
$187F
$1880
UNIMPLEMENTED
UNIMPLEMENTED
$BFFF
$C000
FLASH
16384 BYTES
$DFFF
$E000
FLASH
8192 BYTES
$FFFF
$FFFF
MC9S08SV8
MC9S08SV16
Figure 5. MC9S08SV16 Series Memory Map
MC9S08SV16 Series Data Sheet, Rev. 2
8
Freescale Semiconductor
Electrical Characteristics
5
Electrical Characteristics
5.1
Introduction
This section contains electrical and timing specifications for the MC9S08SV16 series of microcontrollers
available at the time of publication.
5.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
5.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pullup resistor associated with the pin is enabled.
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
9
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 5.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
5.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Symbol
Value
Unit
TA
TL to TH
–40 to 85
°C
Thermal resistance
Single-layer board
32-pin SDIP
32-pin LQFP
θJA
60
85
°C/W
Thermal resistance
Four-layer board
32-pin LQFP
32-pin LQFP
θJA
35
56
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
MC9S08SV16 Series Data Sheet, Rev. 2
10
Freescale Semiconductor
Electrical Characteristics
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
5.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification, ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 5. ESD and Latch-Up Test Conditions
Model
Human
body
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
1
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Latch-up
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
11
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
Rating1
No.
1
5.6
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Charge device model (CDM)
VCDM
±500
—
V
3
Latch-up current at TA = 85 °C
ILAT
±100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 7. DC Characteristics
Num C
1
Characteristic
— Operating voltage
P
Output high
voltage
C
3
D
Output high
current
P
Min.
Typical1
Max.
Unit
—
—
2.7
—
5.5
V
VDD > 2.7 V,
ILoad = –2 mA
VDD – 0.5
—
—
VDD > 4.1 V,
ILoad = –10 mA
All I/O pins,
high-drive strength
VDD – 0.5
—
—
VDD > 2.7 V,
ILoad = –2 mA
VDD – 0.5
—
—
Max total IOH for all ports
—
—
—
100
VDD > 2.7 V,
ILoad = 0.6 mA
—
—
0.5
VDD > 4.1 V,
ILoad = 10 mA
—
—
0.5
VDD > 2.7 V,
ILoad = 3 mA
—
—
0.5
—
—
—
100
VDD > 4.1 V
0.70 × VDD
—
—
VOH
IOHT
All I/O pins,
low-drive strength
C
4
Condition
All I/O pins,
low-drive strength
C
2
Symbol
Output low
voltage
C
Output low
current
5
D
6
P Input high
C voltage
7
P Input low
C voltage
8
C
9
Input
P leakage
current
10
Hi-Z
(off-state)
P
leakage
current
Input
hysteresis
All I/O pins,
high-drive strength
VOL
Max total IOL for all ports
IOLT
All digital inputs
VIH
VDD > 2.7 V
0.85 × VDD
—
—
VDD > 4.1 V
—
—
0.35 × VDD
VDD > 2.7 V
—
—
0.30 × VDD
V
mA
V
mA
V
All digital inputs
VIL
All digital inputs
Vhys
—
0.06 × VDD
—
—
mV
All input only pins
(per pin)
|IIn|
VIn = VDD or VSS
—
0.1
1
μA
All input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.1
1
μA
MC9S08SV16 Series Data Sheet, Rev. 2
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
11a
Pullup,
P pulldown
resistors
11b
Pullup,
C pulldown
resistors
12
All digital inputs, when
enabled (all I/O pins other
than
PTA5/IRQ/TCLK/RESET
(PTA5/IRQ/TCLK/RESET)
DC injection
C current 3, 4,
5
Symbol
Condition
Min.
Typical1
Max.
Unit
RPU,
RPD
—
17.5
—
52.5
kΩ
—
17.5
—
52.5
kΩ
–0.2
—
0.2
mA
–5
—
5
mA
RPU,
RPD
2
(Note )
Single pin limit
Total MCU limit, includes
sum of all stressed pins
13
C Input capacitance, all pins
14
C RAM retention voltage
6
IIC
VIN < VSS, VIN > VDD
CIn
—
—
—
8
pF
VRAM
—
—
0.6
1.0
V
15
C POR re-arm voltage
VPOR
—
0.9
1.4
2.0
V
16
D POR re-arm time
tPOR
—
10
—
—
μs
Low-voltage detection threshold —
high range
P
VDD falling
VDD rising
VLVD1
—
3.9
4.0
4.0
4.1
4.1
4.2
Low-voltage detection threshold —
low range
P
VDD falling
VDD rising
VLVD0
—
2.48
2.54
2.56
2.62
2.64
2.70
Low-voltage warning threshold —
high range 1
C
VDD falling
VDD rising
VLVW3
—
4.5
4.6
4.6
4.7
4.7
4.8
Low-voltage warning threshold —
high range 0
P
VDD falling
VDD rising
VLVW2
—
4.2
4.3
4.3
4.4
4.4
4.5
Low-voltage warning threshold
low range 1
P
VDD falling
VDD rising
VLVW1
—
2.84
2.90
2.92
2.98
3.00
3.06
Low-voltage warning threshold —
low range 0
C
VDD falling
VDD rising
VLVW0
—
2.66
2.72
2.74
2.80
2.82
2.88
Vhys
—
—
80
—
mV
VBG
—
—
1.21
—
V
17
18
19
Low-voltage inhibit reset/recover
hysteresis
21
C
22
C Bandgap voltage reference7
V
V
V
V
V
V
Typical values are measured at 25 °C. Characterized, not tested.
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
3 All functional non-supply pins, except for PTA5 are internally clamped to V
SS and VDD.
1
2
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
13
Electrical Characteristics
4
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
6
Maximum is highest voltage that POR is guaranteed.
7
Factory trimmed at VDD = 5.0 V, Temp = 25 °C
Typical IOH vs. V DD-V OH V DD = 5 V (High Drive)
50.000
45.000
40.000
35.000
-40C
mA
30.000
0C
25.000
25C
20.000
55C
85C
15.000
10.000
5.000
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 6. Typical IOH Vs. VDD–VOH (VDD = 5.0 V) (High Drive)
MC9S08SV16 Series Data Sheet, Rev. 2
14
Freescale Semiconductor
Electrical Characteristics
Typical IOH vs. V DD-V OH V DD = 5 V (Low Drive)
10.000
9.000
8.000
7.000
-40C
mA
6.000
0C
5.000
25C
4.000
55C
85C
3.000
2.000
1.000
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 7. Typical IOH Vs. VDD–VOH (VDD = 5.0 V) (Low Drive)
Typical IOL vs. VOL VDD = 5 V (High Drive)
50.000
45.000
40.000
mA
35.000
-40C
30.000
0C
25.000
25C
20.000
55C
85C
15.000
10.000
5.000
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 8. Typical IOH Vs. VOL (VDD = 5.0 V) (High Drive)
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
15
Electrical Characteristics
Typical IOL vs. VOL VDD = 5V (Low Drive)
14.000
12.000
10.000
-40C
0C
mA
8.000
25C
6.000
55C
85C
4.000
2.000
0.000
0
0.3
0.5
0.8
1
1.3
2
V
Figure 9. Typical IOH Vs. VOL (VDD = 5.0 V) (Low Drive)
Typical IOH vs. VDD-VOH VDD = 3 V (High Drive)
20.000
18.000
16.000
mA
14.000
-40C
12.000
0C
10.000
25C
8.000
55C
85C
6.000
4.000
2.000
0.000
0
0.3
0.5
0.8
0.9
1.2
1.5
V
Figure 10. Typical IOH Vs. VDD–VOH (VDD = 3.0 V) (High Drive)
MC9S08SV16 Series Data Sheet, Rev. 2
16
Freescale Semiconductor
Electrical Characteristics
Typical IOH vs. V DD-V OH V DD = 3 V (Low Drive)
4.000
3.500
mA
3.000
2.500
-40C
2.000
25C
0C
55C
1.500
85C
1.000
0.500
0.000
0
0.3
0.5
0.8
0.9
1.2
1.5
V
Figure 11. Typical IOH Vs. VDD–VOH (VDD = 3.0 V) (Low Drive)
Typical IOL vs. V OL V DD = 3 V (High Drive)
24.000
22.000
20.000
mA
18.000
16.000
-40C
14.000
0C
12.000
25C
10.000
55C
8.000
85C
6.000
4.000
2.000
0.000
0
0.3
0.5
0.8
0.9
1.2
1.5
V
Figure 12. Typical IOL Vs. VOL (VDD = 3.0 V) (High Drive)
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
17
Electrical Characteristics
Typical IOL vs. V OL V DD = 3 V (Low Drive)
5.500
5.000
4.500
4.000
-40C
mA
3.500
0C
3.000
25C
2.500
55C
2.000
85C
1.500
1.000
0.500
0.000
0
0.3
0.5
0.8
0.9
1.2
1.5
V
Figure 13. Typical IOL Vs. VOL (VDD = 3.0 V) (Low Drive)
5.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Num
C
Parameter
Symbol
P
1
C
RIDD
P
C
Run supply current
FBE mode, all modules on
RIDD
C
C
3
C
Run supply current
FBE mode, all modules off
RIDD
C
C
4
C
Run supply current
FBE mode, all modules off
RIDD
C
5
C
C
Typical1
Max
10.57
12.96
5.24
6.48
1 MHz
2.00
2.60
20 MHz
8.86
10.86
4.53
5.61
1 MHz
1.82
2.31
20 MHz
5.91
7.25
2.94
3.69
1 MHz
1.18
1.54
20 MHz
5.69
6.98
2.90
3.60
1.17
1.49
4.83
—
1.06
—
VDD (V)
20 MHz
Run supply current
FBE mode, all modules on
C
2
Bus
Freq
8 MHz
8 MHz
8 MHz
8 MHz
5
3
5
3
1 MHz
Wait mode current
FBE mode, all modules off
WIDD
20 MHz
1 MHz
5
Unit
Temp
mA
–40 to 85 °C
mA
–40 to 85 °C
mA
–40 to 85 °C
mA
–40 to 85 °C
mA
–40 to 85 °C
MC9S08SV16 Series Data Sheet, Rev. 2
18
Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num
6
C
C
C
Parameter
Symbol
Wait mode current
FBE mode, all modules off
WIDD
P
7
11
1
1 MHz
Typical1
Max
4.80
—
1.05
—
5
0.85
1.06
2.59
—
—
—
—
—
—
VDD (V)
3
S2IDD
C
—
3
0.76
0.97
2.25
P
—
5
0.85
1.17
3.56
—
—
3
0.76
1.07
3.22
—
—
5
128.72
—
—
3
123.86
—
—
—
5
300
—
—
—
3
300
—
—
—
5
106.7
—
—
—
3
95.6
—
Stop3 mode supply current
no clocks active
S3IDD
C
10
20 MHz
—
Stop2 mode supply current
8
9
Bus
Freq
C
C
C
C
C
ADC adder to stop3
—
RTC adder to stop3 and stop2
LVD adder to stop3 and stop2
Unit
Temp
mA
–40 to 85 °C
μA
μA
–40 °C
25 °C
85 °C
–40 °C
25 °C
85 °C
–40 °C
25 °C
85 °C
–40 °C
25 °C
85 °C
μA
–40 to 85 °C
nA
–40 to 85 °C
μA
–40 to 85 °C
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
19
Electrical Characteristics
SV16 Run Current VS. Bus Frequency
7.0000
Run Current (mA)
6.0000
5.0000
FBE 3V -40C
FBE 3V 25C
FBE 3V 85C
FBE 5V -40C
FBE 5V 25C
FBE 5V 85C
4.0000
3.0000
2.0000
1.0000
0.0000
1
2
4
8
10
20
Bus Frequency (MHz)
Figure 14. Typical Run IDD for FBE (All Modules Off)
MC9S08SV16 Series Data Sheet, Rev. 2
20
Freescale Semiconductor
Electrical Characteristics
5.8
External Oscillator (XOSC) and ICS Characteristics
Refer to Figure 16 for crystal or resonator circuits.
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient )
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1) FEE or FBE mode2
High range (RANGE = 1), high gain (HGO = 1), FBELP mode
High range (RANGE = 1), low power (HGO = 0), FBELP mode
2
D Load capacitors
3
D
Symbol
Min
Typical1
Max
Unit
flo
fhi
fhi
fhi
32
1
1
1
—
—
—
—
38.4
5
16
8
kHz
MHz
MHz
MHz
C1
C2
Feedback resistor
Low range (32 kHz to 38.4 kHz)
See Note 3
RF
—
10
1
—
MΩ
MΩ
0
100
—
kΩ
0
0
0
0
10
20
High range (1 MHz to 16 MHz)
1
4
D
Series resistor — Low range
Low gain (HGO = 0)
High gain (HGO = 1)
RS
—
5
Series resistor — High range
Low gain (HGO = 0)
High gain (HGO = 1)
D
≥ 8 MHz
4 MHz
1 MHz
RS
—
6
Crystal start-up time 4, 5
Low range, low power
C
Low range, high power
High range, low power
High range, high power
t
CSTL
—
t
CSTH
200
400
5
15
—
kΩ
ms
tIRST
—
60
100
μs
fextal
0.03125
0
—
5
40
MHz
MHz
P Average internal reference frequency — trimmed
fint_t
—
31.25
—
kHz
P DCO output frequency range —
trimmed
P
fdco_t
16
—
20
32
—
40
Δfdco_t
—
–1.0 to 0.5
±0.5
±2
±1
%fdco
tAcquire
—
—
1
ms
CJitter
—
0.02
0.2
%fdco
7
T Internal reference start-up time
8
D
9
10
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE or FBE mode2
FBELP mode
Low range (DRS = 00)
Middle range (DRS = 10)
Total deviation of DCO output from trimmed frequency4
Over full voltage and temperature range
Over fixed voltage and temperature range of 0 to 70 °C
11
C
12
C FLL acquisition time4,6
13
C
Long term jitter of DCO output clock (averaged over 2 ms
interval)7
MHz
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
21
Electrical Characteristics
2
3
4
5
6
7
When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz
to 39.0625 kHz.
See crystal or resonator manufacturer’s recommendation.
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit
is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical Crystal or Resonator Circuit
1.00%
0.50%
Deviation (%)
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
-1.00%
TBD
-1.50%
-2.00%
Temperature
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
MC9S08SV16 Series Data Sheet, Rev. 2
22
Freescale Semiconductor
Electrical Characteristics
5.9
AC Characteristics
This section describes timing characteristics for each peripheral system.
5.9.1
Control Timing
Table 10. Control Timing
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
20
MHz
D
Internal low power oscillator period
tLPO
700
—
1300
μs
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 × tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
Num
C
1
D
2
9
Rating
ns
C
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 85 °C.
1
2
textrst
RESET PIN
Figure 17. Reset Timing
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
23
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
5.9.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 11. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus/4
Hz
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
MC9S08SV16 Series Data Sheet, Rev. 2
24
Freescale Semiconductor
Electrical Characteristics
5.9.3
SPI Timing
Table 12 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 12. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
1
D
SPSCK period
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
2
D
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSPSCK
tcyc
3
D
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSPSCK
tcyc
4
D
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
5
D
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
D
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
25
Electrical Characteristics
SS1
(OUTPUT)
11
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
9
MOSI
(OUTPUT)
LSB IN
10
9
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
BIT 6 . . . 1
10
9
MOSI
(OUTPUT) PORT DATA
LSB IN
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08SV16 Series Data Sheet, Rev. 2
26
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
BIT 6 . . . 1
MSB OUT
SLAVE
10
10
9
SEE
NOTE
SLAVE LSB OUT
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SPSCK
(CPOL = 0)
(INPUT)
4
SPSCK
(CPOL = 1)
(INPUT)
4
SEE
NOTE
SLAVE
MSB OUT
5
7
MOSI
(INPUT)
11
11
12
10
9
MISO
(OUTPUT)
12
8
BIT 6 . . . 1
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
5.10
Analog Comparator (ACMP) Electricals
Table 13. Analog Comparator Electrical Specifications
C
Characteristic
D
Supply voltage
P
Supply current (active)
Symbol
Min
Typical
Max
Unit
VDD
2.7
—
5.5
V
IDDAC
—
20
35
μA
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
27
Electrical Characteristics
Table 13. Analog Comparator Electrical Specifications (continued)
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
—
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
μA
C
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
5.11
ADC Characteristics
Table 14. 10-Bit ADC Operating Conditions
Symb
Min
Typ1
Max
Unit
VDDA
2.7
—
5.5
V
Input voltage
VADIN
VREFL
—
VREFH
V
Input
capacitance
CADIN
—
4.5
5.5
pF
Input resistance
RADIN
—
3
5
kΩ
RAS
—
—
—
—
5
10
kΩ
—
—
10
0.4
—
8.0
0.4
—
4.0
Characteristic
Supply voltage
Analog source
resistance
Conditions
Absolute
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
8-bit mode (all valid fADCK)
ADC
conversion
clock frequency
1
High speed (ADLPC = 0)
Low power (ADLPC = 1)
fADCK
Comment
External to MCU
MHz
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
MC9S08SV16 Series Data Sheet, Rev. 2
28
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
RAS
VAS
ADC SAR
ENGINE
RADIN
+
VADIN
–
CAS
+
–
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ZADIN
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 25. ADC Input Impedance Equivalency Diagram
Table 15. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA)
Symb
Min
Typ1
Max
Unit
T
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
IDDA
—
133
—
μA
T
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
IDDA
—
218
—
μA
T
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
IDDA
—
327
—
μA
P
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
IDDA
—
0.582
1
mA
ADC
asynchronous
clock source
2
3.3
5
P
C
Characteristic
Conditions
High speed (ADLPC = 0)
Low power (ADLPC = 1)
fADACK
MHz
1.25
2
3.3
Comment
tADACK =
1/fADACK
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
29
Electrical Characteristics
Table 15. 10-Bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
C
Characteristic
Conditions
Conversion
time (including
sample time)
Short sample (ADLSMP = 0)
P
Long sample (ADLSMP = 1)
Symb
tADC
Short sample (ADLSMP = 0)
P
Sample time
Long sample (ADLSMP = 1)
D
D
P
P
P
P
T
T
P
P
Temp sensor
slope
–40 °C– 25 °C
25 °C
Total
unadjusted
error
10-bit mode
Integral
non-linearity
Zero-scale
error
T
VTEMP25
ETUE
8-bit mode
10-bit mode3
8-bit
D
D
Max
—
20
—
—
40
—
—
3.5
—
—
23.5
—
—
3.266
—
—
3.638
—
—
1.396
—
—
±1.5
±3.5
mode3
10-bit mode
—
±0.7
±1.5
—
±0.5
±1.0
—
±0.3
±0.5
—
±0.5
±1.0
—
±0.3
±0.5
—
±1.5
±2.1
—
±0.5
±0.7
—
±1
±1.5
—
±0.5
±0.5
—
—
±0.5
—
—
±0.5
—
±0.2
±2.5
—
±0.1
±1
INL
8-bit mode
10-bit mode
EZS
8-bit mode
10-bit mode
EFS
8-bit mode
Quantization
error
10-bit mode
Input leakage
error
10-bit mode
EQ
8-bit mode
EIL
8-bit mode
Unit
ADCK
cycles
ADCK
cycles
Comment
See reference
manual for
conversion
time variances
mV/°C
DNL
Full-scale error
T
Typ1
m
25 °C– 85 °C
Temp sensor
voltage
Differential
non-linearity
tADS
Min
mV
LSB2
Includes
quantization
LSB2
LSB2
LSB2
VADIN = VSSA
LSB2
VADIN = VDDA
LSB2
LSB2
Pad leakage4 *
RAS
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes
4 Based on input pad leakage current. Refer to pad electricals.
1
5.12
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
MC9S08SV16 Series Data Sheet, Rev. 2
30
Freescale Semiconductor
Electrical Characteristics
Table 16. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
–40 °C to 85 °C
Vprog/erase
2.7
—
5.5
V
D
Supply voltage for read operation
VRead
2.7
—
5.5
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
μs
1
D
Internal FCLK frequency
D
Internal FCLK period (1/FCLK)
P
P
P
P
C
C
2
Byte program time (random location)
Byte program time (burst mode)
2
2
Page erase time
2
Mass erase time
Byte program current
Page erase
3
current3
tprog
9
tFcyc
tBurst
4
tFcyc
tPage
4000
tFcyc
tMass
20,000
tFcyc
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
10,000
—
100,000
—
—
cycles
15
100
—
years
endurance4
C
Program/erase
TL to TH = –40 °C to 85 °C
T = 25 °C
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures
DD
with VDD = 5.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
5.13
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5.13.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (the North and East).
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
31
Ordering Information
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal
to the reported emissions levels.
Table 17. Radiated Emissions, Electric Field
Parameter
Radiated emissions,
electric field
1
Symbol
Conditions
Frequency
fOSC/fBUS
VRE_TEM
VDD = 5.0 V
TA = 25 oC
package type
32-pin LQFP
0.15 – 50 MHz
4 MHz crystal
19 MHz bus
50 – 150 MHz
Level1
(Max)
Unit
9
dBμV
5
150 – 500 MHz
2
500 – 1000 MHz
1
IEC Level
N
—
SAE Level
1
—
Data based on qualification test results.
6
Ordering Information
This section contains ordering information for MC9S08SV16 series devices. See below for an example of
the device numbering system.
Table 18. Device Numbering System
Memory
Device Number1
Available Packages2
FLASH
RAM
MC9S08SV16
16 KB
1024 Byte
MC9S08SV8
8 KB
768 Byte
32-pin SDIP
32-pin LQFP
1
See the reference manual, MC9S08SV16 Series Reference Manual, for a complete
description of modules included on each device.
2
See Table 19 for package information.
Example of the device numbering system:
MC 9 S08 SV 16
Status
(MC = Fully qualified)
Memory
(9 = Flash-based)
Core
Family
C XX
Package designator (see Table 19)
Temperature range
(C = –40 °C to 85 °C)
Approximate flash size in KB
MC9S08SV16 Series Data Sheet, Rev. 2
32
Freescale Semiconductor
Package Information
7
Package Information
Table 19. Package Descriptions
Pin Count
7.1
Package Type
Abbreviation
Designator
Case No.
Document No.
32
Low Quad Flat Package
LQFP
LC
873A-03
98ASH70029A
32
Shrink Dual In-line Package
SDIP
BM
1376-02
98ASA99330D
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 19.
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
33
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MC9S08SV16
Rev. 2
7/2009