FREESCALE MC9S08QE96CFT

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MC9S08QE128
Rev. 3, 06/2007
MC9S08QE128
MC9S08QE128 Series
80-LQFP
Case 917A
14 mm2
Covers: MC9S08QE128, MC9S08QE96, MC9S08QE64
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 50.33-MHz HCS08 CPU from 3.6V to 2.1V, and
20-MHz CPU at 2.1V to 1.8V across temperature range
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Flash read/program/erase over full operating voltage and
temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3
mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait,
and stop modes with internal and external clock sources
– 6 μs typical wake up time from stop modes
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by
internal or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints)
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes.
48-QFN
Case 1314
7 mm2
44-QFP
Case 824A
10 mm2
32-LQFP
Case 873A
7 mm2
•
•
•
•
•
•
•
•
Eight deep FIFO for storing change-of-flow addresses
and event-only data. Debug module supports both tag
and force breakpoints.
ADC — 24-channel, 12-bit resolution; 2.5 μs conversion
time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V
ACMPx — Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap reference
voltage; outputs can be optionally routed to TPM module;
operation in stop3
SCIx — Two SCIs with full duplex non-return to zero
(NRZ); LIN master extended break generation; LIN slave
extended break detection; wake up on active edge
SPIx— Two serial peripheral interfaces with Full-duplex or
single-wire bidirectional; Double-buffered transmit and
receive; MSB-first or LSB-first shifting
IICx — Two IICs with; Up to 100 kbps with maximum bus
loading; Multi-master operation; Programmable slave
address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10 bit addressing
TPMx — One 6-channel and two 3-channel; Selectable
input capture, output compare, or buffered edge- or
center-aligned PWMs on each channel
RTC — 8-bit modulus counter with binary or decimal
based prescaler; External clock source for precise time
base, time-of-day, calendar or task scheduling functions;
Free running on-chip low power oscillator (1 kHz) for
cyclic wake-up without external components
Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins.
– SET/CLR registers on 16 pins (PTC and PTE)
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
64-LQFP
Case 840F
10 mm2
Table of Contents
1
2
3
MC9S08QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . .4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .21
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .22
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .24
4
5
6
7
3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.4 Analog Comparator (ACMP) Electricals . . . . . .
3.10.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
3.10.6 Flash Specifications . . . . . . . . . . . . . . . . . . . . .
3.11 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
3.11.2 Conducted Transient Susceptibility . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . .
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
27
30
30
33
33
34
34
35
36
36
36
50
50
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
2
Freescale Semiconductor
3-CHANNEL TIMER/PWM
MODULE (TPM1)
PORT A
TPM1CLK
CPU
ACMP1O
ANALOG COMPARATOR
(ACMP1)
BKP
IIC MODULE (IIC1)
ANALOG COMPARATOR
(ACMP2)
USER FLASH
128K / 96K / 64K
PTC7/TxD2/ACMP2PTC6/RxD2/ACMP2+
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4/RSTO
PTC3/TPM3CH3
PTC2/TPM3CH2
PTC1/TPM3CH1
PTC0/TPM3CH0
PTD7/KBI2P7
PTD6/KBI2P6
PTD5/KBI2P5
PTD4/KBI2P4
PTD3/KBI2P3/SS2
PTD2/KBI2P2/MISO2
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTE7/TPM3CLK
PTE6
PTE5
PTE4
PTE3/SS1
PTE2/MISO1
PTE1/MOSI1
PTE0/TPM2CLK/SPSCK1
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTF3/ADP13
PTF2/ADP12
PTF1/ADP11
PTF0/ADP10
PTG7/ADP23
PTG6/ADP22
PTG5/ADP21
PTG4/ADP20
PTG3/ADP19
PTG2/ADP18
PTG1
PTG0
TPM2CLK
SCL1
SDA1
ACMP2+
ACMP2O
ACMP2TPM3CH5-0
6
6-CHANNEL TIMER/PWM
MODULE (TPM3)
PORT B
IRQ
3
PORT C
INT
MODULE (TPM2)
IRQ
LVD
TPM2CH2-0
3-CHANNEL TIMER/PWM
PORT D
OSCILLATOR (XOSC)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTB5/TPM1CH1/SS1
PTB4/TPM2CH1/MISO1
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTB1/KBI1P5/TxD1/ADP5
PTB0/KBI1P4/RxD1/ADP4
PORT E
HCS08 SYSTEM CONTROL
COP
EXTAL
XTAL
INTERNAL CLOCK
SOURCE (ICS)
PORT F
BDC
ACMP1+
ACMP1-
PORT G
RESET
BKGD/MS
HCS08 CORE
PTA7/TPM2CH2/ADP9
PTA6/TPM1CH2/ADP8
PTA5/IRQ/TPM1CLK/RESET
PTA4/ACMP1O/BKGD/MS
PTA3/KBI1P3/SCL1/ADP3
PTA2/KBI1P2/SDA1/ADP2
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
TPM1CH2-0
TPM3CLK
USER RAM
10
8K / 6K / 4K
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
DEBUG MODULE (DBG)
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
VOLTAGE
REGULATOR
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
PORT J
VDD
VDD
VSS
VSS
REAL TIME COUNTER (RTC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
SS2
MISO2
MOSI2
SPSCK2
TxD2
RxD2
SS1
MISO1
MOSI1
SPSCK1
24-CHANNEL,12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VREFH
VREFL
VDDA
VSSA
SDA2
SCL2
IIC MODULE (IIC2)
PORT H
PTH7/SDA2
PTH6/SCL2
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
TxD1
RxD1
- VREFH/VREFL internally connected to VDDA/VSSA in 48-pin and 32-pin packages
- VDD and VSS pins are each internally connected to two pads in 32-pin package
Figure 1. MC9S08QE128 Series Block Diagram
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
3
MC9S08QE128 Series Comparison
1
MC9S08QE128 Series Comparison
The following table compares the various device derivatives available within the MC9S08QE128 series.
Table 1. MC9S08QE128 Series Features by MCU and Package
Feature
MC9S08QE128
MC9S08QE96
MC9S08QE64
Flash size (bytes)
131072
98304
65536
RAM size (bytes)
8064
6016
4096
Pin quantity
80
64
48
44
80
64
48
ACMP1
yes
ACMP2
yes
ADC channels
24
22
10
10
24
22
10
DBG
yes
ICS
yes
IIC1
yes
IIC2
yes
yes
no
no
yes
IRQ
yes
no
1
Port I/O
48
44
32
10
22
10
10
10
no
yes
no
no
no
16
16
16
16
16
16
16
16
16
16
16
12
70
54
38
34
70
54
38
34
54
38
34
26
RTC
yes
SCI1
yes
SCI2
yes
SPI1
yes
SPI2
yes
TPM1 channels
3
TPM2 channels
3
TPM3 channels
6
1
64
yes
KBI
XOSC
44
yes
Port I/O count does not include the input only PTA5/IRQ/TPM1CLK/RESET or the output
only PTA4/ACMP1O/BKGD/MS.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
4
Freescale Semiconductor
Pin Assignments
2
Pin Assignments
PTC7/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTE0/TPM2CLK/SPSCK1
PTE1/MOSI1
PTG0
PTG1
PTG2/ADP18
PTG3/ADP19
PTE2/MISO1
PTE3/SS1
PTG4/ADP20
PTG5/ADP21
PTG6/ADP22
PTG7/ADP23
PTC6/RxD2/ACMP2+
PTA4/ACMP1O/BKGD/MS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PTA2/KBI1P2/SDA1/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTJ0
PTJ1
PTF0/ADP10
PTF1/ADP11
VSS
VDD
PTE4
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTF2/ADP12
PTF3/ADP13
PTJ2
PTJ3
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTD5/KBI2P5
PTJ7
PTJ6
PTJ5
PTJ4
PTC1/TPM3CH1
PTC0/TPM3CH0
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5
PTB5/TPM1CH1/SS1
PTB4/TPM2CH1/MISO1
PTC3/TPM3CH3
PTC2/TPM3CH2
PTD7/KBI2P7
PTD6/KBI2P6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTE6
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTH7/SDA2
PTH6/SCL2
PTH5
PTH4
PTE7/TPM3CLK
VDD
VDDAD
VREFH
VREFL
VSSAD
VSS
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTH3
PTH2
PTH1
PTH0
PTA5/IRQ/TPM1CLK/RESET
PTC4/TPM3CH4/RSTO
PTC5/TPM3CH5/ACMP2O
This section describes the pin assignments for the available packages. See Table 2 for pin availability by package pin-count.
Pins in bold are added from the next smaller package.
Figure 2. Pin Assignments in 80-Pin LQFP
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
5
PTC7/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
PTC6/RxD2/ACMP2+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PTA2/KBI1P2/SDA11/ADP2
PTA3/KBI1P3/SCL1/ADP3
PTD2/KBI2P2/MISO2
PTD3/KBI2P3/SS2
PTD4/KBI2P4
PTF0/ADP10
PTF1/ADP11
VSS
VDD
PTE4
PTA6/TPM1CH2/ADP8
PTA7/TPM2CH2/ADP9
PTF2/ADP12
PTF3/ADP13
PTB0/KBI1P4/RxD1/ADP4
PTB1/KBI1P5/TxD1/ADP5
PTD5/KBI2P5
PTC1/TPM3CH1
PTC0/TPM3CH0
PTF7/ADP17
PTF6/ADP16
PTF5/ADP15
PTF4/ADP14
PTB3/KBI1P7/MOSI1/ADP7
PTB2/KBI1P6/SPSCK1/ADP6
PTE5
PTB5/TPM1CH1/SS1
PTB4/TPM2CH1/MISO1
PTC3/TPM3CH3
PTC2/TPM3CH2
PTD7/KBI2P7
PTD6/KBI2P6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PTE6
PTE0/TPM2CLK/SPSCK1
PTE1/MOSI1
PTG0
PTG1
PTG2/ADP18
PTG3/ADP19
PTE2/MISO1
PTE3/SS1
PTA4/ACMP1O/BKGD/MS
PTH1
PTH0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTD1/KBI2P1/MOSI2
PTD0/KBI2P0/SPSCK2
PTH7/SDA2
PTH6/SCL2
PTE7/TPM3CLK
VDD
VDDAD
VREFH
VREFL
VSSAD
VSS
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL
PTA5/IRQ/TPM1CLK/RESET
PTC4/TPM3CH4/RSTO
PTC5/TPM3CH5/ACMP2O
Pin Assignments
Pins in bold are added from the next smaller package.
Figure 3. Pin Assignments in 64-Pin LQFP Package
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
6
Freescale Semiconductor
PTA1/KBI1P1/TPM2CH0/AD
37 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
38 PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
39 PTC7/TxD2/ACMP2-
40 PTC6/RxD2/ACMP2+
41 PTE3/SS1
42 PTE2/MISO1
43 PTE1/MOSI1
44 PTE0/TPM2CLK/SPSCK1
45 PTC5/TPM3CH5/ACMP2O
46 PTC4/TPM3CH4/RSTO
47 PTA5/IRQ/TPM1CLK/RESET
48 PTA4/ACMP1O/BKGD/MS
Pin Assignments
PTD1/KBI2P1/MOSI2 1
36 PTA2/KBI1P2/SDA1/ADP2
PTD0/KBI2P0/SPSCK2 2
35 PTA3/KBI1P3/SCL1/ADP3
34 PTD2/KBI2P2/MISO2
PTE7/TPM3CLK 3
33 PTD3/KBI2P3/SS2
VDD 4
VDDAD 5
32 PTD4/KBI2P4
VREFH 6
31 VSS
VREFL 7
30 VDD
VSSAD 8
29 PTE4
VSS 9
28 PTA6/TPM1CH2/ADP8
PTB2/KBI1P6/SPSCK1/ADP6 24
PTB3/KBI1P7/MOSI1/ADP7 23
PTC0/TPM3CH0 22
PTC1/TPM3CH1 21
PTD5/KBI2P5 20
PTD6/KBI2P6 19
PTD7/KBI2P7 18
25 PTB1/KBI1P5/TxD1/ADP5
PTC2/TPM3CH2 17
PTE6 12
PTC3/TPM3CH3 16
26 PTB0/KBI1P4/RxD1/ADP4
PTB4/TPM2CH1/MISO1 15
PTB6/SDA11/XTAL 11
PTB5/TPM1CH1/SS1 14
27 PTA7/TPM2CH2/ADP9
PTE5 13
PTB7/SCL1/EXTAL 10
Figure 4. Pin Assignments in 48-Pin QFN Package
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
7
PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+
PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1-
35
34
PTC7/TxD2/ACMP236
PTC6/RxD2/ACMP2+
37
PTE2
38
PTE1
39
PTC5/TPM3CH5/ACMP2O
PTC4/TPM3CH4/RSTO
PTA5/IRQ/TPM1CLK/RESET
PTE0/TPM2CLK
40
PTD0/KBI2P0/SPSCK2
41
1
42
PTD1/KBI2P1/MOSI2
43
44
PTA4/ACMP1O/BKGD/MS
Pin Assignments
7
27
VDD
VSSAD
8
26
PTA6/TPM1CH2/ADP8
VSS
9
25
PTA7/TPM2CH2/ADP9
10
24
PTB0/KBI1P4/RxD1/ADP4
23
PTB1/KBI1P5/TxD1/ADP5
PTB7/SCL1/EXTAL
PTB6/SDA1/XTAL 11
22
VREFL
PTB2/KBI1P6/SPSCK1/ADP6
VSS
21
28
PTB3/KBI1P7/MOSI1/ADP7
6
20
VREFH
PTC0/TPM3CH0
PTD4/KBI2P4
19
29
PTC1/TPM3CH1
5
18
VDDAD
PTD5/KBI2P5
PTD3/KBI2P3/SS2
17
30
PTD6/KBI2P6
4
16
VDD
PTD7/KBI2P7
PTD2/KBI2P2/MISO2
15
31
PTC2/TPM3CH2
3
14
PTE7/TPM3CLK
PTC3/TPM3CH3
PTA3/KBI1P3/SCL1/ADP3
13
32
PTB4/TPM2CH1/MISO1
2
12
PTA2/KBI1P2/SDA1/ADP2
PTB5/TPM1CH1/SS1
33
Figure 5. Pin Assignments in 44-Pin QFP Package
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
8
Freescale Semiconductor
PTA4/ACMP1O/BKGD/MS
PTA5/IRQ/TPM1CLK/RESET
PTC4/TPM3CH4/RSTO
PTC5/TPM3CH5/ACMP2O
PTC6/RxD2/ACMP2+
PTC7/TxD2/ACMP2-
PTA0/KBIP0/TPM1CH0/ADP0/ACMP1
PTA1/KBIP1/TPM2CH0/ADP1/ACMP1
Pin Assignments
32
31
30
29
28
27
26
25
VDD
3
22
PTD2/KBI2P2/MISO2
VREFH/VDDAD
4
21
PTD3/KBI2P3/SS2
VREFL/VSSAD
5
20
PTA6/TPM1CH2/ADP8
VSS
6
19
PTA7/TPM2CH2/ADP9
PTB7/SCL1/EXTAL
7
18
PTB0/KBI1P4/RxD1/ADP4
PTB6/SDA1/XTAL
8
17
PTB1/KBI1P5/TxD1/ADP5
9
10
11
12
13
14
15
16
PTB2/KBI1P6/SPSCK1/ADP6
PTA3/KBIP3/SCL1/ADP3
PTB3/KBI1P7/MOSI1/ADP7
23
PTC0/TPM3CH0
2
PTC1/TPM3CH1
PTD0/KBI2P0/SPSCK2
PTC2/TPM3CH2
PTA2/KBIP2/SDA1/ADP2
PTC3/TPM3CH3
24
PTB4/TPM2CH1/MISO1
1
PTB5/TPM1CH1/SS1
PTD1/KBI2P1/MOSI2
Figure 6. Pin Assignments 32-Pin LQFP Package
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
9
Pin Assignments
Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count
Pin Number
Lowest
←⎯
Priority
⎯→
Highest
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
80
64
48
44
32
1
1
1
1
1
PTD1
KBI2P1
MOSI2
2
2
2
2
2
PTD0
KBI2P0
SPSCK2
3
3
—
—
—
PTH7
SDA2
4
4
—
—
—
PTH6
SCL2
5
—
—
—
—
PTH5
6
—
—
—
—
PTH4
7
5
3
3
—
PTE7
8
6
4
4
3
VDD
9
7
5
5
4
VDDA
10
8
6
6
—
VREFH
TPM3CLK
11
9
7
7
—
VREFL
12
10
8
8
5
VSSA
13
11
9
9
6
14
12
10
10
7
15
13
11
11
16
—
—
—
VSS
PTB7
SCL1
EXTAL
8
PTB6
SDA1
XTAL
—
PTH3
17
—
—
—
—
PTH2
18
14
—
—
—
PTH1
19
15
—
—
—
PTH0
20
16
12
—
—
PTE6
21
17
13
—
—
PTE5
22
18
14
12
9
PTB5
TPM1CH1 SS1
23
19
15
13
10
PTB4
TPM2CH1 MISO1
24
20
16
14
11
PTC3
TPM3CH3
25
21
17
15
12
PTC2
TPM3CH2
26
22
18
16
—
PTD7
KBI2P7
27
23
19
17
—
PTD6
KBI2P6
28
24
20
18
—
PTD5
KBI2P5
29
—
—
—
—
PTJ7
30
—
—
—
—
PTJ6
31
—
—
—
—
PTJ5
32
—
—
—
—
PTJ4
33
25
21
19
13
PTC1
TPM3CH1
34
26
22
20
14
PTC0
TPM3CH0
35
27
—
—
—
PTF7
ADP17
36
28
—
—
—
PTF6
ADP16
37
29
—
—
—
PTF5
ADP15
38
30
—
—
—
PTF4
ADP14
39
31
23
21
15
PTB3
KBI1P7
MOSI1
ADP7
40
32
24
22
16
PTB2
KBI1P6
SPSCK1
ADP6
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
10
Freescale Semiconductor
Pin Assignments
Table 2. MC9S08QE128 Series Pin Assignment by Package and Pin Count (continued)
Pin Number
80
64
48
44
32
41
33
25
23
17
42
34
26
24
43
—
—
—
Lowest
←⎯
Priority
⎯→
Highest
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
PTB1
KBI1P5
TxD1
ADP5
18
PTB0
KBI1P4
RxD1
ADP4
—
PTJ3
44
—
—
—
—
PTJ2
45
35
—
—
—
PTF3
46
36
—
—
—
PTF2
47
37
27
25
19
PTA7
TPM2CH2
ADP9
48
38
28
26
20
PTA6
TPM1CH2
ADP8
49
39
29
—
—
PTE4
50
40
30
27
—
VDD
51
41
31
28
—
VSS
52
42
—
—
—
PTF1
ADP11
53
43
—
—
—
PTF0
ADP10
54
—
—
—
—
PTJ1
55
—
—
—
—
PTJ0
56
44
32
29
—
PTD4
KBI2P4
57
45
33
30
21
PTD3
KBI2P3
58
46
34
31
22
PTD2
KBI2P2
MISO2
59
47
35
32
23
PTA3
KBI1P3
SCL1
ADP3
60
48
36
33
24
PTA2
KBI1P2
SDA1
ADP2
61
49
37
34
25
PTA1
KBI1P1
TPM2CH0 ADP1
ACMP1-
62
50
38
35
26
PTA0
KBI1P0
TPM1CH0 ADP0
63
51
39
36
27
PTC7
TxD2
64
52
40
37
28
PTC6
RxD2
65
—
—
—
—
PTG7
ADP23
66
—
—
—
—
PTG6
ADP22
67
—
—
—
—
PTG5
ADP21
ADP13
ADP12
SS2
ACMP1+
ACMP2ACMP2+
68
—
—
—
—
PTG4
69
53
41
—
—
PTE3
SS1
ADP20
70
54
42
38
—
PTE2
MISO1
71
55
—
—
—
PTG3
ADP19
72
56
—
—
—
PTG2
ADP18
73
57
—
—
—
PTG1
74
58
—
—
—
PTG0
75
59
43
39
—
PTE1
MOSI1
76
60
44
40
—
PTE0
TPM2CLK SPSCK1
77
61
45
41
29
PTC5
TPM3CH5
78
62
46
42
30
PTC4
TPM3CH4 RSTO
79
63
47
43
31
PTA5
IRQ
TPM1CLK RESET
80
64
48
44
32
PTA4
ACMP1O
BKGD
ACMP2O
MS
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08QE128 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant sample
size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that
normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either
VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
12
Freescale Semiconductor
Electrical Characteristics
3
3.4
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it
is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
TL to TH
–40 to 85
°C
TJM
95
°C
Thermal resistance
Single-layer board
82
32-pin LQFP
44-pin LQFP
θJA
48-pin QFN
64-pin LQFP
80-pin LQFP
69
°C/W
81
θJA
69
60
°C/W
Thermal resistance
Four-layer board
54
32-pin LQFP
44-pin LQFP
θJA
48-pin QFN
64-pin LQFP
80-pin LQFP
47
°C/W
26
θJA
50
47
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
13
Electrical Characteristics
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Human
Body
Machine
Latch-up
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Table 7. ESD and Latch-Up Protection Characteristics
No.
1
Rating1
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
± 2000
—
V
2
Machine model (MM)
VMM
± 200
—
V
3
Charge device model (CDM)
VCDM
± 500
—
V
4
Latch-up current at TA = 85°C
ILAT
± 100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
14
Freescale Semiconductor
Electrical Characteristics
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
1
Symbol
Output high
voltage
All I/O pins,
low-drive strength
P
All I/O pins,
high-drive strength
1.8 V, ILoad = –2 mA
VOH
C
4
D
Output high
current
C
Output low
voltage
Max total IOH for all
ports
Typ1
P
All I/O pins,
high-drive strength
VOL
C
Max total IOL for all
ports
Output low
current
5
D
6
P Input high
voltage
C
all digital inputs
P Input low voltage
all digital inputs
C
8
C Input hysteresis
9
P
Input leakage
current
10
P
11
P
12
DC injection
2, 3, 4
D current
13
C Input Capacitance, all pins
14
C RAM retention voltage
VIL
Unit
3.6
V
—
—
2.7 V, ILoad = –10 mA VDD – 0.5
—
—
2.3 V, ILoad = –6 mA
VDD – 0.5
—
—
1.8V, ILoad = –3 mA
VDD – 0.5
—
—
—
—
100
1.8 V, ILoad = 2 mA
—
—
0.5
2.7 V, ILoad = 10 mA
—
—
0.5
2.3 V, ILoad = 6 mA
—
—
0.5
1.8 V, ILoad = 3 mA
—
—
0.5
—
—
100
VDD > 2.7 V
0.70 x VDD
—
—
VDD > 1.8 V
0.85 x VDD
—
—
VDD > 2.7 V
—
—
0.35 x VDD
VDD >1.8 V
—
—
0.30 x VDD
0.06 x VDD
—
—
mV
IOLT
VIH
Max
VDD – 0.5
IOHT
All I/O pins,
low-drive strength
T
7
Min
1.8
T
3
Condition
Operating Voltage
C
2
Characteristic
V
mA
V
mA
V
all digital inputs
Vhys
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
0.1
1
μA
Hi-Z (off-state)
leakage current
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.1
1
μA
Pull-up resistors
all digital inputs, when
enabled
RPU
17.5
—
52.5
kΩ
–0.2
—
0.2
mA
–5
—
5
mA
CIn
—
—
8
pF
VRAM
—
0.6
1.0
V
Single pin limit
Total MCU limit, includes
sum of all stressed pins
5
IIC
VIN < VSS, VIN > VDD
15
C POR re-arm voltage
VPOR
0.9
1.4
2.0
V
16
D POR re-arm time
tPOR
10
—
—
μs
2.08
2.16
2.1
2.19
2.2
2.27
V
17
P
Low-voltage detection threshold —
high range
VLVDH
VDD falling
VDD rising
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
15
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C
4
5
6
Min
Typ1
Max
Unit
Low-voltage detection threshold —
low range
VLVDL
VDD falling
VDD rising
1.80
1.88
1.82
1.90
1.91
1.99
V
19
P
Low-voltage warning threshold —
high range
VLVWH
VDD falling
VDD rising
2.36
2.36
2.46
2.46
2.56
2.56
V
20
P
Low-voltage warning threshold —
low range
VLVWL
VDD falling
VDD rising
2.08
2.16
2.1
2.19
2.2
2.27
V
21
P Low-voltage inhibit reset/recover hysteresis
Vhys
—
80
—
mV
VBG
1.19
1.20
1.21
V
6
P Bandgap Voltage Reference
Typical values are measured at 25°C. Characterized, not tested
All functional non-supply pins are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 3.0 V, Temp = 25°C
PULL-UP RESISTOR TYPICALS
85°C
25°C
–40°C
40
35
30
25
20
1.8
2
2.2
2.4
2.6 2.8
VDD (V)
3
3.2
3.4
3.6
PULL-DOWN RESISTANCE (kΩ)
3
Condition
P
PULL-UP RESISTOR (kΩ)
2
Symbol
18
22
1
Characteristic
40
35
PULL-DOWN RESISTOR TYPICALS
85°C
25°C
–40°C
30
25
20
1.8
2.3
2.8
VDD (V)
3.3
3.6
Figure 7. Pull-up and Pull-down Typical Resistor Values
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
16
Freescale Semiconductor
Electrical Characteristics
TYPICAL VOL VS IOL AT VDD = 3.0 V
1.2
85°C
25°C
–40°C
1
0.15
VOL (V)
0.8
VOL (V)
TYPICAL VOL VS VDD
0.2
0.6
0.4
0.1
85°C, IOL = 2 mA
25°C, IOL = 2 mA
–40°C, IOL = 2 mA
0.05
0.2
0
0
0
5
10
IOL (mA)
15
1
20
2
3
4
VDD (V)
Figure 8. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
TYPICAL VOL VS VDD
TYPICAL VOL VS IOL AT VDD = 3.0 V
1
85°C
25°C
–40°C
0.8
85°C
25°C
–40°C
0.3
0.6
VOL (V)
VOL (V)
0.4
0.4
0.2
0.2
0.1
0
0
IOL = 10 mA
IOL = 6 mA
IOL = 3 mA
0
10
20
30
1
2
3
4
VDD (V)
IOL (mA)
Figure 9. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
1
TYPICAL VDD – VOH VS VDD AT SPEC IOH
0.25
85°C
25°C
–40°C
VDD – VOH (V)
VDD – VOH (V)
1.2
0.8
0.6
0.4
85°C, IOH = 2 mA
25°C, IOH = 2 mA
–40°C, IOH = 2 mA
0.2
0.15
0.1
0.05
0.2
0
0
0
–5
–10
IOH (mA))
–15
–20
1
2
VDD (V)
3
4
Figure 10. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
17
Electrical Characteristics
TYPICAL VDD – VOH VS VDD AT SPEC IOH
TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V
0.8
85°C
25°C
–40°C
0.6
0.4
0.2
0.2
–5
–10
–15
–20
IOH (mA)
–25
IOH = –10 mA
IOH = –6 mA
0.1
0
0
85°C
25°C
–40°C
0.3
VDD – VOH (V)
VDD – VOH (V)
0.4
IOH = –3 mA
0
–30
1
2
3
4
VDD (V)
Figure 11. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num
C
P
1
T
Parameter
Symbol
Run supply current
FEI mode, all modules on
T
C
2
T
Run supply current
FEI mode, all modules off
RIDD
T
T
T
3
Run supply current
LPS=0, all modules off
RIDD
T
T
4
T
C
5
T
T
T
Run supply current
LPS=1, all modules off, running from
Flash
Run supply current
LPS=1, all modules off, running from
RAM
VDD
(V)
Typ1
Max
17.5
TBD
14.4
TBD
6.5
TBD
1 MHz
1.4
TBD
25.165 MHz
11.5
TBD
9.5
TBD
4.6
TBD
1 MHz
1.0
TBD
16 kHz
FBILP
152
25.165 MHz
RIDD
T
Bus
Freq
20 MHz
8 MHz
20 MHz
8 MHz
16 kHz
FBELP
3
3
3
115
Unit
Temp
(°C)
mA
–40 to 85°C
mA
–40 to 85°C
μA
–40 to 85°C
TBD
TBD
TBD
21.9
RIDD
16 kHz
FBELP
3
25.165 MHz
Wait mode supply current
FEI mode, all modules off
WIDD
20 MHz
8 MHz
1 MHz
3
TBD
TBD
7.3
0 to 70°C
–40 to 85°C
μA
TBD
5740
TBD
4570
TBD
2000
TBD
730
TBD
0 to 70°C
–40 to 85°C
μA
–-40 to 85°C
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
18
Freescale Semiconductor
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num
C
Parameter
Symbol
Bus
Freq
Stop2 mode supply current
6
P
S2IDD
P
3
350
2
Stop3 mode supply current
No clocks active
3
S3IDD
n/a
C
3
2
2
250
450
350
8
T
EREFSTEN=1
32 kHz
500
9
T
IREFSTEN=1
32 kHz
70
10
T
TPM PWM
100 Hz
12
11
T
SCI, SPI, or IIC
300 bps
15
Low power
mode adders:
1
Typ1
n/a
C
7
VDD
(V)
3
12
T
RTC using LPO
1 kHz
200
13
T
RTC using
ICSERCLK
32 kHz
1
14
T
LVD
n/a
100
15
T
ACMP
n/a
20
Max
Unit
TBD
TBD
TBD
Temp
(°C)
0 to 70°C
nA
–40 to 85°C
0 to 70°C
TBD
–40 to 85°C
TBD
0 to 70°C
TBD
TBD
nA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
–40 to 85°C
0 to 70°C
–40 to 85°C
nA
μA
μA
μA
nA
μA
μA
μA
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
0 to 70°C
–40 to 85°C
Data in Typical column was characterized at 3.0 V, 25˚C or is typical recommended value.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
19
Electrical Characteristics
TBD
Figure 12. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ACMP and ADC off, All Other Modules Enabled)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
20
Freescale Semiconductor
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Reference Figure 13 and Figure 14 for crystal or resonator circuits.
Table 10. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
D
3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, High Gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
5
6
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Crystal start-up time 4
Low range, low power
C
Low range, high power
High range, low power
High range, high power
D
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
FBE or FBELP mode
Symbol
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
See Note2
See Note3
C1,C2
RF
RS
t
CSTL
t
CSTH
fextal
—
—
—
—
10
1
—
—
—
—
—
—
—
0
100
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
200
400
5
15
—
—
—
—
ms
0.03125
0
—
—
50.33
50.33
MHz
MHz
MΩ
kΩ
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3 See crystal or resonator manufacturer’s recommendation.
4 Proper PC board layout procedures must be followed to achieve specifications.
2
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
21
Electrical Characteristics
XOSC
EXTAL
XTAL
RF
RS
Crystal or Resonator
C1
C2
Figure 13. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 14. Typical Crystal or Resonator Circuit: Low Range/Low Gain
3.9
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Symbol
Min
Typ1
Max
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25°C
fint_ft
—
32.768
—
kHz
P
Internal reference frequency — user trimmed
fint_ut
31.25
—
39.06
kHz
T
Internal reference start-up time
tIRST
—
60
100
μs
16
—
20
32
—
40
High range (DRS=10)
48
—
60
Low range (DRS=00)
—
19.92
—
—
39.85
—
—
59.77
—
Num
C
1
P
2
3
Characteristic
P
4
P
5
Low range (DRS=00)
DCO output frequency range —
C
trimmed 2
P
P
P
DCO output frequency 2
Reference = 32768 Hz
and
DMX32 = 1
Mid range (DRS=01)
Mid range (DRS=01)
fdco_u
fdco_DMX32
High range (DRS=10)
MHz
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
22
Freescale Semiconductor
Electrical Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued)
Symbol
Min
Typ1
Max
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
+ 0.5
-1.0
±2
%fdco
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
tAcquire
—
—
1
ms
CJitter
—
0.02
0.2
%fdco
Num
C
Characteristic
8
C
9
C
10
C FLL acquisition time 3
11
C
Long term jitter of DCO output clock (averaged over 2-ms interval)
4
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
2
TBD
Figure 15. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
23
Electrical Characteristics
TBD
Figure 16. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C)
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 12. Control Timing
Num
C
1
D
2
D
Symbol
Min
Typ1
Max
Unit
Bus frequency (tcyc = 1/fBus)
VDD ≤ 2.1V
VDD > 2.1V
fBus
dc
dc
—
—
10
25.165
MHz
Internal low power oscillator period
tLPO
700
—
1300
μs
Rating
2
3
D
External reset pulse width
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
24
Freescale Semiconductor
Electrical Characteristics
Table 12. Control Timing (continued)
Num
C
8
D
9
10
C
C
Symbol
Min
Typ1
Max
Unit
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
TBD
TBD
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
TBD
TBD
—
—
Stop3 recovery time, from interrupt event to vector fetch
tSTPREC
—
6
10
Rating
ns
ns
μs
1
Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
2
textrst
RESET PIN
Figure 17. Reset Timing
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
25
Electrical Characteristics
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 13. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fBus/4
Hz
2
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
26
Freescale Semiconductor
Electrical Characteristics
3.10.3
SPI Timing
Table 14 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 14. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
1
D
SPSCK period
Master
Slave
2
4
2048
—
tcyc
tcyc
D
Enable lead time
Master
Slave
tLead
2
1/2
1
—
—
tSPSCK
tcyc
D
Enable lag time
Master
Slave
tLag
3
1/2
1
—
—
tSPSCK
tcyc
4
D
Clock (SPSCK) high or low time
Master
Slave
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
D
Data setup time (inputs)
Master
Slave
tSU
5
15
15
—
—
ns
ns
D
Data hold time (inputs)
Master
Slave
tHI
6
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
fop
tSPSCK
tWSPSCK
tv
tHO
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
27
Electrical Characteristics
SS1
(OUTPUT)
2
11
1
SPSCK
(CPOL = 0)
(OUTPUT)
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN2
BIT 6 . . . 1
9
MOSI
(OUTPUT)
LSB IN
10
9
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MSB IN(2)
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT(2)
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
28
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
MSB OUT
SLAVE
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
6
5
MOSI
(INPUT)
10
10
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
12
11
11
12
SPSCK
(CPOL = 0)
(INPUT)
4
4
SPSCK
(CPOL = 1)
(INPUT)
9
MISO
(OUTPUT)
SEE
NOTE
7
MOSI
(INPUT)
SLAVE
8
10
MSB OUT
5
BIT 6 . . . 1
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
29
Electrical Characteristics
3.10.4
Analog Comparator (ACMP) Electricals
Table 15. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
VDD
1.80
—
3.6
V
D
Supply voltage
P
Supply current (active)
IDDAC
—
20
35
μA
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
μA
C
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
3.10.5
ADC Characteristics
Table 16. 12-bit ADC Operating Conditions
C
D
Characteristic
Supply voltage
Conditions
Absolute
Delta to VDD (VDD-VDDAD)2
Min
Typ1
Max
Unit
VDDAD
1.8
—
3.6
V
ΔVDDAD
-100
0
+100
mV
ΔVSSAD
-100
0
+100
mV
D
Ground voltage
D
Ref Voltage High
VREFH
1.8
VDDAD
VDDAD
V
D
Ref Voltage Low
VREFL
VSSAD
VSSAD
VSSAD
V
D
Input Voltage
VADIN
VREFL
—
VREFH
V
C
Input
Capacitance
CADIN
—
4.5
5.5
pF
C
Input Resistance
RADIN
—
5
7
kΩ
—
—
—
—
2
5
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8 bit mode (all valid fADCK)
—
—
10
0.4
—
8.0
0.4
—
4.0
Analog Source
Resistance
C
D
Delta to
VSS (VSS-VSSAD)2
Symb
12 bit mode
fADCK > 4MHz
fADCK < 4MHz
ADC Conversion High Speed (ADLPC=0)
Clock Freq.
Low Power (ADLPC=1)
kΩ
RAS
fADCK
Comment
External to MCU
MHz
1
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
30
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
CAS
+
–
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 25. ADC Input Impedance Equivalency Diagram
Table 17. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C
Symb
Min
Typ1
Max
Unit
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
T
IDDAD
—
120
—
μA
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
T
IDDAD
—
202
—
μA
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
T
IDDAD
—
288
—
μA
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
P
IDDAD
—
0.532
1
mA
IDDAD
—
0.007
0.8
μA
fADACK
2
3.3
5
MHz
1.25
2
3.3
Characteristic
Conditions
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
P
Low Power (ADLPC=1)
C
Comment
tADACK = 1/fADACK
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
31
Electrical Characteristics
Table 17. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
Symb
Min
Typ1
Max
Unit
Comment
P
tADC
—
20
—
—
40
—
ADCK
cycles
—
3.5
—
—
23.5
—
See the ADC
chapter in the
MC9S08QE128
Reference Manual
for conversion time
variances
—
±3.0
—
P
—
±1
±2.5
8 bit mode
T
—
±0.5
1.0
12 bit mode
T
—
±1.75
—
10 bit mode3
P
—
±0.5
±1.0
8 bit mode3
T
—
±0.3
±0.5
12 bit mode
T
—
±1.5
—
10 bit mode
P
—
±0.5
±1.0
8 bit mode
T
—
±0.3
±0.5
—
±1.5
—
Characteristic
Conditions
Conversion Time Short Sample (ADLSMP=0)
(Including
Long Sample (ADLSMP=1)
sample time)
Sample Time
Short Sample (ADLSMP=0)
P
Long Sample (ADLSMP=1)
C
Total Unadjusted 12 bit mode
Error
10 bit mode
Differential
Non-Linearity
Integral
Non-Linearity
C
T
tADS
ETUE
DNL
INL
Zero-Scale Error 12 bit mode
T
10 bit mode
P
—
±0.5
±1.5
8 bit mode
T
—
±0.5
±0.5
12 bit mode
T
—
±1.0
—
10 bit mode
P
—
±0.5
±1
8 bit mode
T
—
±0.5
±0.5
12 bit mode
D
—
-1 to 0
—
10 bit mode
—
—
±0.5
8 bit mode
—
—
±0.5
—
±2
—
10 bit mode
—
±0.2
±4
8 bit mode
—
±0.1
±1.2
—
1.646
—
—
1.769
—
—
701.2
—
Full-Scale Error
Quantization
Error
Input Leakage
Error
Temp Sensor
Slope
Temp Sensor
Voltage
12 bit mode
-40°C to 25°C
D
D
EZS
EFS
EQ
EIL
m
25°C to 85°C
25°C
D
VTEMP2
ADCK
cycles
LSB2
Includes
Quantization
LSB2
LSB2
LSB2
VADIN = VSSAD
LSB2
VADIN = VDDAD
LSB2
LSB2
Pad leakage4 * RAS
mV/°C
mV
5
1
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH - VREFL)/2
3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
32
Freescale Semiconductor
Electrical Characteristics
3.10.6
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section of the MC9S08QE128 Reference Manual.
Table 18. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
Supply voltage for program/erase
-40°C to 85°C
Vprog/erase
1.8
3.6
V
D
Supply voltage for read operation
VRead
1.8
3.6
V
1
D
Internal FCLK frequency
fFCLK
150
200
kHz
D
Internal FCLK period (1/FCLK)
tFcyc
5
6.67
μs
P
Byte program time (random location)(2)
tprog
9
tFcyc
tBurst
4
tFcyc
tPage
4000
tFcyc
tMass
20,000
tFcyc
P
Byte program time (burst
mode)(2)
time2
P
Page erase
P
Mass erase time(2)
Byte program current3
Page erase current
3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
10,000
—
—
100,000
—
—
cycles
15
100
—
years
4
C
Program/erase endurance
TL to TH = –40°C to + 85°C
T = 25°C
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on
how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
3.11
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
33
Electrical Characteristics
3.11.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 19. Radiated Emissions, Electric Field
Parameter
Radiated emissions,
electric field
1
Symbol
VRE_TEM
Conditions
VDD = TBD
TA = +25oC
package type
TBD
Frequency
fOSC/fBUS
Level1
(Max)
0.15 – 50 MHz
TBD
50 – 150 MHz
TBD
Unit
dBμV
150 – 500 MHz
500 – 1000 MHz
TBD crystal
TBD bus
TBD
TBD
IEC Level
TBD
—
SAE Level
TBD
—
Data based on qualification test results.
3.11.2
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20.
Table 20. Conducted Susceptibility, EFT/B
Parameter
Symbol
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
1
VCS_EFT
Conditions
VDD = TBD
TA = +25oC
package type
TBD
fOSC/fBUS
TBD crystal
TBD bus
Result
Amplitude1
(Min)
A
TBD
B
TBD
C
TBD
D
TBD
Unit
kV
Data based on qualification test results. Not tested in production.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
34
Freescale Semiconductor
Ordering Information
The susceptibility performance classification is described in Table 21.
Table 21. Susceptibility Performance Classification
Result
Performance Criteria
A
No failure
B
Self-recovering
failure
C
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
D
Hard failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
E
4
The MCU performs as designed during and after exposure.
The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.
Ordering Information
This section contains ordering information for MC9S08QE128, MC9S08QE96, and MC9S08QE64 devices.
Table 22. Ordering Information
Memory
Freescale Part Number1
Flash
Package2
RAM
MC9S08QE128CLK
MC9S08QE128CLH
MC9S08QE128CFT
80 LQFP
128K
8K
64 LQFP
48 QFN
MC9S08QE128CQD
44 QFP
MC9S08QE96CLK
80 LQFP
MC9S08QE96CLH
MC9S08QE96CFT
96K
6K
64 LQFP
48 QFN
MC9S08QE96CQD
44 QFP
MC9S08QE64CLH
64 LQFP
MC9S08QE64CFT
MC9S08QE64CQD
MC9S08QE64CLC
64K
4K
48 QFN
44 QFP
32 LQFP
1
See the reference manual, MC9S08QE128RM, for a complete description of modules included
on each device.
2
See Table 23 for package information.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
35
Package Information
4.1
Device Numbering System
Example of the device numbering system:
MC 9 S08 QE 128 C XX
Status
(MC = Fully Qualified)
Package designator (see Table 23)
Temperature range
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in Kbytes
Family
5
Package Information
The below table details the various packages available.
Table 23. Package Descriptions
Pin Count
5.1
Package Type
Abbreviation
Designator
Case No.
Document No.
80
Low Quad Flat Package
LQFP
LK
917A
98ASS23237W
64
Low Quad Flat Package
LQFP
LH
840F
98ASS23234W
48
Quad Flat No-Leads
QFN
FT
1314
98ARH99048A
44
Quad Flat Package
QFP
QD
824A
98ASB42839B
32
Low Quad Flat Package
LQFP
LC
873A
98ASH70029A
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 23. For the latest available drawings please
visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
36
Freescale Semiconductor
Package Information
4X
–X–
4X 20 TIPS
0.20 (0.008) H L–M N
X= L, M, N
0.20 (0.008) T L–M N
80
61
1
P
CL
60
AB
AB
G
–M–
VIEW Y
B
–L–
3X
VIEW Y
B1
V
PLATING
J
V1
41
20
21
0.13 (0.005)
A1
M
BASE
METAL
U
T L–M
S
N
S
SECTION AB–AB
S1
ROTATED 90_ CLOCKWISE
A
S
C
8X
q2
0.10 (0.004) T
–H–
–T–
SEATING
PLANE
VIEW AA
(W)
C2
0.05 (0.002)
ÇÇÇ
ÍÍÍÍ
ÍÍÍÍ
ÇÇÇ
D
40
–N–
F
S
q1
0.25 (0.010)
2X R R1
GAGE
PLANE
(K)
C1
E
(Z)
q
VIEW AA
DATE 09/21/95
CASE 917A-02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –L–, –M– AND –N– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –T–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 (0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
S
S1
U
V
V1
W
Z
0
01
02
MILLIMETERS
MIN
MAX
14.00 BSC
7.00 BSC
14.00 BSC
7.00 BSC
–––
1.60
0.04
0.24
1.30
1.50
0.22
0.38
0.40
0.75
0.17
0.33
0.65 BSC
0.09
0.27
0.50 REF
0.325 BSC
0.10
0.20
16.00 BSC
8.00 BSC
0.09
0.16
16.00 BSC
8.00 BSC
0.20 REF
1.00 REF
0_
10_
0_
–––
9_
14_
INCHES
MIN
MAX
0.551 BSC
0.276 BSC
0.551 BSC
0.276 BSC
–––
0.063
0.002
0.009
0.051
0.059
0.009
0.015
0.016
0.030
0.007
0.013
0.026 BSC
0.004
0.011
0.020 REF
0.013 REF
0.004
0.008
0.630 BSC
0.315 BSC
0.004
0.006
0.630 BSC
0.315 BSC
0.008 REF
0.039 REF
0_
10_
0_
–––
9_
14_
Figure 26. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
37
Package Information
Figure 27. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
38
Freescale Semiconductor
Package Information
Figure 28. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
39
Package Information
Figure 29. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
40
Freescale Semiconductor
Package Information
Figure 30. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 1 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
41
Package Information
Figure 31. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 2 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
42
Freescale Semiconductor
Package Information
Figure 32. 48-pin QFN Package Drawing (Case 1314, Doc #98ARH99048A), Sheet 3 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
43
Package Information
Figure 33. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 1 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
44
Freescale Semiconductor
Package Information
Figure 34. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 2 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
45
Package Information
Figure 35. 44-pin QFP Package Drawing (Case 824A, Doc #98ASB42839B), Sheet 3 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
46
Freescale Semiconductor
Package Information
Figure 36. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 1 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
47
Package Information
Figure 37. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 2 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
48
Freescale Semiconductor
Package Information
Figure 38. 32-pin LQFP Package Drawing (Case 873A, Doc #98ASH70029A), Sheet 3 of 3
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
49
Product Documentation
6
Product Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08QE128RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
7
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Table 24. Revision History
Revision
Date
3
25 Jun 2007
Description of Changes
Initial public Advance Information release.
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
50
Freescale Semiconductor
Revision History
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
51
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Document Number: MC9S08QE128
Rev. 3
06/2007
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