FUJITSU MB96390

FUJITSU SEMICONDUCTOR
DATA SHEET
FME-MB96390 rev 3
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96390 Series
Y
MB96F395*1
AR
■ DESCRIPTION
MB96390 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
IM
IN
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 40MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 25ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
PR
EL
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
MB96390 Series
■ FEATURES
Feature
Technology
Description
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 40 MHz internal, 25 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
Y
CPU
• 8-byte instruction execution queue
AR
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 40 MHz external clock
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
IN
System clock
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Clock modulator
IM
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
Low voltage reset
Code Security
Memory Patch Function
EL
On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
tor
and low power consumption figures
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
• Can also be used to implement embedded debug support
Interrupts
PR
• Fast Interrupt processing
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
Timers
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
2
FME-MB96390 rev 3
MB96390 Series
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
Y
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
AR
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
USART
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
IN
• Up to 400 kbps
I2C
• Master and Slave functionality, 7-bit and 10-bit addressing
• SAR-type
A/D converter
• 10-bit resolution
• 16-bit wide
Reload Timers
IM
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
Free Running Timers
EL
• Event count function
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of
peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
PR
Input Capture Units
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse
Generator
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer underflow as clock input
• Can be triggered by software or reload timer
FME-MB96390 rev 3
3
MB96390 Series
Feature
Description
• Stepper Motor Controller with integrated high current output drivers
• Four high current outputs for each channel
Stepper Motor Control- • Two synchronized 8/10-bit PWMs per channel
ler
• Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral
clock
• LCD controller with up to 4 COM × SEG
• Internal or external voltage generation
Y
• Separate power supply for high current output drivers
• Fixed 1/3 bias
• Programmable frame period
AR
• Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
• Clock source selectable from three options (peripheral clock, subclock or RC
oscillator clock)
LCD Controller
• On-chip drivers for internal divider resistors or external divider resistors
IN
• On-chip data memory for display
• LCD display can be operated in Timer Mode
• Blank display: selectable
IM
• All SEG, COM and V pins can be switched between general and specialized
purposes
• External divided resistors can be also used to shut off the current when LCD is
deactivated
• 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
• PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock
EL
Sound Generator
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
Real Time Clock
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
PR
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• Edge sensitive or level sensitive
External Interrupts
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
Non Maskable Interrupt
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
• Pin shared with external interrupt 0.
4
FME-MB96390 rev 3
MB96390 Series
Feature
Description
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Alarm comparator
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
I/O Ports
• Bit-wise programmable input enable
Y
• Bit-wise programmable as input/output or peripheral signal
AR
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
Packages
• 100-pin plastic LQFP
• Supports automatic programming, Embedded Algorithm
IN
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
Flash Memory
• Data retention time: 20 years
IM
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
PR
EL
• Low voltage detection during Flash erase
FME-MB96390 rev 3
5
MB96390 Series
■ PRODUCT LINEUP
Features
MB96V300B
MB96(F)39x
Product type
Evaluation sample
Flash product: MB96F39x
Mask ROM product: MB9639x
Product options
Low voltage reset persistently on / Single clock devices
Y
YS
RS
Low voltage reset can be disabled / Single clock devices
NA
Low voltage reset persistently on / Dual clock devices
RW
Low voltage reset can be disabled / Dual clock devices
RAM
5KB
BGA416
DMA
16 channels
USART
10 channels
I2C
2 channels
A/D Converter
40 channels
A/D Converter Reference
Voltage switch
yes
EL
Package
FPT-100P-M20
0 channels
3 channels
1 channel
11 channels
No
6 channels + 1
channel (for PPG)
4 channels + 1 channel (for PPG)
16-bit Free-Running Timer
4 channels
2 channels
16-bit Output Compare
12 channels
4 channels
PR
16-bit Reload Timer
16-bit Input Capture
12 channels
4 channels
16-bit Programmable Pulse
Generator
20 channels
4 channels
CAN Interface
5 channels
1 channels
Stepping Motor Controller
6 channels
4 channels
External Interrupts
16 channels
8 channels
Non-Maskable Interrupt
1 channel
Sound generator
2 channels
1 channels
LCD Controller
4 COM x 72 SEG
4 COM x 49 SEG
Real Time Clock
6
MB96F395Y*1, MB96F395R*1,
IN
160KB
ROM/Flash
memory emulation
by external RAM,
92KB internal RAM
IM
Flash/ROM
AR
YW
1
FME-MB96390 rev 3
MB96390 Series
Features
MB96V300B
MB96(F)39x
I/O Ports
136
74 for part number with suffix "W", 76 for part number with suffix "S"
Alarm comparator
2 channels
1 channels
External bus interface
Yes
No
2 channels
Low voltage reset
Yes
Y
Clock output function
On-chip RC-oscillator
Yes
PR
EL
IM
IN
AR
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
FME-MB96390 rev 3
7
MB96390 Series
■ BLOCK DIAGRAMS
Block diagram of MB96F39x
CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
Interrupt
Controller
16FX Core Bus (CLKB)
FRCK0
FRCK0_R
IN0
IN0_R,IN1_R
OUT0 ... OUT3
OUT0_R,OUT2_R
FRCK1
IN6,IN7
IN7_R
INT0 ... INT7
INT1_R ... INT7_R
V0 ... V3
COM0 ... COM3
SEG0 ... SEG64
(Except 5,6,8,9,10,
29,31,32,34,35,48
49,50,54,58,62)
8
16-bit Reload
Timer
4 ch.
I/O Timer 0
ICU 0/1
OCU 0/1/2/3
I/O Timer 1
ICU 6/7
External
Interrupt
LCD
controller/
driver
RAM
IN
IM
TIN0, TIN1
TIN2, TIN3
TOT0, TOT1
TOT2, TOT3
10-bit ADC
11 ch.
EL
AVCC
AVSS
AVRH
AVRL
AN2,3,4,6,7,8,10
AN11,12,14,15
ADTG
I2C
1 ch.
Peripheral Bus 1 (CLKP1)
SCL0
PR
SDA0
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
Peripheral
Bus Bridge
Watchdog
USART
3 ch.
Alarm
Comparator
1 ch.
16-bit PPG
4 ch.
RLT6
Clock &
Mode Controller
Memory Patch
Unit
Flash
Memory A
AR
16FX
CPU
Y
NMI
CAN
Interface
1 ch.
Sound
Generator
1 ch.
Boot ROM
Voltage
Regulator
VCC
VSS
C
TX0
RX0
SGO0
SGA0
SIN0...SIN2
SOT0...SOT2
SCK0...SCK2
ALARM0
TTG0,TTG2,TTG3
PPG0,PPG1,PPG3
PPG0_R ... PPG3_R
Stepper
Motor
Controller
4 ch.
PWM1M0 ... PWM1M2,PWM1M4
PWM1P0 ... PWM1P2,PWM1P4
PWM2M0 ... PWM2M2,PWM2M4
PWM2P0 ... PWM2P2,PWM2P4
DVCC
DVSS
Real Time
Clock
WOT
*1: X0A, X1A only available on devices with suffix “W”
FME-MB96390 rev 3
MB96390 Series
■ PIN ASSIGNMENTS
84
P01_7/CKOTX1_R/SEG27
P02_0/CKOT1_R/SEG28
P02_2/CKOT0_R/IN7_R/SEG30
P02_5/OUT0_R/SEG33
89
P03_0/V0/SEG36
P03_1/V1/SEG37
P03_2/V2/SEG38
P03_3/V3/SEG39
P03_4/INT4/RX0
P03_5/TX0
P03_6/NMI/INT0
Vcc
93
Y
43
P09_3/PWM2M2
42
P09_2/PWM2P2
P09_1/PWM1M2
48
47
80
46
81
45
82
83
IN
LQFP - 100
85
86
87
41
40
39
Package code (mold)
FPT-100P-M20
88
90
38
37
36
35
IM
91
92
94
95
96
97
98
EL
99
100
44
Vcc
P10_3/PWM2M4
P10_2/PWM2P4/SCK2
P10_1/PWM1M4/SOT2/TOT3
P10_0/PWM1P4/SIN2/TIN3
DVss
DVcc
50
49
2
3
4
5
6
7
8
PR
33
32
31
30
29
P08_5/PWM1M1
DVss
DVcc
P08_4/PWM1P1
P08_3/PWM2M0
P08_2/PWM2P0
P08_1/PWM1M0
P08_0/PWM1P0
P05_7/AN15/TOT2/SEG64
27
P05_6/AN14/TIN2/SEG63
P05_4/AN12/INT2_R/SEG61
26
Vss
28
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Vss
C
P03_7/INT1/SIN1/SEG40
P13_0/INT2/SOT1/SEG41
P13_1/INT3/SCK1/SEG42
P13_2/PPG0/TIN0/FRCK1/SEG43
P13_3/PPG1/TOT0/WOT/SEG44
P13_4/SIN0/INT6/SEG45
P13_5/SOT0/ADTG/INT7/SEG46
P13_6/SCK0/CKOTX0/SEG47
P04_4/PPG3/SDA0
P04_5/SCL0
P06_2/AN2/INT5/SEG51
P06_3/AN3/FRCK0/SEG52
1
34
P09_0/PWM1P2
P08_7/PWM2M1
P08_6/PWM2P1
P05_3/AN11/OUT3/SEG60
Vcc
P01_2/OUT1/CKOTX1/SEG22
P01_3/SEG23
P01_4/SEG24
P01_5/SEG25
P01_6/SEG26
78
P05_2/AN10/OUT2/SEG59
79
AR
P00_5/TTG2/IN6/SEG17
P00_6/TTG3/IN7/SEG18
P00_7/SGO0/SEG19
P01_0/SGA0/SEG20
P01_1/OUT0/CKOT1/SEG21
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
77
AVRL
AVss
P05_0/AN8/ALARM0/SEG57
76
P06_4/AN4/IN0/TTG0/SEG53
P06_6/AN6/TIN1/SEG55
P06_7/AN7/TOT1/SEG56
AVcc
AVRH
Vss
P00_3/INT6_R/SEG15
P00_4/INT7_R/SEG16
P00_1/INT4_R/SEG13
P00_0/INT3_R/SEG12
P12_7/INT1_R/SEG11
P12_3/OUT2_R/SEG7
P12_0/IN1_R/SEG4
P11_7/IN0_R/SEG3
P11_6/FRCK0_R/SEG2
P11_5/SEG1
P11_4/PPG3_R/SEG0
P11_3/PPG2_R/COM3
P11_2/PPG1_R/COM2
P11_1/PPG0_R/COM1
P11_0/COM0
RSTX
X1A/P04_1 *1
X0A/P04_0 *1
Vss
X1
X0
MD2
MD1
MD0
Vss
Vcc
P00_2/INT5_R/SEG14
Pin assignment of MB96F39x
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
(FPT-100P-M20)
FME-MB96390 rev 3
9
MB96390 Series
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 of 2)
Feature
Description
ADTG
ADC
A/D converter trigger input
ALARMn
Alarm comparator
Alarm Comparator n input
ANn
ADC
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
ADC
A/D converter high reference voltage input
AVRL
ADC
A/D converter low reference voltage input
AVSS
Supply
Analog circuits power supply
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock output function
Clock Output function n output
CKOTn_R
Clock output function
CKOTXn
Clock output function
CKOTXn_R
Clock output function
Relocated Clock Output function n inverted output
COMn
LCD
LCD COM pins
DVCC
Supply
FRCKn
Free Running Timer
FRCKn_R
Free Running Timer
INn
ICU
INn_R
ICU
INTn
External Interrupt
External Interrupt n input
INTn_R
External Interrupt
Relocated External Interrupt n input
AR
IN
Relocated Clock Output function n output
IM
Clock Output function n inverted output
SMC pins power supply
Free Running Timer n input
EL
Relocated Free Running Timer n input
Input Capture Unit n input
Relocated Input Capture Unit n input
Core
Input pins for specifying the operating mode.
NMI
External Interrupt
Non-Maskable Interrupt input
OUTn
OCU
Output Compare Unit n waveform output
OCU
Relocated Output Compare Unit n waveform output
GPIO
General purpose IO
PPGn
PPG
Programmable Pulse Generator n output
PPGn_R
PPG
Relocated Programmable Pulse Generator n output
PWMn
SMC
SMC PWM high current
RSTX
Core
Reset input
OUTn_R
Pxx_n
10
PR
MDn
Y
Pin name
FME-MB96390 rev 3
MB96390 Series
Pin Function description (2 of 2)
Feature
Description
RXn
CAN
CAN interface n RX input
SCKn
USART
USART n serial clock input/output
SCLn
I2C
I2C interface n clock I/O input/output
SDAn
I2C
I2C interface n serial data I/O input/output
SEGn
LCD
SGA
Sound Generator
SGO
Sound Generator
SINn
USART
SOTn
USART
TINn
Reload Timer
TOTn
Reload Timer
TTGn
PPG
TXn
CAN
Vn
LCD
VCC
Supply
VSS
Supply
WOT
RTC
X0
Clock
X0A
Clock
Subclock Oscillator input (only for devices with suffix "W")
X1
Clock
Oscillator output
X1A
Clock
Subclock Oscillator output (only for devices with suffix "W")
Y
Pin name
LCD segment n
AR
SG amplitude output
SG sound/tone output
USART n serial data input
USART n serial data output
IN
Reload Timer n event input
Reload Timer n output
CAN interface n TX output
LCD voltage references
Power supply
Power supply
Real Timer clock output
Oscillator input
PR
EL
IM
Programmable Pulse Generator n trigger input
FME-MB96390 rev 3
11
MB96390 Series
■ PIN CIRCUIT TYPE
Pin circuit types (1 of 2)
F
3 to 10
J
11,12
N
13 to 17
K
18
Supply
19 to 20
G
21
Supply
22 to 24
K
25,26
Supply
27 to 29
K
30 to 34
M
35,36
Supply
37 to 43
M
44,45
Supply
46 to 49
M
50, 51
Supply
52 to 54
C
55, 56
A
57
Supply
58,59
B *2)
58,59
H *3
60
E
61 to 74
J
75 to 76
Supply
77 to 92
J
93 to 96
L
12
AR
2
IN
Supply
IM
1
EL
Circuit
type *1
PR
Pin no.
Y
FPT-100P-M20
FME-MB96390 rev 3
MB96390 Series
Pin circuit types (2 of 2)
FPT-100P-M20
Circuit
type *1
97 to 99
H
100
Supply
Y
Pin no.
PR
EL
IM
IN
AR
*1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types
*2: Devices with suffix ”W”
*3: Devices without suffix ”W”
FME-MB96390 rev 3
13
MB96390 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Y
X1
R
0
AR
Xout
MRFBE
1
FCI
R
High-speed oscillation circuit:
• Programmable between oscillation mode (external crystal or resonator connected to X0/X1
pins) and Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
X0
IN
FCI or osc disable
B
Xout
X1A
IM
R
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 MΩ. Feedback resistor is grounded in the
center when the oscillator is disabled
EL
SRFBE
R
X0A
osc disable
PR
C
R
E
Hysteresis
inputs
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
14
Hysteresis
inputs
FME-MB96390 rev 3
MB96390 Series
Type
Circuit
Remarks
• Power supply input protection circuit
G
• A/D converter ref+ (AVRH/AVRH2) power supply input pin with protection circuit
• Flash devices do not have a protection circuit
against VCC for pins AVRH/AVRH2
• Devices without AVRH reference switch do not
have an analog switch for the AVRL pin
AVR
ANE
pull-up control
IM
Pout
Nout
R
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
PR
Standby control
for input shutdown
EL
Standby control
for input shutdown
Standby control
for input shutdown
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
IN
H
AR
ANE
Y
F
FME-MB96390 rev 3
15
MB96390 Series
Type
Circuit
Remarks
J
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• SEG or COM output
pull-up control
Pout
Y
Nout
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
IN
Standby control
for input shutdown
AR
R
SEG, COM output
IM
K
pull-up control
EL
Pout
Nout
R
PR
Standby control
for input shutdown
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• SEG output
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
Analog input
SEG output
16
FME-MB96390 rev 3
MB96390 Series
Circuit
Remarks
L
pull-up control
Pout
Nout
R
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
IN
AR
Standby control
for input shutdown
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• Vx input
• SEG output
Y
Type
Analog input
SEG output
IM
Vx input
M
pull-up control
EL
Pout
Nout
R
PR
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
FME-MB96390 rev 3
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL =
30mA, IOH = -30mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
17
MB96390 Series
Type
Circuit
Remarks
N
• CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Y
Nout *1
*1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
PR
EL
IM
IN
Standby control
for input shutdown
AR
R
18
FME-MB96390 rev 3
MB96390 Series
■ MEMORY MAP
MB96V300B
MB96F39x
Emulation ROM
USER ROM /
Reserved*4
External Bus
Reserved
FF:FFFFH
AR
Y
DE:0000H
10:0000H
0F:E000H
Boot-ROM
Boot-ROM
Reserved
0E:0000H
IN
External RAM
02:0000H
01:0000H
IM
Internal RAM
bank 1
ROM/RAM MIRROR
00:8000H
RAMSTART0*3
00:0C00H
RAMSTART0
EL
Internal RAM
bank 0
PR
00:0180H
00:0100H
00:00F0H
00:0000H
ROM/RAM MIRROR
*2
Internal RAM
bank 0
Reserved
External Bus
Peripherals
00:0380H
Reserved
Peripherals
GPR*1
GPR*1
DMA
Reserved
External Bus
Reserved
Peripheral
Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For RAMSTART0 addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the ■ USER ROM MEMORY MAP FOR FLASH DEVICES on the
following pages.
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
FME-MB96390 rev 3
19
MB96390 Series
■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Bank 0 RAM size
RAMSTART0
MB96F395
5KByte
00:6E40H
PR
EL
IM
IN
AR
Y
Devices
20
FME-MB96390 rev 3
MB96390 Series
■ USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F395R
MB96F395Y
E0:0000H
DF:FFFFH
DE:0000H
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
Reserved
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
EL
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
S39 - 64K
S38 - 64K
Y
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
AR
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
Flash size
160kByte
IN
Flash memory
mode address
IM
Alternative mode
CPU address
Reserved
PR
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
FME-MB96390 rev 3
21
MB96390 Series
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode)
MB96F39x
Pin number
USART Number
Normal function
LQFP-100
SOT0
10
SCK0
3
SIN1
4
USART1
SOT1
5
SCK1
46
SIN2
47
48
USART2
Y
USART0
AR
9
SIN0
SOT2
SCK2
IN
8
PR
EL
IM
Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor
to support at least port P00_1 on pin 88.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
22
FME-MB96390 rev 3
MB96390 Series
■ I/O MAP
I/O map MB96F39x (1 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
I/O Port P00 - Port Data Register
PDR00
R/W
000001H
I/O Port P01 - Port Data Register
PDR01
R/W
000002H
I/O Port P02 - Port Data Register
PDR02
R/W
000003H
I/O Port P03 - Port Data Register
PDR03
R/W
000004H
I/O Port P04 - Port Data Register
PDR04
R/W
000005H
I/O Port P05 - Port Data Register
PDR05
R/W
000006H
I/O Port P06 - Port Data Register
PDR06
R/W
000007H
Reserved
000008H
I/O Port P08 - Port Data Register
000009H
I/O Port P09 - Port Data Register
00000AH
I/O Port P10 - Port Data Register
00000BH
I/O Port P11 - Port Data Register
00000CH
AR
Y
000000H
R/W
PDR09
R/W
PDR10
R/W
PDR11
R/W
I/O Port P12 - Port Data Register
PDR12
R/W
00000DH
I/O Port P13 - Port Data Register
PDR13
R/W
00000EH000017H
Reserved
000018H
ADC0 - Control Status register Low
ADCSL
000019H
ADC0 - Control Status register High
ADCSH
00001AH
ADC0 - Data Register Low
ADCRL
00001BH
ADC0 - Data Register High
ADCRH
00001CH
ADC0 - Setting Register
00001DH
ADC0 - Setting Register
00001EH
ADC0 - Extended Configuration Register
00001FH
Reserved
000020H
FRT0 - Data register of free-running timer
000021H
FRT0 - Data register of free-running timer
000022H
FRT0 - Control status register of free-running timer
Low
TCCSL0
000023H
FRT0 - Control status register of free-running timer
High
TCCSH0
PR
EL
IM
IN
PDR08
FME-MB96390 rev 3
ADCS
R/W
R/W
ADCR
R
R
ADSR
R/W
R/W
ADECR
R/W
TCDT0
R/W
R/W
TCCS0
R/W
R/W
23
MB96390 Series
I/O map MB96F39x (2 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
TCDT1
R/W
000024H
FRT1 - Data register of free-running timer
000025H
FRT1 - Data register of free-running timer
000026H
FRT1 - Control status register of free-running timer
Low
TCCSL1
000027H
FRT1 - Control status register of free-running timer
High
TCCSH1
R/W
000028H
OCU0 - Output Compare Control Status
OCS0
R/W
000029H
OCU1 - Output Compare Control Status
OCS1
R/W
00002AH
OCU0 - Compare Register
00002BH
OCU0 - Compare Register
00002CH
OCU1 - Compare Register
00002DH
OCU1 - Compare Register
00002EH
OCU2 - Output Compare Control Status
00002FH
OCU3 - Output Compare Control Status
000030H
OCU2 - Compare Register
000031H
OCU2 - Compare Register
000032H
OCU3 - Compare Register
000033H
OCU3 - Compare Register
000034H00003FH
Reserved
000040H
ICU0/ICU1 - Control Status Register
ICS01
R/W
000041H
ICU0/ICU1 - Edge register
ICE01
R/W
000042H
ICU0 - Capture Register Low
IPCPL0
000043H
ICU0 - Capture Register High
IPCPH0
000044H
ICU1 - Capture Register Low
IPCPL1
000045H
ICU1 - Capture Register High
IPCPH1
000046H000051H
Reserved
000052H
ICU6/ICU7 - Control Status Register
ICS67
R/W
000053H
ICU6/ICU7 - Edge register
ICE67
R/W
000054H
ICU6 - Capture Register Low
24
R/W
R/W
Y
R/W
OCCP1
IN
AR
OCCP0
R/W
R/W
R/W
OCS2
R/W
OCS3
R/W
IM
EL
PR
TCCS1
OCCP2
R/W
R/W
OCCP3
R/W
R/W
-
IPCP0
R
R
IPCP1
R
R
-
IPCPL6
IPCP6
R
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (3 of 22)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
000055H
ICU6 - Capture Register High
IPCPH6
000056H
ICU7 - Capture Register Low
IPCPL7
000057H
ICU7 - Capture Register High
IPCPH7
R
000058H
EXTINT0 - External Interrupt Enable Register
ENIR0
R/W
000059H
EXTINT0 - External Interrupt Interrupt request
Register
00005AH
EXTINT0 - External Interrupt Level Select Low
ELVRL0
00005BH
EXTINT0 - External Interrupt Level Select High
ELVRH0
00005CH00005FH
Reserved
000060H
RLT0 - Timer Control Status Register Low
000061H
RLT0 - Timer Control Status Register High
000062H
RLT0 - Reload Register - for writing
TMRLR0
W
000062H
RLT0 - Reload Register - for reading
TMR0
R
000063H
RLT0 - Reload Register - for writing
W
000063H
RLT0 - Reload Register - for reading
R
000064H
RLT1 - Timer Control Status Register Low
TMCSRL1
000065H
RLT1 - Timer Control Status Register High
TMCSRH1
000066H
RLT1 - Reload Register - for writing
TMRLR1
W
000066H
RLT1 - Reload Register - for reading
TMR1
R
000067H
RLT1 - Reload Register - for writing
W
000067H
RLT1 - Reload Register - for reading
R
000068H
RLT2 - Timer Control Status Register Low
TMCSRL2
000069H
RLT2 - Timer Control Status Register High
TMCSRH2
00006AH
RLT2 - Reload Register - for writing
TMRLR2
W
00006AH
RLT2 - Reload Register - for reading
TMR2
R
00006BH
RLT2 - Reload Register - for writing
W
00006BH
RLT2 - Reload Register - for reading
R
00006CH
RLT3 - Timer Control Status Register Low
TMCSRL3
00006DH
RLT3 - Timer Control Status Register High
TMCSRH3
00006EH
RLT3 - Reload Register - for writing
IPCP7
Y
AR
IN
IM
EL
PR
FME-MB96390 rev 3
R
EIRR0
TMCSRL0
Access
R
R/W
ELVR0
R/W
R/W
-
TMCSR0
TMCSRH0
R/W
R/W
TMCSR1
R/W
R/W
TMCSR2
R/W
R/W
TMCSR3
R/W
R/W
TMRLR3
W
25
MB96390 Series
I/O map MB96F39x (4 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
TMR3
R
00006EH
RLT3 - Reload Register - for reading
00006FH
RLT3 - Reload Register - for writing
W
00006FH
RLT3 - Reload Register - for reading
R
000070H
RLT6 - Timer Control Status Register Low (dedic.
RLT for PPG)
TMCSRL6
000071H
RLT6 - Timer Control Status Register High (dedic.
RLT for PPG)
TMCSRH6
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
TMRLR6
W
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
TMR6
R
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
W
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
R
000074H
PPG3-PPG0 - General Control register 1 Low
000075H
PPG3-PPG0 - General Control register 1 High
GCN1H0
000076H
PPG3-PPG0 - General Control register 2 Low
GCN2L0
000077H
PPG3-PPG0 - General Control register 2 High
GCN2H0
000078H
PPG0 - Timer register
000079H
PPG0 - Timer register
00007AH
PPG0 - Period setting register
00007BH
PPG0 - Period setting register
00007CH
PPG0 - Duty cycle register
00007DH
PPG0 - Duty cycle register
00007EH
PPG0 - Control status register Low
PCNL0
00007FH
PPG0 - Control status register High
PCNH0
000080H
PPG1 - Timer register
000081H
PPG1 - Timer register
000082H
PPG1 - Period setting register
000083H
PPG1 - Period setting register
000084H
PPG1 - Duty cycle register
26
Y
AR
IN
IM
GCN1L0
R/W
R/W
GCN10
R/W
R/W
GCN20
R/W
R/W
PTMR0
EL
PR
TMCSR6
R
R
PCSR0
W
W
PDUT0
W
W
PCN0
R/W
R/W
PTMR1
R
R
PCSR1
W
W
PDUT1
W
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (5 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
000085H
PPG1 - Duty cycle register
W
000086H
PPG1 - Control status register Low
PCNL1
000087H
PPG1 - Control status register High
PCNH1
000088H
PPG2 - Timer register
000089H
PPG2 - Timer register
00008AH
PPG2 - Period setting register
00008BH
PPG2 - Period setting register
00008CH
PPG2 - Duty cycle register
00008DH
PPG2 - Duty cycle register
00008EH
PPG2 - Control status register Low
00008FH
PPG2 - Control status register High
000090H
PPG3 - Timer register
000091H
PPG3 - Timer register
000092H
PPG3 - Period setting register
000093H
PPG3 - Period setting register
000094H
PPG3 - Duty cycle register
000095H
PPG3 - Duty cycle register
000096H
PPG3 - Control status register Low
PCNL3
000097H
PPG3 - Control status register High
PCNH3
000098H0000ABH
Reserved
0000ACH
I2C0 - Bus Status Register
IBSR0
R
0000ADH
I2C0 - Bus Control Register
IBCR0
R/W
0000AEH
I2C0 - Ten bit Slave address Register Low
ITBAL0
0000AFH
I2C0 - Ten bit Slave address Register High
ITBAH0
0000B0H
I2C0 - Ten bit Address mask Register Low
ITMKL0
0000B1H
I2C0 - Ten bit Address mask Register High
ITMKH0
R/W
0000B2H
I2C0 - Seven bit Slave address Register
ISBA0
R/W
0000B3H
I2C0 - Seven bit Address mask Register
ISMK0
R/W
0000B4H
I2C0 - Data Register
IDAR0
R/W
Y
AR
EL
R
R
PCSR2
W
W
PDUT2
W
W
PCN2
PCNH2
R/W
R/W
PTMR3
R
R
PCSR3
IM
IN
PCNL2
R/W
R/W
PTMR2
PR
FME-MB96390 rev 3
PCN1
W
W
PDUT3
W
W
PCN3
R/W
R/W
-
ITBA0
R/W
R/W
ITMK0
R/W
27
MB96390 Series
I/O map MB96F39x (6 of 22)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
0000B5H
I2C0 - Clock Control Register
0000B6H0000BFH
Reserved
0000C0H
USART0 - Serial Mode Register
SMR0
0000C1H
USART0 - Serial Control Register
SCR0
R/W
0000C2H
USART0 - TX Register
TDR0
W
0000C2H
USART0 - RX Register
0000C3H
USART0 - Serial Status
0000C4H
USART0 - Control/Com. Register
0000C5H
USART0 - Ext. Status Register
0000C6H
USART0 - Baud Rate Generator Register Low
0000C7H
USART0 - Baud Rate Generator Register High
BGRH0
R/W
0000C8H
USART0 - Extended Serial Interrupt Register
ESIR0
R/W
0000C9H
Reserved
0000CAH
USART1 - Serial Mode Register
SMR1
R/W
0000CBH
USART1 - Serial Control Register
SCR1
R/W
0000CCH
USART1 - TX Register
TDR1
W
0000CCH
USART1 - RX Register
RDR1
R
0000CDH
USART1 - Serial Status
SSR1
R/W
0000CEH
USART1 - Control/Com. Register
ECCR1
R/W
0000CFH
USART1 - Ext. Status Register
ESCR1
R/W
0000D0H
USART1 - Baud Rate Generator Register Low
BGRL1
0000D1H
USART1 - Baud Rate Generator Register High
BGRH1
R/W
0000D2H
USART1 - Extended Serial Interrupt Register
ESIR1
R/W
0000D3H
Reserved
0000D4H
USART2 - Serial Mode Register
SMR2
R/W
0000D5H
USART2 - Serial Control Register
SCR2
R/W
0000D6H
USART2 - TX Register
TDR2
W
0000D6H
USART2 - RX Register
RDR2
R
0000D7H
USART2 - Serial Status
SSR2
R/W
28
ICCR0
Access
R/W
-
AR
Y
R/W
RDR0
R
SSR0
R/W
ECCR0
R/W
ESCR0
R/W
BGR0
PR
EL
IM
IN
BGRL0
R/W
-
BGR1
R/W
-
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (7 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
0000D8H
USART2 - Control/Com. Register
ECCR2
R/W
0000D9H
USART2 - Ext. Status Register
ESCR2
R/W
0000DAH
USART2 - Baud Rate Generator Register Low
BGRL2
0000DBH
USART2 - Baud Rate Generator Register High
BGRH2
0000DCH
USART2 - Extended Serial Interrupt Register
0000DDH00017FH
Reserved
000180H00037FH
CPU - General Purpose registers (RAM access)
000380H00039FH
Reserved
0003A0H
Interrupt level register
0003A1H
Interrupt index register
0003A2H
Interrupt vector table base register Low
TBRL
0003A3H
Interrupt vector table base register High
TBRH
R/W
0003A4H
Delayed Interrupt register
DIRR
R/W
0003A5H
Non Maskable Interrupt register
NMI
R/W
0003A6H0003ABH
Reserved
0003ACH
EDSU communication interrupt selection Low
EDSU2L
0003ADH
EDSU communication interrupt selection High
EDSU2H
R/W
0003AEH
ROM mirror control register
ROMM
R/W
0003AFH
EDSU configuration register
EDSU
R/W
0003B0H
Memory patch control/status register ch 0/1
0003B1H
Memory patch control/status register ch 0/1
0003B2H
Memory patch control/status register ch 2/3
0003B3H
Memory patch control/status register ch 2/3
0003B4H
Memory patch control/status register ch 4/5
0003B5H
Memory patch control/status register ch 4/5
0003B6H
Memory patch control/status register ch 6/7
0003B7H
Memory patch control/status register ch 6/7
Y
R/W
-
GPR_RAM
ILR
R/W
R/W
ESIR2
AR
IN
IM
EL
PR
FME-MB96390 rev 3
BGR2
R/W
ICR
IDX
R/W
R/W
TBR
R/W
EDSU2
PFCS0
R/W
R/W
R/W
PFCS1
R/W
R/W
PFCS2
R/W
R/W
PFCS3
R/W
R/W
29
MB96390 Series
I/O map MB96F39x (8 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
Memory Patch function - Patch address 0 low
PFAL0
R/W
0003B9H
Memory Patch function - Patch address 0 middle
PFAM0
R/W
0003BAH
Memory Patch function - Patch address 0 high
PFAH0
R/W
0003BBH
Memory Patch function - Patch address 1 low
PFAL1
R/W
0003BCH
Memory Patch function - Patch address 1 middle
PFAM1
R/W
0003BDH
Memory Patch function - Patch address 1 high
PFAH1
R/W
0003BEH
Memory Patch function - Patch address 2 low
0003BFH
Memory Patch function - Patch address 2 middle
0003C0H
Memory Patch function - Patch address 2 high
0003C1H
Memory Patch function - Patch address 3 low
0003C2H
Memory Patch function - Patch address 3 middle
0003C3H
AR
Y
0003B8H
R/W
PFAM2
R/W
PFAH2
R/W
PFAL3
R/W
PFAM3
R/W
Memory Patch function - Patch address 3 high
PFAH3
R/W
0003C4H
Memory Patch function - Patch address 4 low
PFAL4
R/W
0003C5H
Memory Patch function - Patch address 4 middle
PFAM4
R/W
0003C6H
Memory Patch function - Patch address 4 high
PFAH4
R/W
0003C7H
Memory Patch function - Patch address 5 low
PFAL5
R/W
0003C8H
Memory Patch function - Patch address 5 middle
PFAM5
R/W
0003C9H
Memory Patch function - Patch address 5 high
PFAH5
R/W
0003CAH
Memory Patch function - Patch address 6 low
PFAL6
R/W
0003CBH
Memory Patch function - Patch address 6 middle
PFAM6
R/W
0003CCH
Memory Patch function - Patch address 6 high
PFAH6
R/W
0003CDH
Memory Patch function - Patch address 7 low
PFAL7
R/W
0003CEH
Memory Patch function - Patch address 7 middle
PFAM7
R/W
0003CFH
Memory Patch function - Patch address 7 high
PFAH7
R/W
0003D0H
Memory Patch function - Patch data 0 Low
PFDL0
0003D1H
Memory Patch function - Patch data 0 High
PFDH0
0003D2H
Memory Patch function - Patch data 1 Low
PFDL1
0003D3H
Memory Patch function - Patch data 1 High
PFDH1
0003D4H
Memory Patch function - Patch data 2 Low
PFDL2
0003D5H
Memory Patch function - Patch data 2 High
PFDH2
30
PR
EL
IM
IN
PFAL2
PFD0
R/W
R/W
PFD1
R/W
R/W
PFD2
R/W
R/W
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (9 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PFD3
R/W
Memory Patch function - Patch data 3 Low
PFDL3
0003D7H
Memory Patch function - Patch data 3 High
PFDH3
0003D8H
Memory Patch function - Patch data 4 Low
PFDL4
0003D9H
Memory Patch function - Patch data 4 High
PFDH4
0003DAH
Memory Patch function - Patch data 5 Low
0003DBH
Memory Patch function - Patch data 5 High
0003DCH
Memory Patch function - Patch data 6 Low
0003DDH
Memory Patch function - Patch data 6 High
PFDH6
0003DEH
Memory Patch function - Patch data 7 Low
PFDL7
0003DFH
Memory Patch function - Patch data 7 High
0003E0H0003F0H
Reserved
0003F1H
Memory Control Status Register A
0003F2H
Memory Timing Configuration Register A Low
0003F3H
Memory Timing Configuration Register A High
0003F4H0003F7H
Reserved
0003F8H
Flash Memory Write Control register 0
FMWC0
R/W
0003F9H
Flash Memory Write Control register 1
FMWC1
R/W
0003FAH
Flash Memory Write Control register 2
FMWC2
R/W
0003FBH
Flash Memory Write Control register 3
FMWC3
R/W
0003FCH
Flash Memory Write Control register 4
FMWC4
R/W
0003FDH
Flash Memory Write Control register 5
FMWC5
R/W
0003FEH0003FFH
Reserved
000400H
Standby Mode control register
SMCR
R/W
000401H
Clock select register
CKSR
R/W
000402H
Clock Stabilization select register
CKSSR
R/W
000403H
Clock monitor register
CKMR
R
000404H
Clock Frequency control register Low
CKFCRL
000405H
Clock Frequency control register High
CKFCRH
PFDL5
R/W
PFD4
PFDL6
R/W
R/W
PFD5
PFDH5
AR
IN
IM
EL
PR
FME-MB96390 rev 3
Y
0003D6H
R/W
R/W
PFD6
R/W
R/W
PFD7
PFDH7
R/W
R/W
-
MCSRA
MTCRAL
R/W
MTCRA
MTCRAH
R/W
R/W
-
-
CKFCR
R/W
R/W
31
MB96390 Series
I/O map MB96F39x (10 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PLLCR
R/W
PLL Control register Low
PLLCRL
000407H
PLL Control register High
PLLCRH
R/W
000408H
RC clock timer control register
RCTCR
R/W
000409H
Main clock timer control register
MCTCR
R/W
00040AH
Sub clock timer control register
SCTCR
R/W
00040BH
Reset cause and clock status register with clear
function
RCCSRC
R
00040CH
Reset configuration register
RCR
R/W
00040DH
Reset cause and clock status register
RCCSR
R
00040EH
Watch dog timer configuration register
WDTC
R/W
00040FH
Watch dog timer clear pattern register
WDTCP
W
000410H000414H
Reserved
000415H
Clock output activation register
000416H
IN
AR
Y
000406H
R/W
Clock output configuration register 0
COCR0
R/W
000417H
Clock output configuration register 1
COCR1
R/W
000418H
Clock Modulator control register
CMCR
R/W
000419H
Reserved
00041AH
Clock Modulator Parameter register Low
CMPRL
00041BH
Clock Modulator Parameter register High
CMPRH
00041CH00042BH
Reserved
00042CH
Voltage Regulator Control register
VRCR
R/W
00042DH
Clock Input and LVD Control Register
CILCR
R/W
00042EH00042FH
Reserved
000430H
I/O Port P00 - Data Direction Register
DDR00
R/W
000431H
I/O Port P01 - Data Direction Register
DDR01
R/W
000432H
I/O Port P02 - Data Direction Register
DDR02
R/W
000433H
I/O Port P03 - Data Direction Register
DDR03
R/W
000434H
I/O Port P04 - Data Direction Register
DDR04
R/W
32
PR
EL
IM
COAR
CMPR
R/W
R/W
-
-
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (11 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
000435H
I/O Port P05 - Data Direction Register
DDR05
R/W
000436H
I/O Port P06 - Data Direction Register
DDR06
R/W
000437H
Reserved
000438H
I/O Port P08 - Data Direction Register
000439H
I/O Port P09 - Data Direction Register
00043AH
I/O Port P10 - Data Direction Register
00043BH
I/O Port P11 - Data Direction Register
00043CH
I/O Port P12 - Data Direction Register
00043DH
I/O Port P13 - Data Direction Register
00043EH000443H
Reserved
000444H
I/O Port P00 - Port Input Enable Register
PIER00
R/W
000445H
I/O Port P01 - Port Input Enable Register
PIER01
R/W
000446H
I/O Port P02 - Port Input Enable Register
PIER02
R/W
000447H
I/O Port P03 - Port Input Enable Register
PIER03
R/W
000448H
I/O Port P04 - Port Input Enable Register
PIER04
R/W
000449H
I/O Port P05 - Port Input Enable Register
PIER05
R/W
00044AH
I/O Port P06 - Port Input Enable Register
PIER06
R/W
00044BH
Reserved
00044CH
I/O Port P08 - Port Input Enable Register
PIER08
R/W
00044DH
I/O Port P09 - Port Input Enable Register
PIER09
R/W
00044EH
I/O Port P10 - Port Input Enable Register
PIER10
R/W
00044FH
I/O Port P11 - Port Input Enable Register
PIER11
R/W
000450H
I/O Port P12 - Port Input Enable Register
PIER12
R/W
000451H
I/O Port P13 - Port Input Enable Register
PIER13
R/W
000452H000457H
Reserved
000458H
I/O Port P00 - Port Input Level Register
PILR00
R/W
000459H
I/O Port P01 - Port Input Level Register
PILR01
R/W
00045AH
I/O Port P02 - Port Input Level Register
PILR02
R/W
00045BH
I/O Port P03 - Port Input Level Register
PILR03
R/W
-
Y
DDR08
DDR09
R/W
DDR10
R/W
AR
IN
IM
EL
PR
FME-MB96390 rev 3
R/W
DDR11
R/W
DDR12
R/W
DDR13
R/W
-
-
-
33
MB96390 Series
I/O map MB96F39x (12 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
00045CH
I/O Port P04 - Port Input Level Register
PILR04
R/W
00045DH
I/O Port P05 - Port Input Level Register
PILR05
R/W
00045EH
I/O Port P06 - Port Input Level Register
PILR06
R/W
00045FH
Reserved
000460H
I/O Port P08 - Port Input Level Register
PILR08
R/W
000461H
I/O Port P09 - Port Input Level Register
PILR09
R/W
000462H
I/O Port P10 - Port Input Level Register
000463H
I/O Port P11 - Port Input Level Register
000464H
I/O Port P12 - Port Input Level Register
000465H
I/O Port P13 - Port Input Level Register
000466H00046BH
Reserved
00046CH
I/O Port P00 - Extended Port Input Level Register
EPILR00
R/W
00046DH
I/O Port P01 - Extended Port Input Level Register
EPILR01
R/W
00046EH
I/O Port P02 - Extended Port Input Level Register
EPILR02
R/W
00046FH
I/O Port P03 - Extended Port Input Level Register
EPILR03
R/W
000470H
I/O Port P04 - Extended Port Input Level Register
EPILR04
R/W
000471H
I/O Port P05 - Extended Port Input Level Register
EPILR05
R/W
000472H
I/O Port P06 - Extended Port Input Level Register
EPILR06
R/W
000473H
Reserved
000474H
I/O Port P08 - Extended Port Input Level Register
EPILR08
R/W
000475H
I/O Port P09 - Extended Port Input Level Register
EPILR09
R/W
000476H
I/O Port P10 - Extended Port Input Level Register
EPILR10
R/W
000477H
I/O Port P11 - Extended Port Input Level Register
EPILR11
R/W
000478H
I/O Port P12 - Extended Port Input Level Register
EPILR12
R/W
000479H
I/O Port P13 - Extended Port Input Level Register
EPILR13
R/W
00047AH00047FH
Reserved
000480H
I/O Port P00 - Port Output Drive Register
PODR00
R/W
000481H
I/O Port P01 - Port Output Drive Register
PODR01
R/W
000482H
I/O Port P02 - Port Output Drive Register
PODR02
R/W
34
AR
Y
-
R/W
PILR11
R/W
PILR12
R/W
PILR13
R/W
PR
EL
IM
IN
PILR10
-
-
-
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (13 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
I/O Port P03 - Port Output Drive Register
PODR03
R/W
000484H
I/O Port P04 - Port Output Drive Register
PODR04
R/W
000485H
I/O Port P05 - Port Output Drive Register
PODR05
R/W
000486H
I/O Port P06 - Port Output Drive Register
PODR06
R/W
000487H
Reserved
000488H
I/O Port P08 - Port Output Drive Register
000489H
I/O Port P09 - Port Output Drive Register
00048AH
I/O Port P10 - Port Output Drive Register
00048BH
I/O Port P11 - Port Output Drive Register
00048CH
I/O Port P12 - Port Output Drive Register
00048DH
I/O Port P13 - Port Output Drive Register
00048EH00049BH
Reserved
00049CH
I/O Port P08 - Port High Drive Register
00049DH
Y
000483H
IN
AR
PODR08
R/W
PODR09
R/W
PODR10
R/W
PODR11
R/W
PODR12
R/W
PODR13
R/W
R/W
I/O Port P09 - Port High Drive Register
PHDR09
R/W
00049EH
I/O Port P10 - Port High Drive Register
PHDR10
R/W
00049FH0004A7H
Reserved
0004A8H
I/O Port P00 - Pull-Up resistor Control Register
PUCR00
R/W
0004A9H
I/O Port P01 - Pull-Up resistor Control Register
PUCR01
R/W
0004AAH
I/O Port P02 - Pull-Up resistor Control Register
PUCR02
R/W
0004ABH
I/O Port P03 - Pull-Up resistor Control Register
PUCR03
R/W
0004ACH
I/O Port P04 - Pull-Up resistor Control Register
PUCR04
R/W
0004ADH
I/O Port P05 - Pull-Up resistor Control Register
PUCR05
R/W
0004AEH
I/O Port P06 - Pull-Up resistor Control Register
PUCR06
R/W
0004AFH
Reserved
0004B0H
I/O Port P08 - Pull-Up resistor Control Register
PUCR08
R/W
0004B1H
I/O Port P09 - Pull-Up resistor Control Register
PUCR09
R/W
0004B2H
I/O Port P10 - Pull-Up resistor Control Register
PUCR10
R/W
0004B3H
I/O Port P11 - Pull-Up resistor Control Register
PUCR11
R/W
0004B4H
I/O Port P12 - Pull-Up resistor Control Register
PUCR12
R/W
PR
EL
IM
PHDR08
FME-MB96390 rev 3
-
-
35
MB96390 Series
I/O map MB96F39x (14 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
0004B5H
I/O Port P13 - Pull-Up resistor Control Register
0004B6H0004BBH
Reserved
0004BCH
I/O Port P00 - External Pin State Register
EPSR00
0004BDH
I/O Port P01 - External Pin State Register
EPSR01
R
0004BEH
I/O Port P02 - External Pin State Register
EPSR02
R
0004BFH
I/O Port P03 - External Pin State Register
0004C0H
I/O Port P04 - External Pin State Register
0004C1H
I/O Port P05 - External Pin State Register
0004C2H
I/O Port P06 - External Pin State Register
0004C3H
Reserved
0004C4H
I/O Port P08 - External Pin State Register
EPSR08
R
0004C5H
I/O Port P09 - External Pin State Register
EPSR09
R
0004C6H
I/O Port P10 - External Pin State Register
EPSR10
R
0004C7H
I/O Port P11 - External Pin State Register
EPSR11
R
0004C8H
I/O Port P12 - External Pin State Register
EPSR12
R
0004C9H
I/O Port P13 - External Pin State Register
EPSR13
R
0004CAH0004CFH
Reserved
0004D0H
ADC analog input enable register 0
ADER0
R/W
0004D1H
ADC analog input enable register 1
ADER1
R/W
0004D2H
ADC analog input enable register 2
ADER2
R/W
0004D3H
ADC analog input enable register 3
ADER3
R/W
0004D4H
ADC analog input enable register 4
ADER4
R/W
0004D5H
Reserved
0004D6H
Peripheral Resource Relocation Register 0
PRRR0
R/W
0004D7H
Peripheral Resource Relocation Register 1
PRRR1
R/W
0004D8H
Peripheral Resource Relocation Register 2
PRRR2
R/W
0004D9H
Peripheral Resource Relocation Register 3
PRRR3
R/W
0004DAH
Peripheral Resource Relocation Register 4
PRRR4
R/W
0004DBH
Peripheral Resource Relocation Register 5
PRRR5
R/W
36
PUCR13
Access
R/W
AR
Y
-
EPSR03
R
EPSR04
R
EPSR05
R
EPSR06
R
IN
IM
EL
PR
R
-
-
-
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (15 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
Peripheral Resource Relocation Register 6
PRRR6
R/W
0004DDH
Peripheral Resource Relocation Register 7
PRRR7
R/W
0004DEH
Peripheral Resource Relocation Register 8
PRRR8
R/W
0004DFH
Peripheral Resource Relocation Register 9
PRRR9
R/W
0004E0H
RTC - Sub Second Register L
0004E1H
RTC - Sub Second Register M
0004E2H
RTC - Sub-Second Register H
0004E3H
RTC - Second Register
0004E4H
RTC - Minutes
0004E5H
RTC - Hour
0004E6H
RTC - Timer Control Extended Register
0004E7H
RTC - Clock select register
0004E8H
RTC - Timer Control Register Low
0004E9H
RTC - Timer Control Register High
0004EAH
CAL - Calibration unit Control register
0004EBH
Reserved
0004ECH
CAL - Duration Timer Data Register Low
0004EDH
CAL - Duration Timer Data Register High
CUTDH
0004EEH
CAL - Calibration Timer Register 2 Low
CUTR2L
0004EFH
CAL - Calibration Timer Register 2 High
CUTR2H
0004F0H
CAL - Calibration Timer Register 1 Low
CUTR1L
0004F1H
CAL - Calibration Timer Register 1 High
0004F2H0004F9H
Reserved
0004FAH
RLT - Timer input select (for Cascading)
0004FBH00055FH
Reserved
000560H
ALARM0 - Control Status Register
000561H
ALARM0 - Extended Control Status Register
000562H0005DFH
Reserved
Y
0004DCH
WTBRL0
IN
IM
EL
R/W
R/W
AR
WTBRH0
PR
FME-MB96390 rev 3
WTBR0
WTBR1
R/W
WTSR
R/W
WTMR
R/W
WTHR
R/W
WTCER
R/W
WTCKSR
R/W
WTCRL
WTCR
R/W
WTCRH
R/W
CUCR
R/W
-
CUTDL
CUTR1H
CUTD
R/W
R/W
CUTR2
R
R
CUTR1
R
R
-
TMISR
R/W
-
ACSR0
R/W
AECSR0
R/W
-
37
MB96390 Series
I/O map MB96F39x (16 of 22)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
0005E0H
SMC0 - PWM control register
0005E1H
SMC0 - Extended control register (Output enable)
0005E2H
SMC0 - PWM compare register PWM 1
0005E3H
SMC0 - PWM compare register PWM 1
0005E4H
SMC0 - PWM compare register PWM 2
0005E5H
SMC0 - PWM compare register PWM 2
0005E6H
SMC0 - PWM Select register
0005E7H
SMC0 - PWM Select register
0005E8H0005E9H
Reserved
0005EAH
SMC1 - PWM control register
0005EBH
SMC1 - Extended control register (Output enable)
0005ECH
SMC1 - PWM compare register PWM 1
0005EDH
SMC1 - PWM compare register PWM 1
0005EEH
SMC1 - PWM compare register PWM 2
0005EFH
SMC1 - PWM compare register PWM 2
0005F0H
SMC1 - PWM Select register
0005F1H
SMC1 - PWM Select register
0005F2H0005F3H
Reserved
0005F4H
SMC2 - PWM control register
0005F5H
SMC2 - Extended control register (Output enable)
0005F6H
SMC2 - PWM compare register PWM 1
0005F7H
SMC2 - PWM compare register PWM 1
0005F8H
SMC2 - PWM compare register PWM 2
0005F9H
SMC2 - PWM compare register PWM 2
0005FAH
SMC2 - PWM Select register
PWS12
R/W
0005FBH
SMC2 - PWM Select register
PWS22
R/W
0005FCH000607H
Reserved
000608H
SMC4 - PWM control register
38
PWC0
R/W
PWEC0
R/W
PWC10
R/W
Y
R/W
PWC20
AR
PWS10
R/W
PWS20
R/W
IN
IM
R/W
R/W
-
PWC1
EL
PR
Access
R/W
PWEC1
R/W
PWC11
R/W
R/W
PWC21
R/W
R/W
PWS11
R/W
PWS21
R/W
-
PWC2
R/W
PWEC2
R/W
PWC12
R/W
R/W
PWC22
R/W
R/W
PWC4
R/W
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (17 of 22)
Address
Register
Abbreviation
8-bit access
000609H
SMC4 - Extended control register (Output enable)
PWEC4
00060AH
SMC4 - PWM compare register PWM 1
00060BH
SMC4 - PWM compare register PWM 1
00060CH
SMC4 - PWM compare register PWM 2
00060DH
SMC4 - PWM compare register PWM 2
00060EH
SMC4 - PWM Select register
00060FH
SMC4 - PWM Select register
000610H00061BH
Reserved
00061CH
LCD - Output Enable Register 0 (Seg 7-0)
00061DH
LCD - Output Enable Register 1 (Seg 15-8)
00061EH
Abbreviation
16-bit access
Access
R/W
PWC14
R/W
R/W
Y
PWC24
AR
PWS14
PWS24
R/W
R/W
R/W
R/W
R/W
LCDER1
R/W
LCD - Output Enable Register 2 (Seg 23-16)
LCDER2
R/W
00061FH
LCD - Output Enable Register 3 (Seg 31-24)
LCDER3
R/W
000620H
LCD - Output Enable Register 4 (Seg 39-32)
LCDER4
R/W
000621H
LCD - Output Enable Register 5 (Seg 47-40)
LCDER5
R/W
000622H
LCD - Output Enable Register 6 (Seg 55-48)
LCDER6
R/W
000623H
LCD - Output Enable Register 7 (Seg 63-56)
LCDER7
R/W
000624H
LCD - Output Enable Register 8 (Seg 71-64)
LCDER8
R/W
000625H
Reserved
000626H
LCD - Output Enable Register V (Vx)
000627H
LCD - Extended Control Register
000628H
LCD - Common pin switching register
000629H
LCD - Control Register
00062AH
EL
IM
IN
LCDER0
R/W
LECR
R/W
LCDCMR
R/W
LCR
R/W
LCD - Data register for Segment 1-0
VRAM0
R/W
00062BH
LCD - Data register for Segment 3-2
VRAM1
R/W
00062CH
LCD - Data register for Segment 5-4
VRAM2
R/W
00062DH
LCD - Data register for Segment 7-6
VRAM3
R/W
00062EH
LCD - Data register for Segment 9-8
VRAM4
R/W
00062FH
LCD - Data register for Segment 11-10
VRAM5
R/W
000630H
LCD - Data register for Segment 13-12
VRAM6
R/W
PR
LCDVER
FME-MB96390 rev 3
39
MB96390 Series
I/O map MB96F39x (18 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
LCD - Data register for Segment 15-14
VRAM7
R/W
000632H
LCD - Data register for Segment 17-16
VRAM8
R/W
000633H
LCD - Data register for Segment 19-18
VRAM9
R/W
000634H
LCD - Data register for Segment 21-20
VRAM10
R/W
000635H
LCD - Data register for Segment 23-22
VRAM11
R/W
000636H
LCD - Data register for Segment 25-24
VRAM12
R/W
000637H
LCD - Data register for Segment 27-26
000638H
LCD - Data register for Segment 29-28
000639H
LCD - Data register for Segment 31-30
00063AH
LCD - Data register for Segment 33-32
00063BH
LCD - Data register for Segment 35-34
00063CH
LCD - Data register for Segment 37-36
00063DH
LCD - Data register for Segment 39-38
00063EH
LCD - Data register for Segment 41-40
00063FH
AR
Y
000631H
R/W
VRAM14
R/W
VRAM15
R/W
VRAM16
R/W
VRAM17
R/W
VRAM18
R/W
VRAM19
R/W
VRAM20
R/W
LCD - Data register for Segment 43-42
VRAM21
R/W
000640H
LCD - Data register for Segment 45-44
VRAM22
R/W
000641H
LCD - Data register for Segment 47-46
VRAM23
R/W
000642H
LCD - Data register for Segment 49-48
VRAM24
R/W
000643H
LCD - Data register for Segment 51-50
VRAM25
R/W
000644H
LCD - Data register for Segment 53-52
VRAM26
R/W
000645H
LCD - Data register for Segment 55-54
VRAM27
R/W
000646H
LCD - Data register for Segment 57-56
VRAM28
R/W
000647H
LCD - Data register for Segment 59-58
VRAM29
R/W
000648H
LCD - Data register for Segment 61-60
VRAM30
R/W
000649H
LCD - Data register for Segment 63-62
VRAM31
R/W
00064AH
LCD - Data register for Segment 65-64
VRAM32
R/W
00064BH00065FH
Reserved
000660H
Peripheral Resource Relocation Register 10
PRRR10
R/W
000661H
Peripheral Resource Relocation Register 11
PRRR11
R/W
40
PR
EL
IM
IN
VRAM13
-
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (19 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
000662H
Peripheral Resource Relocation Register 12
PRRR12
R/W
000663H
Peripheral Resource Relocation Register 13
PRRR13
W
000664H0006FFH
Reserved
000700H
CAN0 - Control register Low
000701H
CAN0 - Control register High (reserved)
000702H
CAN0 - Status register Low
000703H
CAN0 - Status register High (reserved)
000704H
CAN0 - Error Counter Low (Transmit)
000705H
CAN0 - Error Counter High (Receive)
000706H
CAN0 - Bit Timing Register Low
000707H
CAN0 - Bit Timing Register High
000708H
CAN0 - Interrupt Register Low
000709H
CAN0 - Interrupt Register High
00070AH
CAN0 - Test Register Low
TESTRL0
00070BH
CAN0 - Test Register High (reserved)
TESTRH0
00070CH
CAN0 - BRP Extension register Low
BRPERL0
00070DH
CAN0 - BRP Extension register High (reserved)
BRPERH0
00070EH00070FH
Reserved
000710H
CAN0 - IF1 Command request register Low
IF1CREQL0
000711H
CAN0 - IF1 Command request register High
IF1CREQH0
000712H
CAN0 - IF1 Command Mask register Low
IF1CMSKL0
000713H
CAN0 - IF1 Command Mask register High (reserved)
IF1CMSKH0
000714H
CAN0 - IF1 Mask 1 Register Low
IF1MSK1L0
000715H
CAN0 - IF1 Mask 1 Register High
IF1MSK1H0
000716H
CAN0 - IF1 Mask 2 Register Low
IF1MSK2L0
000717H
CAN0 - IF1 Mask 2 Register High
IF1MSK2H0
000718H
CAN0 - IF1 Arbitration 1 Register Low
IF1ARB1L0
000719H
CAN0 - IF1 Arbitration 1 Register High
IF1ARB1H0
Y
CTRLRL0
AR
CTRLRH0
STATRL0
ERRCNTL0
IN
IM
EL
STATR0
R/W
R
ERRCNT0
ERRCNTH0
R
R
BTR0
BTRH0
INTRL0
R/W
R
STATRH0
BTRL0
PR
FME-MB96390 rev 3
CTRLR0
R/W
R/W
INTR0
INTRH0
R
R
TESTR0
R/W
R
BRPER0
R/W
R
-
IF1CREQ0
R/W
R/W
IF1CMSK0
R/W
R
IF1MSK10
R/W
R/W
IF1MSK20
R/W
R/W
IF1ARB10
R/W
R/W
41
MB96390 Series
I/O map MB96F39x (20 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF1ARB20
R/W
CAN0 - IF1 Arbitration 2 Register Low
IF1ARB2L0
00071BH
CAN0 - IF1 Arbitration 2 Register High
IF1ARB2H0
00071CH
CAN0 - IF1 Message Control Register Low
IF1MCTRL0
00071DH
CAN0 - IF1 Message Control Register High
IF1MCTRH0
00071EH
CAN0 - IF1 Data A1 Low
IF1DTA1L0
00071FH
CAN0 - IF1 Data A1 High
IF1DTA1H0
000720H
CAN0 - IF1 Data A2 Low
000721H
CAN0 - IF1 Data A2 High
000722H
CAN0 - IF1 Data B1 Low
000723H
CAN0 - IF1 Data B1 High
000724H
CAN0 - IF1 Data B2 Low
000725H
CAN0 - IF1 Data B2 High
000726H00073FH
Reserved
000740H
CAN0 - IF2 Command request register Low
IF2CREQL0
000741H
CAN0 - IF2 Command request register High
IF2CREQH0
000742H
CAN0 - IF2 Command Mask register Low
IF2CMSKL0
000743H
CAN0 - IF2 Command Mask register High (reserved)
IF2CMSKH0
000744H
CAN0 - IF2 Mask 1 Register Low
IF2MSK1L0
000745H
CAN0 - IF2 Mask 1 Register High
IF2MSK1H0
000746H
CAN0 - IF2 Mask 2 Register Low
IF2MSK2L0
000747H
CAN0 - IF2 Mask 2 Register High
IF2MSK2H0
000748H
CAN0 - IF2 Arbitration 1 Register Low
IF2ARB1L0
000749H
CAN0 - IF2 Arbitration 1 Register High
IF2ARB1H0
00074AH
CAN0 - IF2 Arbitration 2 Register Low
IF2ARB2L0
00074BH
CAN0 - IF2 Arbitration 2 Register High
IF2ARB2H0
00074CH
CAN0 - IF2 Message Control Register Low
IF2MCTRL0
00074DH
CAN0 - IF2 Message Control Register High
IF2MCTRH0
00074EH
CAN0 - IF2 Data A1 Low
IF2DTA1L0
00074FH
CAN0 - IF2 Data A1 High
IF2DTA1H0
42
R/W
IF1MCTR0
AR
IF1DTA2L0
IF1DTA10
IF1DTA20
IF1DTB10
IN
IM
EL
R/W
R/W
IF1DTB20
IF1DTB2H0
PR
R/W
R/W
IF1DTB1H0
IF1DTB2L0
R/W
R/W
IF1DTA2H0
IF1DTB1L0
R/W
R/W
Y
00071AH
R/W
R/W
-
IF2CREQ0
R/W
R/W
IF2CMSK0
R/W
R
IF2MSK10
R/W
R/W
IF2MSK20
R/W
R/W
IF2ARB10
R/W
R/W
IF2ARB20
R/W
R/W
IF2MCTR0
R/W
R/W
IF2DTA10
R/W
R/W
FME-MB96390 rev 3
MB96390 Series
I/O map MB96F39x (21 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF2DTA20
R/W
CAN0 - IF2 Data A2 Low
IF2DTA2L0
000751H
CAN0 - IF2 Data A2 High
IF2DTA2H0
000752H
CAN0 - IF2 Data B1 Low
IF2DTB1L0
000753H
CAN0 - IF2 Data B1 High
IF2DTB1H0
000754H
CAN0 - IF2 Data B2 Low
000755H
CAN0 - IF2 Data B2 High
000756H00077FH
Reserved
000780H
CAN0 - Transmission Request 1 Register Low
TREQR1L0
000781H
CAN0 - Transmission Request 1 Register High
TREQR1H0
000782H
CAN0 - Transmission Request 2 Register Low
TREQR2L0
000783H
CAN0 - Transmission Request 2 Register High
000784H00078FH
Reserved
000790H
CAN0 - New Data 1 Register Low
NEWDT1L0
000791H
CAN0 - New Data 1 Register High
NEWDT1H0
000792H
CAN0 - New Data 2 Register Low
NEWDT2L0
000793H
CAN0 - New Data 2 Register High
NEWDT2H0
000794H00079FH
Reserved
0007A0H
CAN0 - Interrupt Pending 1 Register Low
INTPND1L0
0007A1H
CAN0 - Interrupt Pending 1 Register High
INTPND1H0
0007A2H
CAN0 - Interrupt Pending 2 Register Low
INTPND2L0
0007A3H
CAN0 - Interrupt Pending 2 Register High
INTPND2H0
0007A4H0007AFH
Reserved
0007B0H
CAN0 - Message Valid 1 Register Low
MSGVAL1L0
0007B1H
CAN0 - Message Valid 1 Register High
MSGVAL1H0
0007B2H
CAN0 - Message Valid 2 Register Low
MSGVAL2L0
0007B3H
CAN0 - Message Valid 2 Register High
MSGVAL2H0
0007B4H0007CDH
Reserved
Y
000750H
IF2DTB2L0
IF2DTB10
AR
IN
IM
EL
R/W
R/W
IF2DTB20
IF2DTB2H0
PR
FME-MB96390 rev 3
R/W
R/W
R/W
-
TREQR10
R
R
TREQR20
TREQR2H0
R
R
-
NEWDT10
R
R
NEWDT20
R
R
-
INTPND10
R
R
INTPND20
R
R
-
MSGVAL10
R
R
MSGVAL20
R
R
-
43
MB96390 Series
I/O map MB96F39x (22 of 22)
Address
Abbreviation
8-bit access
Register
Abbreviation
16-bit access
Access
0007CEH
CAN0 - Output enable register
0007CFH
Reserved
0007D0H
SG0 - Sound Generator Control Register Low
SGCRL0
0007D1H
SG0 - Sound Generator Control Register High
SGCRH0
0007D2H
SG0 - Sound Generator Frequency Register
SGFR0
R/W
0007D3H
SG0 - Sound Generator Amplitude Register
SGAR0
R/W
0007D4H
SG0 - Sound Generator Decrement Register
0007D5H
SG0 - Sound Generator Tone Register
0007D6H000BFFH
Reserved
COER0
R/W
-
AR
Y
SGCR0
R/W
R/W
SGDR0
R/W
SGTR0
R/W
-
PR
EL
IM
IN
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved
address results in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
44
FME-MB96390 rev 3
MB96390 Series
■ INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)39x (1 of 3)
Offset in
Index in
Vector
vector taVector name
ICR to pronumber
ble
gram
Description
3FCH
CALLV0
-
1
3F8H
CALLV1
-
2
3F4H
CALLV2
-
3
3F0H
CALLV3
-
4
3ECH
CALLV4
-
5
3E8H
CALLV5
-
6
3E4H
CALLV6
-
7
3E0H
CALLV7
-
8
3DCH
RESET
-
9
3D8H
INT9
-
10
3D4H
EXCEPTION
-
11
3D0H
NMI
12
3CCH
DLY
13
3C8H
RC_TIMER
14
3C4H
MC_TIMER
14
Main Clock Timer
15
3C0H
SC_TIMER
15
Sub Clock Timer
16
3BCH
17
3B8H
EXTINT0
18
3B4H
19
3B0H
20
3ACH
21
3A8H
22
3A4H
23
IN
AR
Y
0
-
Non-Maskable Interrupt
Delayed Interrupt
13
RC Timer
IM
12
External Interrupt 0
EXTINT1
18
External Interrupt 1
EXTINT2
19
External Interrupt 2
EXTINT3
20
External Interrupt 3
EXTINT4
21
External Interrupt 4
EXTINT5
22
External Interrupt 5
3A0H
EXTINT6
23
External Interrupt 6
24
39CH
EXTINT7
24
External Interrupt 7
25
398H
CAN0
25
CAN Controller 0
26
394H
27
390H
PPG0
27
Programmable Pulse Generator 0
28
38CH
PPG1
28
Programmable Pulse Generator 1
29
388H
PPG2
29
Programmable Pulse Generator 2
30
384H
PPG3
30
Programmable Pulse Generator 3
31
380H
Reserved
32
37CH
Reserved
PR
EL
17
Reserved
FME-MB96390 rev 3
Reserved
45
MB96390 Series
Interrupt vector table MB96(F)39x (2 of 3)
Offset in
Index in
Vector
vector taVector name
ICR to pronumber
ble
gram
46
378H
Reserved
34
374H
Reserved
35
370H
RLT0
35
Reload Timer 0
36
36CH
RLT1
36
Reload Timer 1
37
368H
RLT2
37
Reload Timer 2
38
364H
RLT3
38
Reload Timer 3
39
360H
PPGRLT
39
Reload Timer 6 - dedicated for PPG
40
35CH
ICU0
40
Input Capture Unit 0
41
358H
ICU1
41
Input Capture Unit 1
42
354H
Reserved
43
350H
Reserved
44
34CH
Reserved
45
348H
46
344H
ICU6
46
47
340H
ICU7
47
48
33CH
OCU0
48
49
338H
OCU1
50
334H
OCU2
51
330H
OCU3
52
32CH
FRT0
53
328H
FRT1
53
Free Running Timer 1
54
324H
RTC0
54
Real Timer Clock
55
320H
CAL0
55
Clock Calibration Unit
56
31CH
SG0
56
Sound Generator 0
57
318H
58
314H
59
310H
60
30CH
61
308H
62
304H
LINR0
62
LIN USART 0 RX
63
300H
LINT0
63
LIN USART 0 TX
64
2FCH
LINR1
64
LIN USART 1 RX
65
2F8H
LINT1
65
LIN USART 1 TX
66
2F4H
LINR2
66
LIN USART 2 RX
67
2F0H
LINT2
67
LIN USART 2 TX
IN
AR
Y
33
PR
Description
Reserved
Input Capture Unit 6
Input Capture Unit 7
IM
Output Compare Unit 0
Output Compare Unit 1
50
Output Compare Unit 2
51
Output Compare Unit 3
52
Free Running Timer 0
EL
49
Reserved
IIC0
58
I2C interface
ADC0
59
A/D Converter
ALARM0
60
Alarm Comparator 0
Reserved
FME-MB96390 rev 3
MB96390 Series
Interrupt vector table MB96(F)39x (3 of 3)
Offset in
Index in
Vector
vector taVector name
ICR to pronumber
ble
gram
Description
68
2ECH
Reserved
69
2E8H
Reserved
70
2E4H
Reserved
71
2E0H
Reserved
72
2DCH
73
2D8H
72
Flash memory A (only Flash devices)
PR
EL
IM
IN
AR
Reserved
Y
FLASH_A
FME-MB96390 rev 3
47
MB96390 Series
Latch-up prevention
Unused pins handling
External clock usage
Unused sub clock signal
Notes on PLL clock mode operation
Power supply pins (VCC/VSS)
Crystal oscillator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on energization
Stabilization of power supply voltage
SMC power supply pins
Serial communication
AR
•
•
•
•
•
•
•
•
•
•
•
•
•
Y
■ HANDLING DEVICES
Special care is required for the following when handling the device:
1. Latch-up prevention
IN
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
IM
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
EL
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
PR
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC
Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
48
FME-MB96390 rev 3
MB96390 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
X0
Y
X1
4. Unused sub clock signal
AR
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
6. Power supply pins (VCC/VSS)
IN
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
IM
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
EL
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
PR
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
FME-MB96390 rev 3
49
MB96390 Series
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. SMC power supply pins
All DVSS pins must be set to the same level as the VSS pins.
Y
The DVCC power supply level can be set independently of the VCC power supply level. However note that the
SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to
always power VCC before DVCC.
AR
13. Serial communication
PR
EL
IM
IN
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
50
FME-MB96390 rev 3
MB96390 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Symbol
AD Converter voltage references
SMC Power supply
LCD power supply voltage
Min
Max
Unit
Remarks
VCC
VSS - 0.3 VSS + 6.0
V
AVCC
VSS - 0.3 VSS + 6.0
V
AVRH,
AVRL
VSS - 0.3 VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
DVCC
VSS - 0.3 VSS + 6.0
V
See *7
VCC = AVCC *1
Y
Power supply voltage
Rating
AR
Parameter
V0 to V3 VSS - 0.3 VSS + 6.0
V
V0 to V3 must not exceed VCC
Input voltage
VI
VSS - 0.3 VSS + 6.0
V
VI ≤ (D)VCC + 0.3V
Output voltage
VO
VSS - 0.3 VSS + 6.0
V
VO ≤ (D)VCC + 0.3V *2
Total Maximum Clamp Current
“L” level maximum output current
“L” level average overall output current
PR
”H” level maximum output current
”H” level average output current
”H” level maximum overall output current
”H” level average overall output current
FME-MB96390 rev 3
40
mA
Applicable to general purpose
I/O pins *3
-
15
mA Normal outputs with driving
strength set to 5mA
-
40
mA High current outputs with driving strength set to 30mA
Σ|ICLAMP|
-
IOL1
+4.0
IM
IOLAV1
-
5
mA Normal outputs with driving
strength set to 5mA
IOLAVSMC
-
30
mA High current outputs with driving strength set to 30mA
ΣIOL1
-
100
mA Normal outputs
ΣIOLSMC
-
330
mA High current outputs
ΣIOLAV1
-
50
mA Normal outputs
ΣIOLAVSMC
-
250
mA High current outputs
IOH1
-
-15
mA
IOHSMC
-
-40
mA High current outputs with driving strength set to 30mA
IOHAV1
-
-5
mA Normal outputs with driving
strength set to 5mA
IOHAVSMC
-
-30
mA High current outputs with driving strength set to 30mA
ΣIOH1
-
-100
mA Normal outputs
ΣIOHSMC
-
-330
mA High current outputs
ΣIOHAV1
-
-50
mA Normal outputs
ΣIOHASMC
-
-250
mA High current outputs
EL
“L” level maximum overall output current
Applicable to general purpose
I/O pins *3
-4.0
IOLSMC
“L” level average output current
mA
ICLAMP
IN
Maximum Clamp Current
*2
Normal outputs with driving
strength set to 5mA
51
MB96390 Series
Symbol
Permitted Power dissipation
(MB96F395) *4
Rating
TA
-
255*5
mW TA=105oC
-
510*5
mW TA=85oC
-
830*5
mW TA=60oC
-
320*5
mW
-
575*5
mW
0
+70
-40
-40
TSTG
Remarks
Max
-55
TA=125oC, no Flash program/
erase *6
TA=105oC, no Flash program/
erase *6
Y
PD
Operating ambient temperature
Storage temperature
Unit
Min
MB96V300B
AR
Parameter
+105
o
C
+125
+150
*6
o
C
IN
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard
ports depend on VCC.
PR
EL
IM
*3: • Applicable to all general purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality.
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
• No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins).
52
FME-MB96390 rev 3
MB96390 Series
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
AR
R
Y
N-ch
IM
IN
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
EL
*7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always
power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value.
PR
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
FME-MB96390 rev 3
53
MB96390 Series
2. Recommended Operating Conditions
Symbol
Power supply voltage
Smoothing capacitor at C
pin
Value
Unit
Min
Typ
Max
VCC, DVCC
3.0
-
5.5
V
CS
3.5
4.7
15
µF
Remarks
Use a X7R ceramic capacitor or
a capacitor that has similar frequency characteristics
Y
Parameter
PR
EL
IM
IN
AR
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
54
FME-MB96390 rev 3
MB96390 Series
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Pin
Condition
Input H voltage
CMOS Hysteresis
0.8/0.2 input selected
Max
0.8
VCC
-
(D)VCC
+ 0.3
V
-
(D)VCC
+ 0.3
V
(D)VCC ≥ 4.5V
-
(D)VCC
+ 0.3
V
(D)VCC < 4.5V
0.7
VCC
0.74
VCC
0.8
VCC
-
(D)VCC
+ 0.3
V
TTL input selected
2.0
-
(D)VCC
+ 0.3
V
X0
External clock in
“Fast Clock Input
mode”
0.8
VCC
-
VCC +
0.3
V
VIHX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
2.5
-
VCC +
0.3
V
VIHR
RSTX
-
0.8
VCC
-
VCC +
0.3
V
VIHM
MD2-MD0
-
VCC 0.3
-
VCC +
0.3
V
CMOS Hysteresis
0.8/0.2 input selected
VSS 0.3
-
0.2
(D)VCC
V
CMOS Hysteresis
0.7/0.3 input sePort inputs lected
VSS 0.3
-
0.3
(D)VCC
V
VSS 0.3
-
0.5
(D)VCC
V
VSS 0.3
-
0.46
(D)VCC
TTL input selected
VSS 0.3
-
0.8
V
IM
EL
Pnn_m
PR
VIL
AUTOMOTIVE
Hysteresis input
selected
Remarks
Typ
VIHX0F
Input L voltage
FME-MB96390 rev 3
Unit
Min
AR
VIH
CMOS Hysteresis
Port inputs 0.7/0.3 input selected
Pnn_m
AUTOMOTIVE
Hysteresis input
selected
Value
Y
Symbol
IN
Parameter
CMOS Hysteresis input
(D)VCC ≥ 4.5V
(D)VCC < 4.5V
VILX0F
X0
External clock in
“Fast Clock Input
mode”
VSS 0.3
-
0.2 VCC
V
VILX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
VSS 0.3
-
0.4
V
VILR
RSTX
-
VSS 0.3
-
0.2 VCC
V
VILM
MD2-MD0
-
VSS 0.3
-
VSS +
0.3
V
CMOS Hysteresis input
55
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Pin
Min
Typ
Normal
and High
Current
outputs
IOH = -2mA
3.0V ≤ (D)VCC <
4.5V
(D)VCC
- 0.5
-
V
Driving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
(D)VCC
- 0.5
-
-
V
Driving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
DVCC 0.5
3.0V ≤ DVCC < 4.5V
-
-
V
Driving strength set
to 30mA
(PHDR:HD=1)
VCC 0.5
-
-
V
I/O circuit type “N”
V
Driving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
IOH = -5mA
3.0V ≤ (D)VCC <
4.5V
IOH = -3mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
IN
VOH30
-
Remarks
AR
4.5V ≤ (D)VCC ≤
5.5V
Normal
and High
Current
outputs
High current outputs
Unit
Y
IOH = -1.6mA
VOH5
Max
4.5V ≤ (D)VCC ≤
5.5V
Output H voltage
VOH2
Value
Condition
IOH = -20mA
4.5V ≤ VCC ≤ 5.5V
3mA outputs
IOH = -3mA
3.0V ≤ VCC < 4.5V
IM
VOH3
IOH = -2mA
4.5V ≤ (D)VCC ≤
5.5V
Output L voltage
IOL = +2mA
3.0V ≤ (D)VCC <
4.5V
EL
VOL2
Normal
and High
Current
outputs
-
-
0.4
IOL = +1.6mA
IOL = +5mA
PR
VOL5
Normal
and High
Current
outputs
4.5V ≤ (D)VCC ≤
5.5V
3.0V ≤ (D)VCC <
4.5V
-
-
0.4
V
Driving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
-
-
0.5
V
Driving strength set
to 30mA
(PHDR:HD=1)
-
-
0.4
V
I/O circuit type “N”
-1
-
+1
IOL = +3mA
4.5V ≤ DVCC ≤ 5.5V
VOL30
High current outputs
VOL3
3mA outputs
IIL
Pnn_m
IOL = +30mA
3.0V ≤ DVCC < 4.5V
IOL = +20mA
3.0V ≤ VCC ≤ 5.5V
IOL = +3mA
VSS < VI < VCC
Input leak current
56
AVSS, AVRL < VI <
AVCC, AVRH
µA Single port pin
FME-MB96390 rev 3
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Symbol
Pin
Condition
Total LCD leak
current
Σ|IILCD|
all SEG/
COM pins
Internal LCD divide resistance
RLCD
Between
V3 and VSS
Pull-up resistance
RUP
Pnn_m,
RSTX
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.0V
-
0.5
10
Maximum leakage
µA current of all LCD
pins
VCC = 5.0V
25
40
65
kΩ
VCC = 3.3V ± 10%
40
100
160
kΩ
VCC = 5.0V ± 10%
25
50
100
kΩ
Y
Parameter
PR
EL
IM
IN
AR
Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
FME-MB96390 rev 3
57
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Symbol
Value
Condition (at TA)
Typ
Max
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
+25˚C
15
20
1 Flash/ROM wait state
+125˚C
16
22.5
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
+25˚C
23
2 Flash/ROM wait states
+125˚C
24.5
31.5
+25˚C
27
39
+125˚C
28.5
41.5
+25˚C
38
51
+125˚C
39.5
53.5
+25˚C
4.2
5.2
+125˚C
4.7
7
+25˚C
2.7
3.7
+125˚C
3.2
5.4
0 Flash/ROM wait states
29
AR
IN
(CLKRC and CLKSC
stopped)
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
Remarks
mA
(CLKRC and CLKSC
stopped)
ICCPLL
Unit
Y
Parameter
mA
mA
IM
(CLKRC and CLKSC
stopped)
Power supply current in Run
modes*
EL
PLL Run mode with
CLKS1/2 = 80MHz,
CLKB = CLKP1 = 40MHz,
CLKP2 = 20MHz
1 Flash wait state
mA
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
PR
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
ICCMAIN
1 Flash/ROM wait state
mA
(CLKPLL, CLKSC and
CLKRC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
ICCRCH
1 Flash/ROM wait state
mA
(CLKMC, CLKPLL and
CLKSC stopped)
58
FME-MB96390 rev 3
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Value
Condition (at TA)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
Typ
Max
+25˚C
0.4
0.6
+125˚C
0.9
2.1
mA
Power supply current in Run
modes*
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
AR
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
ICCRCL
+25˚C
0.15
0.25
(CLKMC, CLKPLL and +125˚C
CLKSC stopped. Voltage
regulator in low power
mode, no Flash programming/erasing allowed)
0.55
1.75
+25˚C
0.1
0.2
(CLKMC, CLKPLL and +125˚C
CLKRC stopped, no Flash
programming/erasing allowed)
0.5
1.7
IN
1 Flash/ROM wait state
mA
1 Flash/ROM wait state
mA
PR
EL
ICCSUB
IM
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
Remarks
Y
1 Flash/ROM wait state
Unit
FME-MB96390 rev 3
59
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
PLL Sleep mode with
CLKS1/2 = CLKP1 =
16MHz,
CLKP2 = 8MHz
(CLKRC and CLKSC
stopped)
Max
+25˚C
4
6
+125˚C
4.6
8
+25˚C
7
7.6
11.5
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
+25˚C
7
9
(CLKRC and CLKSC
stopped)
+125˚C
7.6
11
PLL Sleep mode with
CLKS1/2 = 80MHz,
CLKP1 = 40MHz,
CLKP2 = 20MHz
+25˚C
11
13
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
11.6
15
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
+25˚C
1.3
1.8
(CLKPLL, CLKSC and
CLKRC stopped)
+125˚C
1.8
3.3
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
+25˚C
0.8
1.4
+125˚C
1.3
2.9
PR
ICCSRCH
EL
ICCSMAIN
(CLKMC, CLKPLL and
CLKSC stopped)
60
Remarks
9.5
+125˚C
(CLKRC and CLKSC
stopped)
Unit
mA
IM
Power supply current in Sleep
modes*
Typ
IN
PLL Sleep mode with
CLKS1/2 = CLKP1 =
32MHz,
CLKP2 = 16MHz
ICCSPLL
Value
Condition (at TA)
Y
Symbol
AR
Parameter
mA
mA
mA
mA
mA
FME-MB96390 rev 3
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Symbol
Power supply current in Sleep
modes*
ICCSSUB
+25˚C
0.3
0.5
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C
0.7
2
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 1
+25˚C
1.6
mA
0.04
0.12
+125˚C
0.43
1.55
PLL Timer mode with
CLKMC = 4MHz, CLKPLL
= 48MHz
+25˚C
1.5
2
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
2
3.6
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
+25˚C
0.35
0.55
+125˚C
0.75
2
+25˚C
0.1
0.18
+125˚C
0.5
1.6
IM
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
Remarks
Y
0.44
+25˚C
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
FME-MB96390 rev 3
0.15
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
EL
ICCTMAIN
0.05
+125˚C
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
Unit
mA
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
PR
Power supply current in Timer
modes*
Max
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKRC stopped)
ICCTPLL
Typ
AR
ICCSRCL
Value
Condition (at TA)
IN
Parameter
mA
mA
mA
61
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
ICCTRCH
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
0.5
+125˚C
0.75
2
+25˚C
0.07
0.15
+125˚C
0.46
1.6
+25˚C
0.3
0.45
+125˚C
mA
mA
0.03
0.1
+125˚C
0.41
1.55
Sub Timer mode with
CLKSC = 32kHz
+25˚C
0.035
0.1
(CLKMC, CLKPLL and
CLKRC stopped)
+125˚C
0.42
1.55
VRCR:LPMB[2:0] = 110B
+25˚C
0.02
0.08
(Core voltage at 1.8V)
+125˚C
0.4
1.5
VRCR:LPMB[2:0] = 000B
+25˚C
0.015
0.06
(Core voltage at 1.2V)
+125˚C
0.3
1.2
+25˚C
90
140
+125˚C
100
150
-
3
4.5
EL
Remarks
mA
+25˚C
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
Unit
mA
mA
mA
ICCH
Power supply current for active Low
Voltage detector
ICCLVD
Power supply current for active
Clock modulator
ICCCLOMO
62
0.35
1.9
PR
Power supply current in Stop Mode
+25˚C
0.65
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
ICCTSUB
Max
IM
ICCTRCL
Typ
IN
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
Power supply current in Timer
modes*
Value
Condition (at TA)
Y
Symbol
AR
Parameter
Low voltage detector enabled (RCR:LVDE = 1)
Clock modulator enabled
(CMCR:PDX = 1)
mA
µA
This current must be
added to all Power
supply currents above
mA
Must be added to all
current above
FME-MB96390 rev 3
MB96390 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Symbol
Flash Write/Erase
current
ICCFLASH
Current for one Flash
module
Input capacitance
CIN
-
Input capacitance
Value
Condition (at TA)
-
-
CIN
-
Remarks
Typ
Max
Unit
15
40
mA
Must be added to all
current above
15
30
pF
High current outputs
pF
Other than C, AVCC,
AVSS, AVRH, AVRL,
VCC, VSS, DVCC, DVSS,
High current outputs
5
15
Y
Parameter
PR
EL
IM
IN
AR
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of
the Hardware Manual for further details about voltage regulator control.
FME-MB96390 rev 3
63
MB96390 Series
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
fFCI
fCL
X0A
Clock frequency
fCR
Max
3
-
16
MHz When using a crystal oscillator, PLL off
0
-
16
MHz
When using an opposite phase external
clock, PLL off
3.5
-
16
MHz
When using a crystal oscillator or opposite phase external clock, PLL on
0
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL off
3.5
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL on
32
32.768
100
kHz When using an oscillation circuit
0
-
100
kHz
When using an opposite phase external
clock
0
-
50
kHz
When using a single phase external
clock
50
100
200
kHz
When using slow frequency of RC oscillator
2
4
MHz
When using fast frequency of RC oscillator
1
RC clock stabilization time
tRCSTAB
-
PLL Clock frequency
fCLKVCO
-
PLL Phase Jitter
TPSKEW
-
Input clock pulse
width
PWH, PWL
X0,X1
64
Applied after any reset and when activating the RC oscillator.
EL
64 RC clock cycles
64
-
200
MHz
Permitted VCO output frequency of PLL
(CLKVCO)
-
-
± 5
ns
For CLKMC (PLL input clock) ≥ 4MHz,
jitter coming from external oscillator,
crystal or resonator is not covered
8
-
-
ns
Duty ratio is about 30% to 70%
5
-
-
µs
PR
Input clock pulse
width
PWHL, PWLL X0A,X1A
Remarks
Typ
X0
X0A, X1A
Clock frequency
Unit
Min
Y
X0, X1
Value
AR
Clock frequency
fC
Pin
IN
Clock frequency
Symbol
IM
Parameter
FME-MB96390 rev 3
MB96390 Series
tCYL
VIH
X0
VIL
PWH
AR
tCYLL
Y
PWL
X0A
PWHL
VIH
VIL
PR
EL
IM
IN
PWLL
FME-MB96390 rev 3
65
MB96390 Series
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Core Voltage Settings
Symbol
Internal CPU clock frequency (CLKB), internal
peripheral clock frequency
(CLKP1)
fCLKB, fCLKP1
fCLKP2
Min
Max
Min
Max
0
92
0
96
0
72
0
80
0
52
0
36
0
28
Unit
Remarks
MHz
Others than below
MHz
MB96F395
0
56
MHz
Others than below
0
40
MHz
MB96F395
0
32
MHz
PR
EL
IM
IN
Internal peripheral clock
frequency (CLKP2)
fCLKS1, fCLKS2
1.9V
Y
Internal System clock frequency (CLKS1 and
CLKS2)
1.8V
AR
Parameter
66
FME-MB96390 rev 3
MB96390 Series
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Reset input time
Symbol
Pin
tRSTL
RSTX
Value
Min
Typ
Max
500
-
-
tRSTL
ns
0.2 VCC
PR
EL
IM
IN
0.2 VCC
Remarks
AR
RSTX
Unit
Y
Parameter
FME-MB96390 rev 3
67
MB96390 Series
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Power on rise time
Power off time
Symbol
Pin
tR
tOFF
Value
Typ
Max
Vcc
0.05
-
30
ms
Vcc
1
-
-
ms
Remarks
AR
tR
2.7V
VCC
Unit
Min
Y
Parameter
0.2 V
0.2 V
0.2 V
IN
tOFF
IM
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
Rising edge of 50 mV/ms
maximum is allowed
PR
EL
3V
68
FME-MB96390 rev 3
MB96390 Series
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol
Pin
Value
Condition
INTn(_R)
NMI(_R)
Min
Max
200
⎯
Unit
NMI
General Purpose IO
Y
tINH
tINL
External Interrupt
ns
Pnn_m
Input pulse
width
Used Pin input function
TINn(_R)
⎯
TTGn(_R)
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)
⎯
AR
ADTG(_R)
FRCKn(_R)
INn(_R)
ns
Reload Timer
PPG Trigger input
AD Converter Trigger
Free Running Timer
external clock
Input Capture
VIH
VIH
VIL
VIL
IM
External Pin input
IN
Note : Relocated Resource Inputs have same characteristics
tINL
PR
EL
tINH
FME-MB96390 rev 3
69
MB96390 Series
Slew Rate High Current Outputs
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Output
rise/fall
time
tR30
tF30
Pin
Condition
I/O circuit type M
Output
driving
strength
set to
“30mA”
Value
Min
Max
15
⎯
• Slew rate output timing
VH
VL
Remarks
ns
AR
Note : Relocated Resource Inputs have same characteristics
VH
Unit
Y
Parameter Symbol
VL
VH = VOL30 + 0.9 × (VOH30 - VOL30)
VL = VOL30 + 0.1 × (VOH30 - VOL30)
tF30
PR
EL
IM
IN
tR30
70
FME-MB96390 rev 3
MB96390 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must then be increased by 10ns.
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
Pin
Condition
Serial clock cycle time
tSCYCI
SCKn
4 tCLKP1
⎯
4 tCLKP1
⎯
ns
SCK ↓ → SOT delay
time
tSLOVI
SCKn,
SOTn
-20
+20
-30
+30
ns
SOT → SCK ↑ delay
time
tOVSHI
SCKn,
SOTn
N*tCLKP1
- 20 *1
⎯
N*tCLKP1 30 *1
⎯
ns
Valid SIN → SCK ↑
tIVSHI
SCKn,
SINn
tCLKP1 +
45
⎯
tCLKP1 +
55
⎯
ns
SCK ↑ → Valid SIN
hold time
tSHIXI
SCKn,
SINn
0
⎯
0
⎯
ns
Serial clock “L” pulse
width
tSLSHE
SCKn
tCLKP1 +
10
⎯
tCLKP1 +
10
⎯
ns
Serial clock “H” pulse
width
tSHSLE
SCKn
tCLKP1 +
10
⎯
tCLKP1 +
10
⎯
ns
SCK ↓ → SOT delay
time
tSLOVE
SCKn,
SOTn
⎯
2 tCLKP1
+ 45
⎯
2 tCLKP1
+ 55
ns
Valid SIN → SCK ↑
tIVSHE
tCLKP1/2
+ 10
⎯
tCLKP1/2 +
10
⎯
ns
SCK ↑ → Valid SIN
hold time
tSHIXE
SCKn,
SINn
tCLKP1 +
10
⎯
tCLKP1 +
10
⎯
ns
SCK fall time
tFE
SCKn
⎯
20
⎯
20
ns
SCK rise time
tRE
SCKn
⎯
20
⎯
20
ns
AR
Y
Symbol
IM
IN
Internal Shift
Clock Mode
External Shift
Clock Mode
SCKn,
SINn
EL
Parameter
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Unit
Min
Max
Min
Max
PR
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
FME-MB96390 rev 3
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
3
7*tCLKP1, 8*tCLKP1
4
...
...
71
MB96390 Series
tSCYCI
SCK for
ESCR:SCES = 0
0.8*VCC
0.2*VCC
0.2*VCC
SCK for
ESCR:SCES = 1
0.8*VCC
Y
0.8*VCC
0.2*VCC
tOVSHI
AR
tSLOVI
0.8*VCC
SOT
0.2*VCC
tSHIXI
tIVSHI
VIH
VIH
VIL
VIL
IN
SIN
IM
Internal Shift Clock Mode
tSLSHE
SCK for
ESCR:SCES = 0
VIH
SIN
VIL
VIL
tSLOVE
PR
SOT
VIH
VIH
VIL
tFE
VIH
VIL
VIL
EL
SCK for
ESCR:SCES = 1
VIH
tSHSLE
tRE
0.8*VCC
0.2*VCC
tIVSHE
tSHIXE
VIH
VIH
VIL
VIL
External Shift Clock Mode
72
FME-MB96390 rev 3
MB96390 Series
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Standard-mode
Symbol
Fast-mode*1
Unit
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
Data hold time
SCL↓→SDA↓↑
tHDDAT
Data set-up time
SDA↓↑→SCL↑
tSUDAT
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
AR
Hold time (repeated) START condition
SDA↓→SCL↓
4.7
⎯
0.6
⎯
µs
0
3.45
0
0.9
µs
250
⎯
100
⎯
ns
4.0
⎯
0.6
⎯
µs
IN
SCL clock frequency
Y
Min
tBUS
4.7
⎯
1.3
⎯
µs
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
20 + 0.1*Cb *2
250
20 + 0.1*Cb *2
250
ns
Capacitive load for each bus line
Cb
⎯
400
⎯
400
pF
tSP
n/a
n/a
0
1*tCLKP1*3
ns
Pulse width of spikes which will be suppressed by input noise filter
IM
Bus free time between a STOP and START
condition
EL
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
SDA
tLOW
SCL
tHDSTA
PR
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
tSUDAT
tHDDAT
tHIGH
tBUS
tHDSTA
tSUSTA
tSUSTO
• VOH = 0.7 * VCC
• VOL = 0.3 * VCC
• CMOS Hysteresis 0.7/0.3 input selected
FME-MB96390 rev 3
73
MB96390 Series
5. Analog Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Resolution
-
Total error
Value
Unit
Typ
Max
-
-
-
10
bit
-
-
-
-
±3
LSB
Nonlinearity error
-
-
-
-
± 2.5
LSB
Differential nonlinearity
error
-
-
-
± 1.9
Zero transition voltage
VOT
ANn
AVRL - AVRL+ AVRL +
1.5 LSB 0.5 LSB 2.5 LSB
V
Full scale transition
voltage
VFST
ANn
AVRH - AVRH - AVRH +
3.5 LSB 1.5 LSB 0.5 LSB
V
Compare time
-
-
Sampling time
-
-
AVRH
AVRL
Power supply current
Reference voltage current
Offset between input
channels
1.2
AR
3.0V ≤ ΑVCC < 4.5V
-
-
µs
4.5V ≤ ΑVCC ≤ 5.5V
-
-
µs
3.0V ≤ ΑVCC < 4.5V
-
+1
TA ≤ 105 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
105 ˚C < TA ≤ 125 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
-1.2
-
+1.2
AVRL
-
AVRH
V
AVRH
0.75
AVcc
-
AVcc
V
AVRL
AVSS
-
0.25
AVCC
V
AVcc
-
2.5
5
mA A/D Converter active
ANn
PR
IA
µs
IN
VAIN
-
2.0
IM
Analog input voltage
range
ANn
4.5V ≤ ΑVCC ≤ 5.5V
EL
IAIN
µs
-
0.5
LSB
16,500
1.0
-1
Analog input leakage
current (during conversion)
Reference voltage
range
-
Remarks
Y
Min
A/D Converter not operated
IAH
AVcc
-
-
5
µA
IR
AVRH/
AVRL
-
0.7
1
mA A/D Converter active
IRH
AVRH/
AVRL
-
-
5
µA
-
ANn
-
-
4
LSB
A/D Converter not operated
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
74
FME-MB96390 rev 3
MB96390 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Y
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
AR
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
IM
Digital output
1.5 LSB
IN
Actual conversion
characteristics
003
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
002
001
EL
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
[LSB]
PR
Total error of digital output “N” =
N: A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
FME-MB96390 rev 3
75
MB96390 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
N+1
VNT (actual
measurement value)
004
003
Actual conversion
characteristics
N
N−1
002
Ideal characteristics
N−2
001
VOT (actual measurement value)
AVRH
Analog input
Nonlinearity error of digital output N =
Actual conversion
characteristics
V (N+1) T − VNT
1 LSB
1 LSB =
VFST − VOT
1022
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
IM
Differential nonlinearity error of digital output N =
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
AVRL
IN
AVRL
Y
VFST (actual
measurement
value)
Actual conversion
characteristics
AR
Digital output
3FD
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FE
[LSB]
−1 LSB [LSB]
[V]
PR
EL
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
76
FME-MB96390 rev 3
MB96390 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal
sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and
the AVcc voltage level. The following replacement model can be used for the calculation:
Analog
input
Rext
RADC
Y
MCU
Comparator
Source
CIN
CADC
AR
Cext
Sampling switch
IM
IN
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
CIN: capacitance of MCU input pin: 15pF (max)
RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V
12kΩ (max) for 3.0V ≤ AVcc < 4.5V
CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement
model above can be used:
EL
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this
case the internal sampling capacitance CADC will be charged out of this external capacitance.
PR
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input
leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total
leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL
cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
FME-MB96390 rev 3
77
MB96390 Series
6. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
IA5ALMF
Power supply current
IA5ALMS
AVCC
IA5ALMH
ALARM pin input voltage range
VALIN
External low threshold
high->low transition
VEVTL(H->L)
External low threshold
low->high transition
VEVTL(L->H)
External high threshold
high->low transition
VEVTH(H->L)
External high threshold
low->high transition
VEVTH(L->H)
Internal low threshold
high->low transition
VIVTL(H->L)
Internal low threshold
low->high transition
VIVTL(L->H)
Internal high threshold
high->low transition
VIVTH(H->L)
Internal high threshold
low->high transition
VIVTH(L->H)
Comparison time
Power-up stabilization
time after enabling
alarm comparator
Slow/Fast mode transition time
78
-
25
45
-
7
-1
-3
0
-
13
-
µA
Alarm comparator
enabled in fast
mode (one channel)
µA
Alarm comparator
enabled in slow
mode (one channel)
Alarm comparator
disabled
µA
-
+1
µA TA = 25 ˚C
-
+3
µA TA = 125 ˚C
-
AVCC
V
-
V
0.36 * AVCC 0.36 * AVCC
+0.1
+0.25
-
0.78 * AVCC 0.78 * AVCC
+0.1
+0.25
0.9
Remarks
5
0.78 * AVCC 0.78 * AVCC
-0.25
-0.1
ALARM0,
ALARM1
Unit
-
0.36 * AVCC 0.36 * AVCC
-0.25
-0.1
V
INTREF = 0
V
V
1.1
-
V
1.3
1.55
V
INTREF = 1
2.2
2.4
-
V
-
2.6
2.85
V
VHYS
50
-
300
mV
tCOMPF
-
0.1
1
µs
CMD = 1 (fast)
tCOMPS
-
1
10
µs
CMD = 0 (slow)
tPD
-
1
10
ms
tCMD
-
100
500
µs
Threshold levels
specified above are
not guaranteed
within this time
PR
Switching hysteresis
Max
IM
IALIN
Typ
EL
ALARM pin input current
Min
Y
Pin
AR
Symbol
IN
Parameter
FME-MB96390 rev 3
MB96390 Series
Comparator
Output
Y
H
VxVTx(H->L)
VHYS
VALIN
PR
EL
IM
IN
VxVTx(L->H)
AR
L
FME-MB96390 rev 3
79
MB96390 Series
7. Low Voltage Detector characteristics
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Remarks
75
µs
After power-up or change
of detection level
2.7
2.9
V
CILCR:LVL[3:0]=”0000”
VDL1
2.9
3.1
V
CILCR:LVL[3:0]=”0001”
Level 2
VDL2
3.1
3.3
V
CILCR:LVL[3:0]=”0010”
Level 3
VDL3
3.5
3.75
V
CILCR:LVL[3:0]=”0011”
Level 4
VDL4
3.6
3.85
V
CILCR:LVL[3:0]=”0100”
Level 5
VDL5
3.7
3.95
V
CILCR:LVL[3:0]=”0101”
Level 6
VDL6
3.8
4.05
V
CILCR:LVL[3:0]=”0110”
Level 7
VDL7
3.9
4.15
V
CILCR:LVL[3:0]=”0111”
Level 8
VDL8
4.0
4.25
V
CILCR:LVL[3:0]=”1000”
Level 9
VDL9
4.1
4.35
V
Level 10
VDL10
not used
Level 11
VDL11
not used
Level 12
VDL12
not used
Level 13
VDL13
not used
Level 14
VDL14
not used
Level 15
VDL15
not used
TLVDSTAB
-
Level 0
VDL0
Level 1
EL
Max
Y
Unit
Min
AR
Stabilization time
Value
IN
Symbol
CILCR:LVL[3:0]=”1001”
IM
Parameter
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
V
For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- .
dt
µs
Faster variations are regarded as noise and may not be detected.
PR
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
“Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to
3.0V).
80
FME-MB96390 rev 3
MB96390 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
Y
VDLx, Max
VDLx, Min
dV
AR
dt
Low Voltage Reset Assertion
Power Reset Extension Time
PR
EL
IM
IN
Normal Operation
Time [s]
FME-MB96390 rev 3
81
MB96390 Series
8. FLASH memory program/erase characteristics
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Unit
Remarks
3.6
s
Without erasure pre-programming time
n*0.9
n*3.6
s
Without erasure pre-programming time (n is the number of
Flash sector of the device)
-
23
370
us
10 000
-
-
cycle
20
-
-
year
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
Program/Erase cycle
Flash data retention time
Without overhead time for submitting write command
AR
Min
Y
Parameter
*1
PR
EL
IM
IN
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
82
FME-MB96390 rev 3
PR
EL
IM
IN
AR
Y
MB96390 Series
FME-MB96390 rev 3
83
MB96390 Series
■ EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes.
Y
Common condition for all operation modes:
• VCC = AVCC = 5.0V
• Main clock = 4MHz external clock
• Sub clock = 32kHz external clock
Mode name
Details
AR
Operation mode details:
PLL Run mode current ICCPLL with the following settings:
• fCLKS1 = fCLKS2 = 80MHz
• fCLKB = fCLKP1 = 40MHz
• fCLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 1 Flash/ROM wait states (MTCRA=6B09H)
• RC oscillator and Sub oscillator stopped
PLL Run 24
PLL Run mode current ICCPLL with the following settings:
• fCLKS1 = fCLKS2 = 48MHz
• fCLKB = fCLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 0 Flash/ROM wait states (MTCRA=2208H)
• RC oscillator and Sub oscillator stopped
Main Run
Main Run mode current ICCMAIN with the following settings:
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Sub oscillator stopped
RC Run 2M
RC Run mode current ICCRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
84
PR
EL
IM
IN
PLL Run 40
FME-MB96390 rev 3
MB96390 Series
Mode name
Details
RC Run mode current ICCRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
Sub Run
Sub Run mode current ICCSUB with the following settings:
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Main oscillator stopped
PLL Sleep 40
PLL Sleep mode current ICCSPLL with the following settings:
• fCLKS1 = fCLKS2 = 80MHz
• fCLKP1 = 40MHz
• fCLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
PLL Sleep 24
PLL Sleep mode current ICCSPLL with the following settings:
• fCLKS1 = fCLKS2 = 48MHz
• fCLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
Main Sleep
Main Sleep mode current ICCSMAIN with the following settings:
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, RC oscillator and Sub oscillator stopped
RC Sleep 2M
RC Sleep mode current ICCSRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, Main oscillator and Sub oscillator stopped
RC Sleep 100k
RC Sleep mode current ICCSRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
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RC Run 100k
FME-MB96390 rev 3
85
MB96390 Series
Mode name
Details
Sub Sleep mode current ICCSSUB with the following settings:
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
PLL Timer 48
PLL Timer mode current ICCTPLL with the following settings:
• fCLKS1 = fCLKS2 = 48MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
Main Timer
Main Timer mode current ICCTMAIN with the following settings:
• fCLKS1 = fCLKS2 = 4MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Sub oscillator stopped
RC Timer 2M
RC Timer mode current ICCTRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = 2MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k
RC Timer mode current ICCTRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
Sub Timer
Sub Timer mode current ICCTSUB with the following settings:
• fCLKS1 = fCLKS2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
Stop 1.8V
Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B)
Stop 1.2V
Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B)
86
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Sub Sleep
FME-MB96390 rev 3
MB96390 Series
MB96F395 PLL Run and Sleep mode currents
40
PLL Run 40
30
Y
PLL Run 24
10
AR
Icc[mA]
20
PLL Sleep 40
0
-60
-40
-20
0
IN
PLL Sleep 24
20
40
60
80
100
120
Ta [˚C]
IM
MB96F395 operation modes with medium currents
5
Main Run
Icc[mA]
3
PR
RC Run 2M
EL
4
2
PLL Timer 48
Main Sleep
1
RC Sleep 2M
0
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96390 rev 3
87
MB96390 Series
MB96F395 Low power mode currents
1
RC Run 100k
0.1
Main Timer
Y
Icc[mA]
Sub
RC Timer 2M
AR
RC Sleep 100k
Sub Sleep
Sub Timer
RC Timer 100k
0.01
Stop 1.8V
0.001
-60
-40
-20
0
20
IN
Stop 1.2V
40
60
80
100
120
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Ta [˚C]
88
FME-MB96390 rev 3
MB96390 Series
2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL
Run mode at different frequencies and Flash timing settings.
IN
AR
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Measurement conditions:
• VCC = AVCC = 5.0V
• Ta = 25˚C
• fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram
• fCLKS2 = fCLKS1
• fCLKP1 = fCLKB
• fCLKP2 = fCLKB/2
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram
• Main clock = 4MHz external clock
• Flash memory timing settings:
• MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB)
• MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB)
• MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB)
• MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB)
• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash wait states: 0.5
• 1 Flash wait states: 0.33
• 2 Flash wait states: 0.25
IM
MB96F395 PLL Run mode currents
40
30
25
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
20
PR
ICCPLL (mA)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
EL
35
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
15
10
2 Flash wait states
(CLKS1=CLKB, 1.9V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
: Specified in "DC characteristics"
5
0
0
4
8
12
16
20
24
28
32
36
40
CLKB/CLKP1 (MHz)
FME-MB96390 rev 3
89
MB96390 Series
■ PACKAGE DIMENSION MB96F39x LQFP 100P
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Y
100-pin plastic LQFP
AR
Sealing method
100-pin plastic LQFP
(FPT-100P-M20)
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
16.00±0.20(.630±.008)SQ
51
76
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Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
* 14.00±0.10(.551±.004)SQ
75
Mounting height
IN
(FPT-100P-M20)
Plastic mold
INDEX
100
1
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50
0.08(.003)
Details of "A" part
+0.20
26
0.20±0.05
(.008±.002)
0.08(.003)
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
25
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
M
0.145±0.055
(.0057±.0022)
©2005-2008
FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2
C
2005 FUJITSU LIMITED F100031S-c-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
90
FME-MB96390 rev 3
MB96390 Series
■ ORDERING INFORMATION
Flash/ROM
Subclock
MB96F395YSB PMC-GSE2 *1
MB96F395RSB PMC-GSE2
No
*1
MB96F395YWB PMC-GSE2
*1
Flash A (160KB)
Yes
MB96F395RWB PMC-GSE2 *1
Emulated by ext.
RAM
Yes
Package
Yes
No
Yes
100 pin Plastic LQFP
(FPT-100P-M20)
No
No
416 pin Plastic BGA
(BGA-416P-M02)
AR
MB96V300BRB-ES
(for evaluation)
Persistent
Low Voltage Reset
Y
Part number
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
IN
This datasheet is also valid for the following outdated devices:
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MB96F395YSA, MB96F395RSA, MB96F395YWA, MB96F395RWA.
FME-MB96390 rev 3
91
MB96390 Series
■ REVISION HISTORY
Date
Modification
Prelim 1
2008-04-18
Initial Draft
Prelim 2
2009-01-09
• Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly
style changes and official notes and disclaimer added)
• specified AD converter channel offset to 4LSB
• package code of MB96V300 corrected in ordering information
• Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm, Max
50kOhm -> 65kOhm
• Added voltage condition to pull-up resistance and LCD divide resistance spec
• Ordering information: column “Flash/ROM” added, column “Remarks” removed
• Official package dimension drawing with additional notes added
• Empty pages removed
• Alarm comparator: Power supply current max values increased, comparison time
reduced, mode transition time and power-up stabilization time newly added
• Handling devices: Notes added about Serial communication and about using
ceramic resonators.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• All ICC (Run/Sleep/Timer/Stop mode) currents adjusted to evaluation results
• IO map cleaned up (removed not available resources)
• Absolute maximum ratings: Pd spec corrected
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
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Revision
92
FME-MB96390 rev 3
MB96390 Series
Date
Modification
Prelim 3
2010-06-25
• AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg
• Note added that PLL phase jitter spec does not include jitter coming from Main
clock
• Alarm comparator: Maximum power-up stabilization time increased to 10ms
• Note added in DC characteristics how to select driving strength of ports
• I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and Condition
removed
• I/O Circuit type: Note added for type “N” (slew rate control according to I2C spec)
• Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new spec
items in PLL Run/Sleep mode, small adjustment of most other values)
• Prepared Example characteristics
• Package dimension: Added the following sentence under the figure: “Please
confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/”
• AD converter: Impact of input pin capacitance and external capacitance added
to formula for calculation of the sampling time
• Added specification of RC clock stabilization time
• Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’
• Feature description PPG: ‘Reload timer overflow as clock input’ corrected to
‘Reload timer underflow as clock input’
• Company name updated on the cover page: Fujitsu Microelectronics Limited ->
Fujitsu Semiconductor Limited
• Ordering information: MB96F395**A -> MB96F395**B
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Revision
FME-MB96390 rev 3
93
MB96390 Series
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Y
FME-MB96390 rev 3
PR
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MB96390 Series
FME-MB96390 rev 3
95
MB96390 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
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North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Specifications are subject to change without notice. For further information please contact each office.
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All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
96
FME-MB96390 rev 3