LT4363 High Voltage Surge Stopper with Current Limit FEATURES DESCRIPTION n n n n n n n n n n Withstands Surges Over 80V with VCC Clamp Wide Operating Voltage Range: 4V to 80V Adjustable Output Clamp Voltage Fast Overcurrent Limit: Less Than 5µs Reverse Input Protection to –60V Adjustable UV/OV Comparator Thresholds Low 7µA Shutdown Current Shutdown Pin Withstands –60V to 100V Adjustable Fault Timer Controls N-Channel MOSFET Less Than 1% Retry Duty Cycle During Faults, LT4363-2 n Available in 12-Pin (4mm × 3mm) DFN, 12-Pin MSOP or 16-Pin SO Packages The LT®4363 surge stopper protects loads from high voltage transients. It regulates the output during an overvoltage event, such as load dump in vehicles, by controlling the gate of an external N-channel MOSFET. The output is limited to a safe value allowing the loads to continue functioning. The LT4363 also monitors the voltage drop between the SNS and OUT pins to protect against overcurrent faults. An internal amplifier limits the voltage across the current sense resistor to 50mV. In either fault condition, a timer is started inversely proportional to MOSFET stress. Before the timer expires, the FLT pin pulls low to warn of an impending power down. If the condition persists, the MOSFET is turned off. The LT4363-1 remains off until reset whereas the LT4363-2 restarts after a cool down period. APPLICATIONS Two precision comparators can monitor the input supply for overvoltage (OV) and undervoltage (UV) conditions. When the potential is below the UV threshold, the external MOSFET is kept off. If the input supply voltage is above the OV threshold, the MOSFET is not allowed to turn back on. Back-to-back MOSFETs can be used in lieu of a Schottky diode for reverse input protection, reducing voltage drop and power loss. A shutdown pin reduces the quiescent current to less than 7µA during shutdown. n n n n n Automotive/Avionic Surge Protection Hot Swap™/Live Insertion High Side Switch for Battery Powered Systems Intrinsic Safety Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No RSENSE, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 4A, 12V Overvoltage Output Regulator with 150V Surge Protection FDB33N25 VIN 12V 10mΩ 22µF 1k 10Ω 0.1µF 127k VCC GATE SNS 4.99k SHDN GND ENOUT GND TMR VCC DC/DC CONVERTER LT4363-2 49.9k OV 80V INPUT SURGE CTMR = 6.8µF ILOAD = 500mA VIN 20V/DIV OUT SHDN UV OUTPUT CLAMP AT 16V 57.6k FB SMAJ58A Overvoltage Protector Regulates Output at 27V During Transient FLT 4363 TA01 FAULT 12V VOUT 20V/DIV 27V ADJUSTABLE CLAMP 12V 100ms/DIV 4363 TA01b 0.1µF 4363fa 1 LT4363 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) VCC, SHDN, UV, OV.................................... –60V to 100V SNS, OUT.................................................. –0.3V to 100V SNS to OUT.................................................. –30V to 30V GATE (Note 3)...................................–0.3V to SNS + 10V ENOUT, FLT............................................... –0.3V to 100V FB.............................................................. –0.3V to 5.5V TMR.......................................................................0.5mA Operating Temperature Range LT4363C................................................... 0°C to 70°C LT4363I.................................................–40°C to 85°C Storage Temperature Range DE12................................................... –65°C to 125°C MS, SO............................................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS, SO.............................................................. 300°C PIN CONFIGURATION LT4363-1 LT4363-1 LT4363-1 TOP VIEW TOP VIEW FB 1 12 TMR OUT 2 11 ENOUT 10 FLT 9 GND 5 8 UV 6 7 GND SNS 3 GATE 4 VCC SHDN 13 GND TOP VIEW FB OUT SNS GATE VCC SHDN 12 11 10 9 8 7 TMR ENOUT FLT GND UV GND MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 135°C/W DE PACKAGE 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) IS GND, CONNECTION TO PCB OPTIONAL LT4363-2 1 2 3 4 5 6 OUT 1 16 FB SNS 2 15 TMR NC 3 14 NC GATE 4 13 ENOUT NC 5 12 FLT VCC 6 11 GND NC 7 10 UV SHDN 8 9 S PACKAGE 16-LEAD PLASTIC SO TJMAX = 125°C, θJA = 80°C/W LT4363-2 LT4363-2 TOP VIEW TOP VIEW FB 1 12 TMR OUT 2 11 ENOUT 10 FLT 9 GND 5 8 UV 6 7 OV SNS 3 GATE 4 VCC SHDN 13 GND GND DE PACKAGE 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 13) IS GND, CONNECTION TO PCB OPTIONAL TOP VIEW FB OUT SNS GATE VCC SHDN 1 2 3 4 5 6 12 11 10 9 8 7 MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 135°C/W TMR ENOUT FLT GND UV OV OUT 1 16 FB SNS 2 15 TMR NC 3 14 NC GATE 4 13 ENOUT NC 5 12 FLT VCC 6 11 GND NC 7 10 UV SHDN 8 9 OV S PACKAGE 16-LEAD PLASTIC SO TJMAX = 125°C, θJA = 80°C/W 4363fa 2 LT4363 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4363CDE-1#PBF LT4363CDE-1#TRPBF 43631 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C LT4363IDE-1#PBF LT4363IDE-1#TRPBF 43631 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C LT4363CDE-2#PBF LT4363CDE-2#TRPBF 43632 12-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C LT4363IDE-2#PBF LT4363IDE-2#TRPBF 43632 12-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C LT4363CMS-1#PBF LT4363CMS-1#TRPBF 43631 12-Lead Plastic MSOP 0°C to 70°C LT4363IMS-1#PBF LT4363IMS-1#TRPBF 43631 12-Lead Plastic MSOP –40°C to 85°C LT4363CMS-2#PBF LT4363CMS-2#TRPBF 43632 12-Lead Plastic MSOP 0°C to 70°C LT4363IMS-2#PBF LT4363IMS-2#TRPBF 43632 12-Lead Plastic MSOP –40°C to 85°C LT4363CS-1#PBF LT4363CS-1#TRPBF LT4363S-1 16-Lead Plastic SO 0°C to 70°C LT4363IS-1#PBF LT4363IS-1#TRPBF LT4363S-1 16-Lead Plastic SO –40°C to 85°C LT4363CS-2#PBF LT4363CS-2#TRPBF LT4363S-2 16-Lead Plastic SO 0°C to 70°C LT4363IS-2#PBF LT4363IS-2#TRPBF LT4363S-2 16-Lead Plastic SO –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VCC Operating Voltage Range LT4363C LT4363I l l ICC VCC Supply Current SHDN Open, OUT = SNS = 12V SHDN = 0V, OUT = SNS = 0V l IR Reverse Input Current VCC = –60V, SHDN, UV, OV Open VCC = SHDN = UV = OV = –60V ΔVGATE GATE Drive ΔVGATE = (GATE – SNS);VCC = OUT VCC = 4V; IGATE = –0.5µA, 0µA 9V ≤ VCC ≤ 80V; IGATE = –1µA, 0µA TYP 4 4.5 UNITS 80 80 V V 0.7 7 1.2 20 40 mA µA µA –0.5 –3 –3 –10 mA mA l l l MAX l l 4.5 10 13 16 V V –35 –40 µA µA IGATE(UP) GATE Pull-Up Current VCC = GATE = OUT = 12V VCC = GATE = OUT = 48V l l –10 –10 –20 –25 IGATE(DN) GATE Pull-Down Current Overvoltage: FB = 1.5V, GATE = 12V, OUT = 5V Overcurrent: ΔVSNS = 150mV, VGATE = 10V, OUT = 0V Shutdown/UV Mode:SHDN = 0V, GATE = 10V UV = 1V, GATE = 10V l l l l 75 50 50 200 150 100 1000 1000 1.25 1.275 1.3 V ±0.2 ±1 µA mA mA µA µA VFB FB Servo Voltage GATE = 12V; OUT = 8V l IFB FB Input Current VFB = 1.275V l ΔVSNS Current Limit Sense Voltage ΔVSNS = (SNS – OUT) VCC = 12V, OUT = 3V to 12V VCC = 48V, OUT = 3V to 48V l l 43 45 50 52 58 59 mV mV Current Limit Foldback VCC = 12V, OUT = 0V to 1V VCC = 48V, OUT = 0V to 1V l l 15 16 25 27 35 36 mV mV SNS Input Current OUT = SNS = 3V to 80V OUT = SNS = 0V l l 20 –10 30 –15 µA µA ISNS 4363fa 3 LT4363 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ITMR TMR Pull-up Current, Overvoltage TMR = 1V, FB = 1.5V, ΔVDS = 0.5V TMR = 1V, FB = 1.5V, ΔVDS = 75V l l –1.7 –42 –4 –50 –6 –58 µA µA TMR Pull-up Current, OV Warning TMR = 1.325V, FB = 1.5V, ΔVDS = 0.5V l –3 –5 –7 µA TMR Pull-up Current, Overcurrent TMR = 1V, ΔVSNS = 100mV, ΔVDS = 0.5V TMR = 1V, ΔVSNS = 100mV, ΔVDS = 80V l l –5 –190 –9 –250 –13 –310 µA µA TMR Pull-up Current, Cool Down TMR = 3V, FB = 1.5V, ΔVSNS = 0V, ΔVDS = 0V l –1 –2.3 –3.5 µA TMR Pin Pull-down Current, Cool Down VTMR = 3V, FB = 1.5V, ΔVSNS = 0V, ΔVDS = 0V l 1 2 4 µA VTMR(F) VTMR(G) VTMR(R) TMR Fault Threshold TMR Gate Off Threshold TMR Restart Threshold TMR Rising TMR Rising TMR Falling, LT4363-2 l l l 1.235 1.335 0.47 1.275 1.375 0.5 1.31 1.41 0.53 V V V ΔVTMR Early Warning Window VTMR(G) – VTMR(F) l 80 100 120 mV VTMR(H) TMR Cool Down High Threshold VCC = 7V to 80V, TMR Rising l 3.7 4.3 5 V VUV UV Input Threshold UV Rising l 1.24 1.275 1.31 V VUV(HYST) UV Input Hysteresis VOV OV Input Threshold OV Rising l 1.24 1.275 VOV(HYST) OV Input Hysteresis IIN UV, OV Input Current UV = 1.275V UV = –60V l l ±0.2 –1 ±1 –2 ILEAK FLT, ENOUT Leakage Current FLT, ENOUT = 80V l ±0.5 ±2.5 µA VOL FLT, ENOUT Output Low ISINK = 0.1mA ISINK = 2mA l l 300 2 800 9 mV V ΔVOUT(TH) OUT High Threshold ΔVOUT = VCC – VOUT, ENOUT From Low to High l 0.25 0.5 0.75 V ENOUT From High to Low l 1.9 2.7 3.6 V l l 0.25 0.25 0.5 1 mA mA 1.4 1.7 2.1 V V 2.2 V ΔVOUT(RST) OUT Reset Threshold 12 7.5 IOUT OUT Input Current VCC = OUT = 12V, SHDN Open VCC = OUT = 12V, SHDN = 0V VSHDN SHDN Threshold VCC = 4V to 80V l VSHDN(Z) SHDN Open Voltage mV 1.31 VCC = 4V to 80V 0.6 0.4 l ISHDN SHDN Current SHDN = 0.4V l tRESET SHDN Reset Time SHDN ≤ 0.4V; LT4363-1 l –1 –4 D Retry Duty Cycle; Overvoltage VCC = 80V, OUT = 16V, FB = 1.5V; LT4363-2 l 1 Retry Duty Cycle; Output Short VCC = 12V, OUT = 0V, ∆VSNS = 100mV; LT4363-2 l V mV µA mA –8 µA 100 µs 2 % 0.76 1 % tOFF(UV) Undervoltage Turn Off Propagation Delay UV Steps from 1.5V to 1V l 2 5 µs tOFF(OV) Overvoltage Turn Off Propagation Delay FB Steps from 0V to 1.5V; OUT = 0V l 0.25 1 µs tOFF(OC) Overcurrent Turn Off Propagation Delay ∆VSNS Steps from 0V to 150mV; OUT = 0V l 1 2.5 µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive all current out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 10V above the OUT pin. Driving this pin to voltages beyond the clamp may damage the device. 4363fa 4 LT4363 TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. 1000 Supply Current vs Supply Voltage (ICC vs VCC) 8 Specifications are at VCC = 12V, TA = 25°C, unless Supply Current During Shutdown vs Temperature (ICC(SHDN) vs Temperature) 6 OUT = SNS = 0V 7 5 4 400 ICC (µA) 5 600 4 3 2 1 1 0 10 20 30 40 50 VCC (V) 60 70 0 –50 80 SHDN = 0.4V 1.5 1.0 0.5 –25 75 0 25 50 TEMPERATURE (°C) 0 125 100 40 VCC = SNS = OUT = GATE 35 35 30 30 25 25 20 15 5 5 GATE Pull-Down Current vs Temperature: Overcurrent 0 10 20 30 40 50 VCC (V) 60 70 175 14 150 150 12 125 10 100 75 50 SNS = OUT = 5V 25 GATE = 12V FB = 1.5V 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 125 4363 G07 ∆VGATE (V) 175 IGATE(DN,OV) (mA) 16 ∆VSNS = 150mV 25 OUT = 0V GATE = 10V 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 60 70 80 4363 G03 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4363 G06 200 50 40 50 VCC (V) 4363 G05 200 100 30 VCC = SNS = OUT 0 –50 80 GATE Pull-Down Current vs Temperature: Overvoltage 75 20 15 10 4363 G04 100 10 20 10 0 125 125 0 GATE Pull-Up Current vs Temperature IGATE(UP) (µA) IGATE(UP) (µA) ICC(SHDN) (µA) SHDN = 0V 0 –50 100 GATE Pull-Up Current vs VCC 40 2.0 0 25 50 75 TEMPERATURE (°C) 4363 G02 3.0 2.5 –25 4363 G01 SHDN Current vs Temperature IGATE(DN,OC) (mA) 3 2 200 0 OUT = SNS = 0V 6 ICC (µA) ICC (µA) 800 Supply Current During Shutdown vs Supply Voltage (ICC(SHDN) vs VCC) Gate Drive Voltage vs Gate Pull-Down Current ΔVGATE vs IGATE VCC = SNS = OUT 8 6 4 2 100 125 4363 G08 0 0 2 6 4 IGATE (µA) 8 10 4363 G09 4363fa 5 LT4363 TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. TMR High Threshold vs Supply Voltage 5 VCC = SNS = OUT IGATE = 0µA 4 12 11 10 IGATE = 1µA 8 VTMR (V) IGATE = –1µA 12 Gate Drive vs Supply Voltage (ΔVGATE vs VCC) 14 IGATE = 0µA 13 ∆VGATE (V) 16 ∆VGATE (V) 14 Gate Drive at Temperature (ΔVGATE vs Temperature) Specifications are at VCC = 12V, TA = 25°C, unless 6 3 2 4 2 VCC = SNS = OUT 10 –50 75 0 25 50 TEMPERATURE (°C) –25 100 0 125 0 4 8 12 4363 G10 260 TMR = 1V 20 10 Overcurrent TMR Current vs (VCC – VOUT) 2.5 TMR = 1V 10 20 30 40 50 VCC – VOUT (V) 60 70 120 80 0 80 ITMR(UP,COOL) (µA) 2.0 1.6 1.2 0.8 0.4 0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 4363 G16 30 40 50 VCC (V) 60 70 80 4363 G12 Warning Period TMR Current vs VCC ∆VDS = 0.5V 1.5 1.0 0 10 20 30 40 50 VCC – VOUT (V) 60 70 0 80 2.5 5 2.0 4 1.5 2 0.5 1 75 0 25 50 TEMPERATURE (°C) 20 30 100 125 4363 G17 40 50 VCC (V) 60 70 80 4363 G15 OUT = SNS = 3V 3 1.0 –25 10 Output Low Voltage vs Current 6 TMR = 3V 0 –50 0 4363 G14 TMR Pull-Up Current (Cool Down) vs Temperature TMR = 1V 20 0.5 4363 G13 3.0 10 2.0 40 0 0 4363 G11 160 TMR Pull-Down Current vs Temperature ITMR(DN) (µA) 1 80 ITMR(OV,EW) (µA) ITMR(UP,OC) (µA) ITMR(UP,OV) (µA) 30 2.4 70 220 40 0 60 VOL (V) 50 Overvoltage TMR Current vs (VCC – VOUT) 16 20 VCC (V) 0 0 0.5 1.0 1.5 2.0 ISINK (mA) 2.5 3.0 4363 G18 4363fa 6 LT4363 TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. Overcurrent Turn-Off Time vs Temperature 350 1.4 300 1.2 250 1.0 tOFF(OC) (µs) tOFF(OV) (ns) Overvoltage Turn-Off Time vs Temperature 200 150 50 0.2 0 25 50 75 TEMPERATURE (°C) 100 OUT = 3V ∆VSNS = 300mV 0.6 0.4 –25 OUT = 0V ∆VSNS = 150mV 0.8 100 0 –50 Specifications are at VCC = 12V, TA = 25°C, unless 0 –50 125 –25 0 25 50 75 TEMPERATURE (°C) 100 4363 G19 4363 G20 Reverse Current vs Reverse Voltage –7 60 VCC = SHDN –6 OUT = 3V 50 ∆VSNS (mV) IGND (mA) Current Limit at Supply Voltage (ΔVSNS vs VCC) 55 –5 –4 –3 45 40 –2 OUT = 0V 35 –1 0 125 0 –10 –20 –30 –40 –50 –60 –70 –80 VCC (V) 4363 G21 30 0 10 20 30 40 50 VCC (V) 60 70 80 4363 G22 4363fa 7 LT4363 PIN FUNCTIONS ENOUT: Open Collector Enable Output. The ENOUT pin goes high impedance when the voltage at the OUT pin is within 0.5V of VCC and 3V above GND, indicating the external MOSFET is fully on. The state of the pin is latched until the OUT pin voltage drops below 2V, resetting the latch. The internal NPN is capable of sinking up to 2mA of current. Exposed Pad (DFN Package Only): Exposed pad may be left open or connected to device ground (GND). FB: Voltage Regulator Feedback Input. Connect this pin to the center tap of the resistive divider connected between the OUT pin and ground. During an overvoltage condition, the GATE pin is controlled to maintain a 1.275V threshold at the FB pin. Connect to GND to disable the OV clamp. FLT: Open Collector Fault Output. This pin pulls low after the voltage at the TMR pin has reached the fault threshold of 1.275V. It indicates the pass transistor is about to turn off because either the supply voltage has stayed at an elevated level for an extended period of time (voltage fault) or the device is in an overcurrent condition (current fault). The internal NPN is capable of sinking up to 2mA of current. GATE: N-Channel MOSFET Gate Drive Output. The GATE pin is pulled up by an internal charge pump current source and clamped to 14V above the OUT pin. Both voltage and current amplifiers control the GATE pin to regulate the output voltage and limit the current through the MOSFET. GND: Device Ground. OUT: Output Voltage Sense Input. This pin senses the voltage at the source of the external N-channel MOSFET. The voltage difference between VCC and OUT sets the fault timer current. When this difference drops below 0.5V, the EN pin goes high impedance. OV (LT4363-2): Overvoltage Comparator Input. When OV is above its threshold of 1.275V, the fault retry function is inhibited even when the TMR pin voltage has reached its retry threshold. As soon as the voltage at OV pin falls below its lower threshold the GATE pin is allowed to turn back on. Connect to GND if unused. SHDN: Shutdown Control Input. The LT4363 can be shutdown to a low current mode by pulling the SHDN pin below the threshold of 0.4V. Pull this pin above 2.1V or disconnect it to allow the internal current source to turn the part back on. The leakage current to ground at the pin should be limited to no more than 1µA if no external pull up is used to turn the part on. The SHDN pin can be pulled up to 100V or below GND by 60V without damage. SNS: Current Sense Input. Connect this pin to the input of the current sense resistor. The current limit circuit controls the GATE pin to limit the sense voltage between SNS and OUT pins to 50mV. This is reduced to 25mV in a severe fault when OUT is below 2V. When in current limit mode, a current source charges up the TMR pin. The voltage difference with the OUT pin must be limited to less than 30V. Connect to OUT pin if unused. TMR: Fault Timer Input. Connect a capacitor between this pin and ground to set the times for early fault warning, fault turn-off, and cool down periods. The current charging up this pin during fault conditions depends on the voltage difference between the VCC and OUT pins. When TMR reaches 1.275V, the FLT pin pulls low to indicate the detection of a fault condition. If the condition persists, the pass transistor turns off when TMR reaches the threshold of 1.375V. A 2µA current source then continues to pull the TMR up. When TMR reaches 4.3V, the 2µA current reverses direction and starts to pull the TMR pin low. When TMR reaches the retry threshold of 0.5V, the GATE pin pulls high turning back on the pass transistor for the LT4363-2 version. The GATE pin latches low after fault time out for the LT4363-1. UV: Undervoltage Comparator Input. When UV falls below its threshold of 1.275V, the GATE is pulled down with a 1mA current. When UV rises above 1.275V plus the hysteresis, the pull down current disappears and the GATE pin is pulled up by the internal charge pump. If unused, connect to VCC. VCC: Positive Supply Voltage Input. The positive supply input ranges from 4V to 80V for normal operation. It can also be pulled below ground by up to 60V during a reverse battery condition, without damaging the part. Shutting down the LT4363 by pulling the SHDN pin to ground will reduce the supply current to 7µA. 4363fa 8 LT4363 BLOCK DIAGRAM VCC GATE SNS 13V OUT CHARGE PUMP + – FB + + VA – – 50mV/ 25mV IA SHDN UV 1.275V FLT SHDN – ENOUT UV + CONTROL LOGIC 1.275V + RETRY – GATEOFF OV (LT4363-2 ONLY) 1.375V FLT – 0.5V ITMR – + VCC + + 2µA 1.275V – + 4.3V TMR – GND 4363 BD 4363fa 9 LT4363 OPERATION Some power systems must cope with high voltage surges of short duration such as those in vehicles. Load circuitry must be protected from these transients, yet high availability systems must continue operating during these events. sufficient time for TMR to discharge to 0.5V and for the MOSFET to cool before attempting to reset the part. To reset, pull the SHDN pin low for at least 100µs, then pull high with a slew rate of at least 10V/ms. The LT4363 is an overvoltage protection regulator that drives an external N-channel MOSFET as the pass transistor. It operates from a wide supply voltage range of 4V to 80V. It can also be pulled below ground potential by up to 60V without damage. The low power supply requirement of 4V allows it to operate even during cold cranking conditions in automotive applications. The internal charge pump turns on the N-channel MOSFET to supply current to the loads with very little power loss. Two MOSFETs can be connected back to back to replace an inline Schottky diode for reverse input protection. This improves the efficiency and increases the available supply voltage level to the load circuitry during cold crank. The fault timer allows the load to continue functioning during short transient events while protecting the MOSFET from being damaged by a long period of supply overvoltage, such as a load dump in vehicles. The timer period varies with the voltage across the MOSFET. A higher voltage corresponds to a shorter fault timer period, helping to keep the MOSFET within its safe operating area (SOA). Normally, the pass transistor is fully on, powering the loads with very little voltage drop. When the supply voltage surges too high, the voltage amplifier (VA) controls the gate of the MOSFET and regulates the voltage at the OUT pin to a level that is set by the external resistive divider from the OUT pin to ground and the internal 1.275V reference. A current source starts charging up the capacitor connected at the TMR pin to ground. If the TMR voltage reaches 1.275V, the FLT pin pulls low to indicate impending turn-off due to the overvoltage condition. The pass transistor stays on until TMR reaches 1.375V, at which point the GATE pin pulls low turning off the MOSFET. The LT4363 senses an overcurrent condition by monitoring the voltage across an optional sense resistor placed between the SNS and OUT pins. An active current limit circuit (IA) controls the GATE pin to limit the sense voltage to 50mV, if the OUT pin potential is above 2V. In the case of a severe output short that brings OUT below 2V, the servo sense voltage is reduced to 25mV to reduce the stress on the pass transistor. During current limit, the current charging the TMR capacitor is about 5 times the current during an overvoltage event. The FLT pin pulls low when the TMR voltage reaches 1.275V and the MOSFET is turned off when it reaches 1.375V. The MOSFET turns back on and the FLT pin returns to a high impedance state after TMR has reached the 0.5V threshold for the LT4363‑2 version. For the latch-off version, LT4363-1, both the GATE and FLT pins remain low even after TMR has reached the 0.5V threshold. Reset the part in the same way as in overvoltage time-out case. A current continues to pull the TMR pin up until it reaches about 4.3V, at which point the current reverses direction and pulls the TMR pin down. For the LT4363-2 version, when the voltage at the TMR pin reaches 0.5V the GATE pin begins rising, turning on the MOSFET. The FLT pin will then return to a high impedance state. For the latch-off version, LT4363-1, both the GATE and FLT pins remain low even after TMR has reached the 0.5V threshold. Allow An accurate undervoltage comparator keeps the GATE pin low until the voltage at the UV pin is above the 1.275V threshold. An overvoltage comparator prevents the MOSFET from turning on after fault time-out while the voltage at the OV pin is still above 1.275V for the LT4363‑2. The SHDN pin turns off the pass transistor and all the internal circuitry, reducing the supply current to a mere 7µA. 4363fa 10 LT4363 APPLICATIONS INFORMATION The LT4363 limits the voltage and current delivered to the load during supply transient or output overload events. The total fault timer period is set to ride through short-duration faults, while longer events cause the output to shut off and protect the MOSFET pass device from damage. The MOSFET provides a low resistance path from the input to the load during normal operation, while in fault conditions it operates as a series regulator. Overvoltage Fault The LT4363 limits the voltage at the output during an overvoltage at the input. An internal amplifier regulates the GATE pin to maintain 1.275V at the FB pin. During this interval the MOSFET is on and supplies current to the load. This allows uninterrupted operation during short overvoltage events. If the overvoltage condition persists, the timer causes the MOSFET to turn off. Overcurrent Fault The LT4363 features and adjustable current limit that protects against output short circuits or excessive load current. During an overcurrent event, the GATE pin is regulated to limit the current sense voltage across the SNS and OUT pins to 50mV. In the case of a severe short at the output, where OUT is less than 2V, the current sense voltage is reduced to 25mV to further reduce power dissipation in the MOSFET. If the overcurrent condition persists, the timer causes the MOSFET to turn off. Fault Timer Overview Overvoltage and overcurrent conditions are limited in duration by an adjustable timer. A capacitor at the TMR pin sets the delay time before a fault condition is reported at the FLT pin as well as the overall delay before the MOSFET is turned off. The same capacitor also sets the cool down time before the MOSFET is allowed to turn back on. When either an overvoltage or overcurrent fault condition occurs, a current source charges the TMR pin capacitor. The exact current level varies as a function of the type of fault and the VDS voltage drop across the MOSFET. This scheme takes better advantage of the MOSFET’s available Safe Operating Area (SOA) than would a fixed timer current. The TMR pin is biased to 0.5V under normal operating conditions. In the presence of a fault the timer first charges to 1.275V, and then enters the early warning phase of operation. At this point the FLT pin pulls low and after charging to 1.375V, the timer shuts off the MOSFET. The warning phase is indicated by FLT low and gives time for the load to perform house-keeping chores such as data storage in anticipation of impending power loss. After faulting off, the timer enters the cool down phase. At the end of the cool down period the LT4363-1 remains off until reset, while the LT4363-2 automatically restarts. For the LT4363-2 retry is inhibited if the OV pin is greater than 1.275V. This prevents motorboating in the event there is a sustained input overvoltage condition. Fault Timer Operation in Overvoltage In the presence of an overvoltage condition when the LT4363 regulates the output voltage, the timer charges from 0.5V to 1.275V with a current that varies as a function of VDS (see Figure 1). VDS is inferred from the drop across VCC and OUT. The timer current increases linearly from around 4µA with VDS ≤ 0.5V, to 50µA with VDS = 75V. Because VDS is measured indirectly, clamping or filtering at the VCC pin affects the timer current response. A graph of Overvoltage TMR Current vs (VCC – VOUT) is shown in the Typical Performance Characteristics. When TMR reaches 1.275V, the FLT pin is latched low as an early warning of impending shutdown. The timer current is cut to a fixed value of 6µA and continues to run until TMR reaches 1.375V, producing a fixed early warning period given by: CTMR = t WARNING • 6µA 100mV When TMR reaches 1.375V, the MOSFET is turned off and allowed to cool for an extended period. The total elapsed time between the onset of output regulation and turn-off is given by: 0.775V 100mV tREG = CTMR • + I 6µA TMR Because ITMR is a function of VCC – VOUT, the exact time in regulation depends upon the input waveform and the time required for the output voltage to come into regulation. 4363fa 11 LT4363 APPLICATIONS INFORMATION Fault Timer Operation in Overcurrent TMR pin behavior in overcurrent is substantially the same as in overvoltage. In the presence of an overcurrent condition when the LT4363 regulates the output current, the timer charges from 0.5V to 1.275V with a current that varies as a function of VDS (see Figure 2). The current is about 5 times the value produced in overvoltage, under similar conditions VDS, increasing linearly from 8µA with VDS < 0.5V to 260µA with VDS = 80V. VDS is inferred from the drop across VCC and OUT. Because VDS is measured indirectly, clamping or filtering at the VCC pin affects the timer current response. A graph of Overcurrent TMR Current vs (VCC – VOUT) is shown in the Typical Performance Characteristics. VTMR(V) ITMR = 6µA ITMR = 6µA 1.375 1.275 VDS = 75V (ITMR = 50µA) 0.50 TIME tWARNING = 16.67ms/µF tFLT = 96.9ms/µF tWARNING = 16.67ms/µF TOTAL FAULT TIMER = tFLT + tWARNING CTMR = t WARNING • ITMR 100mV When TMR reaches 1.375V, the MOSFET is turned off and allowed to cool for an extended period. The total elapsed time between the onset of current limiting and turn-off is given by: tLIM = CTMR • 0.875V ITMR Because ITMR is a function of VCC – VOUT, the exact time in current limit depends upon the input waveform and the time required for the output current to come into regulation. Cool Down Phase VDS = 10V (ITMR = 8µA) tFLT = 15.5ms/µF When TMR reaches 1.275V, the FLT pin is latched low as an early warning of impending shutdown. But unlike the overvoltage case, the timer current is not reduced and instead continues unabated until TMR reaches 1.375V, producing an early warning period given by: Cool Down behavior is the same whether initiated by overvoltage or overcurrent. During the cool down phase, the timer continues to charge from 1.375V to 4.3V with 2µA, and then discharges back down to 0.5V with 2µA, for a total equivalent voltage swing of 6.725V. The cool down time is given by: 4363 F01 Figure 1. Overvoltage Fault Timer Current VTMR(V) tCOOL = CTMR • 2.925V + 3.8V 2µA Up to this point the operation of the LT4363-1 and LT4363-2 is the same. Behavior at the end of the cool down phase and in response to the SHDN pin is entirely different. 1.375 1.275 VDS = 80V (ITMR = 260µA) 0.50 tFLT = 2.98ms/µF VDS = 10V (ITMR = 35µA) TIME tWARNING = 0.38ms/µF tFLT = 22.14ms/µF TOTAL FAULT TIMER = tFLT + tWARNING tWARNING = 2.86ms/µF Figure 2. Overcurrent Fault Timer Current 4363 F02 At the end of the cool down phase the LT4363-1 remains latched off and FLT remains low. It may be restarted by pulling the SHDN pin low for at least 100µs or by cycling power. The cool down phase may be interrupted at anytime by pulling SHDN low for at least 1s/µF of CTMR; the LT4363-1 will restart when SHDN goes high. The LT4363-2 will automatically retry at the end of the cool down phase. Retry is inhibited if the OV pin is above 1.275V; this prevents repetitive retries while the input is held in a sustained overvoltage condition. Retry is auto4363fa 12 LT4363 APPLICATIONS INFORMATION matically initiated once the OV pin falls below 1.268V. OV has no effect on initial start-up when power is first applied and upon exiting shutdown. The cool down phase may be interrupted in the LT4363-2 by pulling SHDN low for at least 1s/µF of CTMR. For both the LT4363-1 and LT4363-2 the FLT pin goes high in shutdown and is cleared high when power is first applied to VCC. If FLT is set low, it can be reset during the cool down phase by pulling SHDN low for at least 1s/µF of CTMR. Intermittent Fault Conditions Brief overvoltage or overcurrent conditions interrupt the operation of the timer. If the TMR pin has not yet reached 1.275V when the input falls below the regulation value or drops out of current limit, the timer capacitor is discharged back to 0.5V with a 2µA current sink. If the TMR voltage crosses 1.275V FLT is set low. If the overvoltage or overcurrent abates before reaching 1.375V, the timer capacitor discharges with 2µA back to 0.5V, whereupon FLT resets high. If several short overvoltage or overcurrent events occur in rapid succession, the timer capacitor will integrate the charging and discharging currents. MOSFET Selection The LT4363 drives an N-channel MOSFET to conduct the load current. The important features of the MOSFET are on-resistance RDS(ON), the maximum drain-source voltage V(BR)DSS, the threshold voltage, and the SOA. The maximum allowable drain-source voltage must be higher than the supply voltage. If the output is shorted to ground or during an overvoltage event, the full supply voltage will appear across the MOSFET. The gate drive for the MOSFET is guaranteed to be more than 10V and less than 16V for those applications with VCC higher than 9V. This allows the use of standard threshold voltage N-channel MOSFETs. For systems with VCC less than 9V, a logic level MOSFET is required since the gate drive can be as low as 4.5V. The SOA of the MOSFET must encompass all fault conditions. In normal operation the pass transistor is fully on, dissipating very little power. But during either overvoltage or overcurrent faults, the GATE pin is controlled to regulate either the output voltage or the current through the MOSFET. Large current and high voltage drop across the MOSFET can coexist in these cases. The SOA curves of the MOSFET must be considered carefully along with the selection of the fault timer capacitor. Transient Stress in the MOSFET During an overvoltage event, the LT4363 drives a series pass MOSFET to regulate the output voltage at an acceptable level. The load circuitry may continue operating throughout this interval, but only at the expense of dissipation in the MOSFET pass device. MOSFET dissipation or stress is a function of the input voltage waveform, regulation voltage and load current. The MOSFET must be sized to survive this stress. Most transient event specifications use the prototypical waveshape shown in Figure 3, comprising a linear ramp of rise time tr, reaching a peak voltage of VPK and exponentially decaying back to VIN with a time constant of τ. A common automotive transient specification has constants of tr = 10µs, VPK = 80V and τ = 1ms. A surge condition known as load dump commonly has constants of tr = 5ms, VPK = 60V and τ = 200ms. MOSFET stress is the result of power dissipated within the device. For long duration surges of 100ms or more, stress is increasingly dominated by heat transfer; this is a matter of device packaging and mounting, and heat sink thermal mass. This is best analyzed by simulation, using the MOSFET thermal model. For short duration transients of less than 100ms, MOSFET survival is increasingly a matter of safe operating area VPK τ VIN tr 4363 F03 Figure 3. Prototypical Transient Waveform 4363fa 13 LT4363 APPLICATIONS INFORMATION (SOA), an intrinsic property of the MOSFET. SOA quantifies the time required at any given condition of VDS and ID to raise the junction temperature of the MOSFET to its rated maximum. MOSFET SOA is expressed in units of watt-squared-seconds (P2t). This figure is essentially constant for intervals of less than 100ms for any given device type, and rises to infinity under DC operating conditions. Destruction mechanisms other than bulk die temperature distort the lines of an accurately drawn SOA graph so that P2t is not the same for all combinations of ID and VDS. In particular P2t tends to degrade as VDS approaches the maximum rating, rendering some devices useless for absorbing energy above a certain voltage. When a fast input voltage step occurs, the current through the pass transistor to supply the load and charge up the output capacitor can be high enough to trigger an overcurrent event. The gate pulls low to 1V above the OUT pin, turning off the MOSFET momentarily. The internal charge pump will then start to pull the GATE pin high and turn on the MOSFET to support the load current and charge up the OUT pin. The fault timer may not start yet because the current level is below the overcurrent limit threshold and the output voltage has not reached the servo voltage. This extra stress needs to be included in calculating the overall stress level of the MOSFET. a = VREG – VIN b = VPK – VIN (VIN = Nominal Input Voltage) Then P 2 t = ILOAD2 • 1 ( b – a )3 1 2 b + τ 2a ln + 3a 2 +b2 − 4ab tr b 2 a 3 Typically VREG ≈ VIN and τ » tr simplifying the above to 1 2 P 2 t = ILOAD2 ( VPK – VREG ) τ 2 [W 2s] For the transient conditions of VPK = 80V, VIN = 12V, VREG = 16V, tr = 10µs and τ = 1ms, and a load current of 3A, P2t is 18.4W2s – easily handled by a MOSFET in a DPAK package. The P2t of other transient waveshapes is evaluated by integrating the square of MOSFET power over time. LTSpice can be used to simulate timer behavior for more complex transients and cases where overvoltage and overcurrent faults coexist. Calculating Short-Circuit Stress Calculating Transient Stress To select a MOSFET suitable for any given application, the SOA stress must be calculated for each input transient which shall not interrupt operation. It is then a simple matter to choose a device which has adequate SOA to survive the maximum calculated stress. P2t for a prototypical transient waveform is calculated as follows (Figure 4): VPK SOA stress must also be calculated for short-circuit conditions. Short-circuit P2t is given by: 2 ΔV P t = ΔVDS • SNS • t TMR [W 2s] R 2 SNS Where ΔVDS is the voltage across the MOSFET, and ΔVSNS is the SNS pin threshold, and tTMR is the overcurrent timer interval. For VIN = 15V, ΔVDS = 13V (VOUT = 2V), ΔVSNS = 50mV, RSNS = 12mΩ and CTMR = 100nF, P2t is 6.3W2s – less than the transient SOA calculated in the previous example. Nevertheless, to account for circuit tolerances this figure should be doubled to 12.6W2s. τ VREG VIN Let tr 4363 F04 Figure 4. Safe Operating Area Required to Survive Prototypical Transient Waveform 4363fa 14 LT4363 APPLICATIONS INFORMATION Limiting Inrush Current and GATE Pin Compensation The LT4363 limits the inrush current to any load capacitance by controlling the GATE pin voltage slew rate. An external capacitor can be connected from GATE to ground to reduce the inrush current at the expense of slower turn-off time. The gate capacitor is set at: C1= IGATE(UP) IINRUSH • CL threshold during a fault. The pass transistor is not allowed to turn back on even after the cool down period has finished. This prevents the pass transistor from cycling between ON and OFF states when the input voltage stays at an elevated level for a long period of time, reducing the stress on the N-channel MOSFET. For the latch-off version, LT4363-1, the overvoltage comparator function is not available. Reverse Input Protection The LT4363 does not need extra compensation components at the GATE pin for stability during an overvoltage or overcurrent event. With transient input voltage slew rates faster than 5V/µs, a gate capacitor, C1, to ground is needed to prevent self enhancement of the N-channel MOSFET. A blocking diode is commonly employed to protect the load when reverse input is possible, such as in automotive applications. This diode causes extra power loss, generates heat, and reduces the available supply voltage range. During cold crank, the extra voltage drop across the diode is particularly undesirable. The extra gate capacitance slows down the turn off time during fault conditions and may allow excessive current during an output short event. An extra resistor, R1, in series with the gate capacitor can improve the turn off time. A diode, D1, should be placed across R1 with the cathode connected to C1 as shown in Figure 5. The LT4363 is designed to withstand reverse voltage without damage to itself. The VCC, SHDN, UV, and OV pins can withstand up to 60V of DC voltage below the GND potential. Back-to-back MOSFETs must be used to block the current path through Q1’s body diode (Figure 6). Figure 7 shows the approach with a P-channel MOSFET in place of Q2. Q1 Q2 IRLR2908 VIN 12V D1 IN4148W D1* SMAJ58CA R3 Q3 2N3904 R1 RSNS 10mΩ Q1 IRLR2908 R4 R5 10Ω 1M VOUT 12V, 3A CLAMPED AT 16V R3 10Ω R1 57.6k C1 GATE D2 1N4148 R7 10k C1 47nF LT4363 4363 F05 5 Figure 5. External GATE network VCC The overvoltage comparator prevents the LT4363-2 from restarting if the voltage at the OV pin is above the 1.275V 2 OUT FB 1 R2 4.99k Undervoltage/Overvoltage Comparators The LT4363 has both undervoltage and overvoltage comparators that can be used to sense the input supply voltage. When the voltage at the UV pin is below the 1.275V threshold, the GATE pin is held low to keep the external MOSFET off. The supply voltage at the VCC pin should be at least 4V for the UV comparator to function. 3 SNS 4 GATE LT4363DE-2 6 8 7 SHDN ENOUT UV OV GND 9 *DIODES INC. FLT TMR 12 11 10 4363 F06 CTMR 0.1µF Figure 6. Overvoltage Regulator with N-channel MOSFET Reverse Input Protection 4363fa 15 LT4363 APPLICATIONS INFORMATION VIN 12V Q2 SI7461DP D1* SMAJ58CA R7 10k 5 RSNS 10mΩ Q1 IRLR2908 D2 1N5245 15V C1 47nF VOUT 12V, 3A CLAMPED AT 16V R3 10Ω 4 GATE VCC 2 OUT FB 1 LT4363DE-2 8 7 SHDN ENOUT OV GND 9 *DIODES INC. FLT TMR 12 11 10 4363 F07 CTMR 0.1µF Figure 7. Overvoltage Regulator with P-channel MOSFET Reverse Input Protection Shutdown The LT4363 can be shut down to a low current mode when the voltage at the SHDN pin is pulled below the shutdown threshold of 0.4V. The quiescent current drops down to 7µA with internal circuitry turned off. The SHDN pin can be pulled up to 100V or below GND by up to 60V without damage. Leaving the pin open allows an internal current source to pull it up and turn on the part while clamping the pin to 2.2V. The leakage current at the pin should be limited to no more than 1µA if no pull up device is used to help turn it on. Supply Transient Protection The LT4363 is tested to operate to 80V and guaranteed to be safe from damage up to 100V. Nevertheless, voltage transients above 100V may cause permanent damage. During a short-circuit condition, the large change in current flowing through power supply traces and associated wiring can cause inductive voltage transients which could exceed 100V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wide traces. A small RC filter, in Figure 8, at the VCC pin will clamp the voltage spikes. RSNS 10mΩ VOUT CL** 22µF R3 10Ω 3 4 VCC GATE SNS R1 100k 2 OUT 5 FB 1 R2 4.99k D1* SMAJ58A 6 R4 374k UV C1 47nF R7 1k C2 0.1µF R2 4.99k 6 VIN R1 57.6k 3 SNS Q1 FDB33N25 R5 90.9k R6 10k 8 SHDN VCC LT4363DE-2 DC/DC CONVERTER UV ENOUT 7 OV GND 9 TMR 12 FLT 11 10 SHDN FAULT 4363 F08 CTMR 47nF GND *DIODES INC. **SANYO 25CE22GA Figure 8. Overvoltage Regulator with Input Voltage Detection Another way to limit transients above 100V at the VCC pin is to use a Zener diode and a resistor, D1 and R7 in Figure 8. The Zener diode limits the voltage at the pin while the resistor limits the current through the diode to a safe level during the surge. However, D1 can be omitted if the filtered voltage, due to R7 and C1, at the VCC pin is below 100V. The inclusion of R7 in series with the VCC pin will increase the minimum required voltage at VIN due to the extra voltage drop across it. This voltage drop is due to the supply current of the LT4363 and the leakage current of D1. A total bulk capacitance of at least 22µF low ESR electrolytic is required close to the source pin of MOSFET Q1. In addition, the bulk capacitance should be at least 10 times larger than the total ceramic bypassing capacitor on the input of the DC/DC converter. Layout Considerations To achieve accurate current sensing, Kelvin connection to the current sense resistor (RSNS in Figure 8) is recommended. The minimum trace width for 1 oz copper foil is 0.02" per amp to ensure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/square. Small resistances can cause large errors in 4363fa 16 LT4363 APPLICATIONS INFORMATION high current applications. Noise immunity will be improved significantly by locating resistive dividers close to the pins with short VCC and GND traces. Design Example As a design example, take an application with the following specifications: VCC = 8V to 14V DC with a transient of 150V and decay time constant (τ) of 400ms, VOUT ≤ 27V, current limit (ILIM) at 5A, low battery detection of 6V, input overvoltage level at 60V, and 1ms of overvoltage early warning (Figure 8). Selection of SMAJ58A for D1 will limit the voltage at the VCC pin to less than 71V during 150V surge. The minimum required voltage at the VCC pin is 4V when VIN is at 8V; the supply current for LT4363 is 1.5mA. The maximum value for R7 to ensure proper operation is: R7 = 8V – 4V = 2.67kΩ 1.5mA Select 1kΩ for R7 to accommodate all conditions. The maximum current through R7 into D1 is then calculated as: ID1 = 150V – 64V = 86mA 1kΩ which is easily handled by the SMAJ58A for more than 500ms. Choose 4.99kΩ for R2. R1= (27V – 1.275V ) • R2 = 100.7kΩ 1.275V The nearest standard value for R1 is 100kΩ. Next calculate the sense resistor, RSNS, value: RSNS = 50mV 50mV = = 10mΩ ILIM 5A CTMR is then chosen for 1ms of early warning time: CTMR = 1ms • 6µA = 60nF 100mV The nearest standard value for CTMR is 47nF. Finally, calculate R4, R5, and R6 for 6V low battery detection and 60V input overvoltage level: 6V • R5 + R6 = 1.275V R4 + R5 + R6 60V • R6 = 1.275V R4 + R5 + R6 Choose 10kΩ for R6. R4 + R5 = 60V • 10kΩ – 10kΩ = 460.6kΩ 1.275V 460.6kΩ + 10kΩ – 10kΩ = 90kΩ 6V With 0.1µF of bypass capacitance, C1, along with 1k of R7, high voltage transients up to 200V with a pulse width less than 10µs are filtered out at the VCC pin. Next, calculate the resistive divider value to limit VOUT to 27V during an overvoltage event: Select 90.9kΩ for R5 and 374kΩ for R4. 1.275V • (R1+ R2) VREG = = 27V R2 Set the current through R1 and R2 during the overvoltage condition to 250µA. 1.275V R2 = = 5kΩ 250µA R5 = 1.275V • R4 = 460.6kΩ – 90kΩ = 370.6kΩ The pass transistor, Q1, should be chosen to withstand a short-circuit with VCC = 14V. In the case of a severe output short where VOUT = 0V, the total overcurrent fault time is: tOC = 47nF • 0.875V = 0.904ms 45.5µA 4363fa 17 LT4363 APPLICATIONS INFORMATION The power dissipation in Q1 is: P= The power dissipation in Q1 is: 14V • 25mV = 35W 10mΩ During an output overload or soft short, the voltage at the OUT pin could stay at 2V or higher. The total overcurrent fault time when VOUT = 2V is: tOC = P= (14V – 2V ) • 50mV = 60W 10mΩ These conditions are well within the Safe Operating Area of the FDB33N25. 47nF • 0.875V = 1.028ms 40µA TYPICAL APPLICATIONS Overvoltage Regulator with Output Keep Alive During Shutdown VIN R7 1k D1* SMAJ58A R9 1k, 1W RSNS 10mΩ Q1 IRLR2908 CL** 22µF R3 10Ω C1 47nF 5 VCC 3 4 GATE SNS 2 OUT FB R1 287k VOUT 12V, 4A REGULATED AT 16V D2 1N4746A 18V 1W 1 R2 24.9k 6 R4 147k R5 30.1k R6 10k 8 SHDN LT4363DE-2 UV ENOUT 7 OV GND 9 FLT TMR 12 4363 TA02 CTMR 0.1µF 11 10 UV = 6V OV = 24V *DIODES INC. **SANYO 25CE22GA 4363fa 18 LT4363 TYPICAL APPLICATIONS 2.5A, 48V Hot Swap with Overvoltage Output Regulation at 72V VIN RSNS 15mΩ Q1 FDB3632 R7 1k VOUT 48V, 2.5A CL 300µF R3 10Ω C1 47nF 5 D1* SMAT70A 3 4 GATE SNS VCC 2 OUT FB R1 221k 1 R2 4.02k 6 R4 604k R5 13k 8 SHDN LT4363DE-2 UV ENOUT 7 OV GND R6 10k FLT TMR 9 12 11 10 UV = 35V OV = 80V 4363 TA03 CTMR 0.1µF *DIODES INC. 2.5A, 28V Hot Swap with Overvoltage Output Regulation at 36V VIN 28V Q1 IRLR2908 R7 1k RSNS 15mΩ VOUT 28V, 2.5A CL 300µF R3 10Ω C1 47nF 5 D1* SMAJ58A VCC 3 4 GATE SNS 2 OUT FB R1 110k 1 R2 4.02k 6 R4 261k R5 10k R6 10k 8 SHDN LT4363DE-2 UV ENOUT 7 OV GND 9 TMR 12 FLT 4363 TA04 CTMR 0.1µF 11 10 UV = 18V OV = 36V *DIODES INC. 4363fa 19 LT4363 TYPICAL APPLICATIONS Overvoltage Regulator with Reverse Input Protection Up to –80V Q2 IRLR2908 VIN 12V Q3 2N3904 R5 1M R1 57.6k C1 47nF 3 4 GATE SNS 5 VCC D1* SMAJ58CA D3** 1N4148 VOUT 12V, 3A CL** CLAMPED 22µF AT 16V R3 10Ω R4 10Ω D2 1N4148 R7 10k RSNS 10mΩ Q1 IRLR2908 2 OUT FB 1 R2 4.99k 6 8 7 LT4363DE-2 SHDN UV ENOUT OV GND *DIODES INC. **SANYO 25CE22GA ***OPTIONAL COMPONENT FOR REDUCED STANDBY CURRENT FLT TMR 9 12 11 10 4363 TA05 CTMR 0.1µF Overvoltage Regulator with 250V Surge Protection VIN 12V Q1 FDB33N25 R6 49.9k Q2 MPS-A42 D1* SMAJ58A C1 0.1µF RSNS 10mΩ CL 22µF R3 10Ω R1 57.6k C1 47nF 5 VCC R4 127k 6 8 4 3 GATE SNS FB R2 4.99k ENOUT 7 1 LT4363DE-2 R5 49.9k OV GND 9 *DIODES INC. 2 OUT SHDN UV OUTPUT CLAMP AT 16V FLT TMR 12 11 10 VCC DC/DC CONVERTER SHDN GND FAULT 4363 TA07 0.1µF 4363fa 20 LT4363 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695 Rev D) 0.70 ±0.05 3.60 ±0.05 2.20 ±0.05 3.30 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) 7 R = 0.115 TYP 0.40 ± 0.10 12 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) 0.200 REF 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ± 0.10 0.75 ±0.05 6 0.25 ± 0.05 1 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER (UE12/DE12) DFN 0806 REV D 0.50 BSC 2.50 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4363fa 21 LT4363 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 12 11 10 9 8 7 0.889 ± 0.127 (.035 ± .005) 0.254 (.010) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.406 ± 0.076 (.016 ± .003) REF GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ± .0015) TYP 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1 2 3 4 5 6 1.10 (.043) MAX 0.86 (.034) REF 0.1016 ± 0.0508 (.004 ± .002) 0.650 (.0256) BSC MSOP (MS12) 1107 REV Ø S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .386 – .394 (9.804 – 10.008) NOTE 3 .045 ±.005 .050 BSC 16 N .245 MIN 13 12 11 10 9 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 1 2 3 4 5 .053 – .069 (1.346 – 1.752) NOTE: 1. DIMENSIONS IN .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 6 7 8 .004 – .010 (0.101 – 0.254) 0° – 8° TYP .016 – .050 (0.406 – 1.270) 22 14 N .160 ±.005 1 .030 ±.005 TYP 15 .050 (1.270) BSC S16 0502 4363fa LT4363 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 03/12 Add 57.6k resistor to Typical Application 24 4363fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT4363 TYPICAL APPLICATION Overvoltage Regulator with Ideal Diode Reverse Voltage Protection M1 FDB3632 VIN 12V IRLR2908 10mΩ OUTPUT CLAMP AT 16V 22µF 10Ω IN GATE OUT LTC4357 47nF VDD DCLAMP SMAT70A GND D1 MMBD1205 VCC GATE SNS FB 4.99k SHDN LT4363 127k –60V TO 75V DC PROTECTION 100V TRANSIENT MAXIMUM UV = 4.5V 57.6k OUT DC/DC CONVERTER UV ENOUT 49.9k GND VCC SHDN FLT TMR FAULT GND 4363 TA06 0.1µF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1696 Overvoltage Protection Controller ThinSOT™ Package, 2.7V to 28V LTC2909 Triple/Dual Inputs UV/OV Negative Monitor Pin Selectable Input Polarity Allows Negative and OV Monitoring LTC2912/LTC2913 Single/Dual UV/OV Voltage Monitor Ads UV and OV Trip Values, ±1.5% Threshold Accuracy LTC2914 Quad UV/OV Monitor For Positive and Negative Supplies LTC3827/LTC3827-1 Low IQ, Dual, Synchronous Controller LTC3835/LTC3835-1 Low IQ, Synchronous Step-Down Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 80µA Quiescent Current Single Channel LTC3827/LTC3827-1 LT3845 Low IQ, Synchronous Step-Down Controller 4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, 120µA Quiescent Current LT3850 Dual, 550kHz, 2-Phase Sychronous Step-Down Controller Dual 180° Phased Controllers, VIN 4V to 24V, 97% Duty Cycle, 4mm × 4mm QFN-28, SSOP-28 Packages LTC3890 Low IQ, Dual 2-Phase, Synchronous Step-Down Controller 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, 50µA Quiescent Current LT4256 Positive 48V Hot Swap Controller with Open-Circuit Detect Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to 80V Supply LTC4260 Positive High Voltage Hot Swap Controller with 8-Bit ADC and I2C Wide Operating Range 8.5V to 80V LT4352 Ideal MOSFET ORing Diode External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V LTC4354 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation LTC4355 Positive Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 0.5µs Turn-Off, 80V Operation LT4356 High Voltage Surge Stopper 100V Overvoltage and Overcurrent Protection, Latch-Off and Auto-Retry Options LTC4365 Window Passer - OV, UV and Reverse Supply Protection Controller 2.5V to 34V Operation, Protects 60V to –40V 4363fa 24 Linear Technology Corporation LT 0312 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2011