LINER LTC4252-2

LTC4253/LTC4253A
–48V Hot Swap Controllers
with Sequencer
NOT RECOMMENDED FOR NEW DESIGNS
Please See LTC4253B for Drop-In Replacement
FEATURES
DESCRIPTION
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The LTC®4253/LTC4253A negative voltage Hot Swap™
controllers allow a board to be safely inserted and removed
from a live backplane. Output current is controlled by three
stages of current-limiting: a timed circuit breaker, active
current limiting and a fast feedforward path that limits
peak current under worst-case catastrophic fault conditions. The LTC4253/LTC4253A latch off after a circuit fault.
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Allows Safe Board Insertion and Removal from a
Live –48V Backplane
Floating Topology Permits Very High Voltage
Operation
Adjustable Analog Current Limit with Breaker Timer
Ideal for Two Battery Feeds
Fast Response Time Limits Peak Fault Current
Adjustable Undervoltage/Overvoltage Protection
with ±1% Threshold Accuracy (LTC4253A)
Three Sequenced Power Good Outputs
Adjustable Soft-Start Current Limit
Adjustable Timer with Drain Voltage Accelerated
Response
Latchoff After Fault
Available in a 16-Pin SSOP Package
Adjustable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the
desired operating range. The LTC4253/LTC4253A’s supply
input is shunt-regulated, allowing safe operation with very
high supply voltages. A multifunction timer delays initial
start-up and controls the circuit breaker’s response time.
The circuit breaker’s response time can be accelerated
by sensing excessive MOSFET drain voltage, keeping the
MOSFET within its safe operating area (SOA). An adjustable
soft-start circuit controls MOSFET inrush current at start-up.
APPLICATIONS
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–48V Distributed Power Systems
Negative Power Supply Control
Central Office Switching
High Availability Servers
Disk Arrays
Three power good outputs are sequenced by an adjustable
timer and two ENABLE inputs to enable external power
modules at start-up or disable them if the circuit breaker
trips. The LTC4253A features tight ±1% undervoltage/
overvoltage threshold accuracy. The LTC4253/LTC4253A
are available in a 16-pin SSOP.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners.
TYPICAL APPLICATION
– 48V/2.5A Hot Swap Controller
– 48V RTN
2.5k
15k(1/4W)/6
1μF
Start-Up Behavior
+
VIN
100μF
– 48V RTN
402k
1%
5.6k
10nF
DIN††
DDZ13B*
5.6k
LOAD1
LOAD2
5.6k
EN2 EN3 VIN
LTC4253
RESET
LOAD3
EN
EN
EN
†
UV
68nF
0.1μF
– 48V A
B3100*
SS
– 48V B
4253 TA01
SS
1V
SENSE
50mV
PWRGD3
DRAIN
SQTIMER
TIMER
1M
IRF530S
SENSE
VEE
B3100*
†
PWRGD2
GATE
0.33μF
†
PWRGD1
OV
32.4k
1%
GATE
10V
10Ω
18nF
0.02Ω
*DIODES, INC.
†MOC207
††RECOMMENDED FOR HARSH ENVIRONMENTS.
VOUT
50V
1ms/DIV
4253 TA01b
425353afe
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LTC4253/LTC4253A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1), All voltages referred to VEE
TOP VIEW
Current into VIN (100μs Pulse) .............................100mA
Current into DRAIN (100μs Pulse) .........................20mA
VIN, DRAIN Minimum Voltage ................................–0.3V
Input/Output (Except SENSE
and DRAIN) Voltage ................................... –0.3V to 16V
SENSE Voltage ........................................... –0.6V to 16V
Current Out of SENSE (20μs Pulse) .................. –200mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4253C ................................................ 0°C to 70°C
LTC4253I .............................................–40°C to 85°C
LTC4253AC (OBSOLETE)......................... 0°C to 70°C
LTC4253AI (OBSOLETE)......................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
EN2
1
16 PWRGD3
PWRGD2
2
15 EN3
PWRGD1
3
14 SQTIMER
VIN
4
13 TIMER
RESET
5
12 UV
SS
6
11 OV
SENSE
7
10 DRAIN
VEE
8
9
GATE
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4253CGN#PBF
LTC4253CGN#TRPBF
4253
16-Lead Plastic SSOP
0°C to 70°C
LTC4253IGN#PBF
LTC4253IGN#TRPBF
4253I
16-Lead Plastic SSOP
–40°C to 85°C
LTC4253ACGN#PBF
LTC4253ACGN#TRPBF
4253A
16-Lead Plastic SSOP
0°C to 70°C
LTC4253AIGN#PBF
LTC4253AIGN#TRPBF
4253AI
16-Lead Plastic SSOP
–40°C to 85°C
OBSOLETE PACKAGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
425353afe
2
LTC4253/LTC4253A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
LTC4253
LTC4253A
SYMBOL
PARAMETER
CONDITIONS
VZ
VIN – VEE Zener Voltage
IIN = 2mA
RZ
VIN – VEE Zener Dynamic Impedance
IIN = (2mA to 30mA)
IIN
VIN Supply Current
UV = OV = 4V, VIN = (VZ – 0.3V)
●
0.8
2
1.1
2
mA
VLKO
VIN Undervoltage Lockout
Coming Out of UVLO (Rising VIN)
●
9.2
11.5
9
10
V
VLKH
VIN Undervoltage Lockout Hysteresis
●
0.5
1
1.5
0.5
0.75
V
VIH
TTL Input High Voltage
●
2
VIL
TTL Input Low Voltage
●
VHYST
TTL Input Buffer Hysteresis
IRESET
RESET Input Current
VEE ≤ VRESET ≤ VIN
●
IEN
EN2, EN3 Input Current
VEN = 4V VEN = 0V
●
●
VCB
Circuit Breaker Current Limit Voltage
VCB = (VSENSE – VEE)
VACL
Analog Current Limit Voltage
VACL
VCB
●
MIN
TYP
MAX
MIN
TYP
MAX UNITS
11.5
13
14.5
11.5
13
14.5
5
5
0.25
V
0.8
0.8
600
600
±10
60
120
±0.1
180
±10
●
40
50
60
VACL = (VSENSE – VEE), SS = Open or 2.2V
●
80
100
120
Analog Current Limit Voltage
Circuit Breaker Current Limit Voltage
VACL = (VSENSE – VEE), SS = Open or 1.4V
●
VFCL
Fast Current Limit Voltage
VFCL = (VSENSE – VEE)
●
150
200
VSS
SS Voltage
After End of SS Timing Cycle
●
2
ISS
SS Pin Current
UV = OV = 4V, VSENSE = VEE,
VSS = 0V (Sourcing)
●
12
UV = OV = 0V, VSENSE = VEE,
VSS = 1V (Sinking)
Ω
2
±0.1
V
V
mV
±0.1
±10
μA
60
120
±0.1
180
±10
μA
μA
45
50
55
mV
mV
1.05
1.20
1.38
V/V
300
150
200
300
mV
2.2
2.4
1.25
1.4
1.55
V
22
32
16
28
40
μA
28
28
mA
RSS
SS Output Impedance
100
50
kΩ
VOS
Analog Current Limit Offset Voltage
10
10
mV
0.05
0.05
V/V
VACL + VOS Ratio (VACL + VOS) to SS Voltage
VSS
IGATE
GATE Pin Output Current
UV = OV = 4V, VSENSE = VEE,
VGATE = 0V (Sourcing)
●
30
50
70
30
50
70
μA
UV = OV = 4V, VSENSE – VEE = 0.15V,
VGATE = 3V (Sinking)
17
17
mA
UV = OV = 4V, VSENSE – VEE = 0.3V,
VGATE = 1V (Sinking)
190
190
mA
●
VGATE
External MOSFET Gate Drive
VGATE – VEE, IIN = 2mA
10
VGATEL
Gate Low Threshold
Before Gate Ramp Up
0.5
0.5
V
VGATEH
Gate High Threshold
VGATEH = VIN – VGATE, for PWRGD1,
PWRGD2, PWRGD3 Status
2.8
2.8
V
VUVHI
UV Pin Threshold HIGH
UV Low to High
● 3.075 3.225 3.375
VUVLO
UV Pin Threshold LOW
UV High to Low
● 2.775 2.925 3.075
VUV
UV Pin Threshold
UV Low to High
●
VUVHST
UV Pin Hysteresis
230
12
300
VZ
10
12
VZ
V
V
3.05
3.08
3.11
V
292
324
356
mV
mV
350
●
V
VOVHI
OV Pin Threshold HIGH
OV Low to High
●
5.85
6.15
6.45
V
VOVLO
OV Pin Threshold LOW
OV High to Low
●
5.55
5.85
6.15
V
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LTC4253/LTC4253A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LTC4253
SYMBOL
PARAMETER
CONDITIONS
VOV
OV Pin Threshold
OV Low to High
VOVHST
OV Pin Hysteresis
MIN
TYP
LTC4253A
MAX
●
230
300
MIN
TYP
MAX UNITS
5.04
5.09
5.14
V
82
102
122
mV
mV
350
●
ISENSE
SENSE Pin Input Current
UV = 0V = 4V, VSENSE = 50mV
(Sourcing)
●
15
30
15
30
μA
IINP
UV, OV Pin Input Current
UV = OV = 4V
●
± 0.1
±1
±0.1
±1
μA
VTMRH
TIMER Pin Voltage High Threshold
4
4.5
3.5
4
4.5
V
VTMRL
TIMER Pin Voltage Low Threshold
ITMR
TIMER Pin Current
Timer On (Initial Cycle/Latchoff,
Sourcing), VTMR = 2V
●
3.5
●
0.8
1
1.2
0.8
1
1.2
V
●
3
5
7
3
5
7
μA
28
Timer Off (Initial Cycle, Sinking),
VTMR = 2V
Timer On (Circuit Breaker, Sourcing,
IDRN = 0μA), VTMR = 2V
●
120
Timer On (Circuit Breaker, Sourcing,
IDRN = 50μA), VTMR = 2V
Timer Off (Circuit Breaker, Sinking),
VTMR = 2V
200
28
280
120
600
200
mA
280
600
μA
●
3
5
7
3
5
7
μA
μA/μA
ΔITMRACC
ΔIDRN
ITMR at IDRN = 50μA – ITMR at IDRN = 0μA Timer On (Circuit Breaker with
50μA
IDRN = 50μA)
●
7
8
9
7
8
9
VSQTMRH
SQTIMER Pin Voltage High Threshold
●
3.5
4
4.5
3.5
4
4.5
VSQTMRL
SQTIMER Pin Voltage Low Threshold
ISQTMR
SQTIMER Pin Current
0.33
SQTIMER On (Power Good
Sequence, Sourcing), VSQTMR = 2V
●
3
SQTIMER Off (Power Good
Sequence, Sinking), VSQTMR = 2V
VDRNL
DRAIN Pin Voltage Low Threshold
For PWRGD1, PWRGD2, PWRGD3 Status
IDRNL
DRAIN Leakage Current
VDRAIN = 5V
VDRAIN = 4V
μA
5
0.33
7
3
28
●
2
3
± 0.1
±1
DRAIN Pin Clamp Voltage
IDRN = 50μA
●
VPGL
PWRGD1, PWRGD2, PWRGD3
Output Low Voltage
IPG = 1.6mA
IPG = 5mA
●
●
IPGH
PWRGD1, PWRGD2, PWRGD3
Output High Current
VPG = 0V (Sourcing)
●
tSQ
SQTIMER Default Ramp Period
SQTIMER Pin Floating,
VSQTMR Ramps from 0.5V to 3.5V
250
tSS
SS Default Ramp Period
SS Pin Floating, VSS Ramps from 0.2V to 2V
SS Pin Floating, VSS Ramps from 0.2V to 1.25V
250
6
30
V
7
28
2.39
VDRNCL
5
7
8.5
0.25
0.4
1.2
50
70
2
5
30
V
μA
mA
2.39
3
V
± 0.1
±1
μA
μA
6
7.5
V
0.25
0.4
1.2
V
V
50
70
μA
250
μs
140
μs
μs
tPLLUG
UV Low to GATE Low
●
0.4
5
0.4
5
μs
tPHLOG
OV High to GATE Low
●
0.4
5
0.4
5
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specified.
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LTC4253/LTC4253A
TYPICAL PERFORMANCE CHARACTERISTICS
VZ vs Temperature
14.5
IIN vs VIN
IIN vs Temperature
1000
IIN = 2mA
1000
950
14.0
900
100
13.0
TA = –40°C
TA = 85°C
TA = 25°C
TA = 125°C
10
850
IIN (μA)
VZ (V)
IIN (mA)
13.5
VIN = VZ – 0.3V
800
750
700
650
1
12.5
600
550
12.0
–55 –35 –15
0.1
5 25 45 65 85 105 125
TEMPERATURE (°C)
0
5
10
VIN (V)
15
500
–55 –35 –15
20
4253 G01
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G02
4253 G03
Circuit Breaker Current Limit
Voltage VCB vs Temperature
IEN vs VEN
IIN = 2mA
160 TA = 25°C
140
VCB (mV)
IEN (μA)
120
100
80
60
55
150
54
140
53
130
52
120
51
110
VACL (mV)
180
Analog Current Limit Voltage
VACL vs Temperature
50
49
90
48
80
40
47
70
20
46
60
0
0
2
4
6
8
10
VEN (V)
12
14
45
–55 –35 –15
16
4253 G05
Fast Current Limit Voltage VFCL vs
Temperature
58
260
56
240
54
220
52
180
140
44
120
42
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G07
25
40
–55 –35 –15
UV/OV = 4V
TIMER = 0V
VSENSE – VEE = 0.15V
VGATE = 3V
20
48
46
100
–55 –35 –15
UV/OV = 4V
TIMER = 0V
VSENSE = VEE
VGATE = 0V
50
160
IGATE (ACL, Sink) vs Temperature
30
IGATE (mA)
280
IGATE (μA)
60
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G06
IGATE (Source) vs Temperature
300
200
50
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G04
VFCL (mV)
100
15
10
5
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G08
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G09
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LTC4253/LTC4253A
TYPICAL PERFORMANCE CHARACTERISTICS
IGATE (FCL, Sink) vs Temperature
400
UV/OV = 4V
TIMER = 0V
VSENSE – VEE = 0.3V
VGATE = 1V
350
300
14.0
13.5
UV/OV = 4V
TIMER = 0V
VSENSE = VEE
IIN = 2mA
0.9
0.8
150
12.5
12.0
11.5
0.6
0.5
0.4
0.3
100
11.0
0.2
50
10.5
0.1
10.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
IIN = 2mA
3.275
UV THRESHOLD (V)
2.8
2.6
3.175
VUV
3.075
2.975
VUVL
2.875
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.775
–55 –35 –15
ISENSE vs (VSENSE – VEE)
–5
ISENSE (μA)
10
–0.5
0
0.5
VSENSE – VEE (V)
1
1.5
4253 G16
5 25 45 65 85 105 125
TEMPERATURE (°C)
TIMER Threshold vs Temperature
UV/OV = 4V
TIMER = 0V
VSENSE – VEE = 50mV
VGATE = HIGH
4.5
IIN = 2mA
4.0
–15
–20
UV/OV = 4V
TIMER = 0V
GATE = HIGH
TA = 25°C
VOV
4352 G15
5.0
–10
–1
5.4
ISENSE vs Temperature
0
0.1
1000
–1.5
5.6
4253 G14
0.01
1
VOVL
5.8
5.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G13
100
6.0
5.2
TIMER THRESHOLD (V)
2.0
–55 –35 –15
VOVH
VUVH
2.4
2.2
IIN = 2mA
6.2
OV THRESHOLD (V)
UV/OV = 4V
VGATEH = VIN – VGATE
IIN = 2mA
OV Threshold vs Temperature
6.4
3.2
–ISENSE (mA)
4253 G12
UV Threshold vs Temperature
3.375
3.0
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G11
VGATEH vs Temperature
3.4
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G10
3.6
UV/OV = 4V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP UP
0.7
VGATEL (V)
200
0
–55 –35 –15
VGATEH (V)
VGATEL vs Temperature
1.0
13.0
250
VGATE (V)
IGATE (mA)
VGATE vs Temperature
14.5
3.5
3.0
2.5
2.0
1.5
1.0
–25
VTMRH
VTMRL
0.5
–30
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G17
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G18
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LTC4253/LTC4253A
TYPICAL PERFORMANCE CHARACTERISTICS
ITMR (Initial Cycle, Sourcing)
vs Temperature
10
9
ITMR (Circuit Breaker, Sourcing)
vs Temperature
240
IIN = 2mA
VTMR = 2V
IIN = 2mA
IDRN = 0μA
230
8
ITMR vs IDRN
10
IIN = 2mA
TA = 25°C
220
5
4
210
ITMR (mA)
6
ITMR (μA)
ITMR (μA)
7
200
190
3
1
180
2
170
1
0
–55 –35 –15
160
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
IIN = 2mA
8.6
4.0
8.4
3.5
7.8
2.5
2.0
1.5
7.4
1.0
7.2
0.5
7.0
–55 –35 –15
2.45
2.40
2.35
2.30
VSQTMRL
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.25
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.20
–55 –35 –15
VDRNCL vs Temperature
4253 G24
IDRN vs VDRAIN
8.0
100
IIN = 2mA
7.8 IDRN = 50μA
VPGL vs Temperature
3.0
IIN = 2mA
10
IIN = 2mA
2.5
7.6
IPG = 10mA
1
7.4
2.0
7.0
6.8
6.6
0.1
VPGL (V)
7.2
IDRN (mA)
VDRNCL (V)
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G23
4253 G22
TA = 85°C
0.01
TA = 125°C
0.0001
6.2
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G25
1.5
1.0
0.001
6.4
6.0
–55 –35 –15
IIN = 2mA
2.50
3.0
7.6
10
2.55
VSQTMRH
VDRNL (V)
8.0
1
VDRNL vs Temperature
2.60
IIN = 2mA
4.5
VSQTMR (V)
ΔITMRACC /ΔIDRN (μA/μA)
5.0
8.2
0.1
IDRN (mA)
4253 G21
SQTIMER Threshold
vs Temperature
ΔITMRACC/ΔIDRN vs Temperature
8.8
0.01
4253 G20
4253 G19
9.0
0.1
0.001
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.5
TA = 25°C
IPG = 5mA
IPG = 1.6mA
TA = –40°C
0.00001
0
2
4
6
8
10
VDRAIN (V)
12
14
16
4253 G26
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G27
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LTC4253/LTC4253A
TYPICAL PERFORMANCE CHARACTERISTICS
IPGH vs Temperature
tSS vs Temperature
60
300
290
IIN = 2mA
SS PIN FLOATING
VSS RAMPS FROM 0.2V TO 2V
450
56
280
54
270
350
52
260
300
50
48
250
250
240
200
46
230
150
44
220
100
42
210
50
40
–55 –35 –15
200
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G28
IIN = 2mA
VSQTMR RAMPS FROM 0.5V TO 3.5V
400
tSQ (μs)
tSS (μs)
VPGH (μA)
IIN = 2mA
58 VPWRGD = 0V
tSQ vs Temperature
500
4253 G29
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4253 G30
PIN FUNCTIONS
EN2 (Pin 1): Power Good Status Output Two Enable. This
is a TTL compatible input that is used to control PWRGD2
and PWRGD3 outputs. When EN2 is driven low, both
PWRGD2 and PWRGD3 will go high. When EN2 is driven
high, PWRGD2 will go low provided PWRGD1 has been
active for more than one power good sequence delay
(tSQT) provided by the sequencing timer. EN2 can be used
to control the power good sequence. This pin is internally
pulled low by a 120μA current source.
VIN (Pin 4): Positive Supply Input. Connect this pin to the
positive side of the supply through a dropping resistor. A
shunt regulator clamps VIN at 13V above VEE. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO, overriding UV and OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating GATE ramp
up. If VIN drops below approximately 8.2V (8.5V for the
LTC4253A), GATE pulls low immediately.
PWRGD2 (Pin 2): Power Good Status Output Two. Power
good sequence starts with PWRGD1 latching active low.
PWRGD2 will latch active low after EN2 goes high and
after one power good sequence delay tSQT provided by
the sequencing timer from the time PWRGD1 goes low,
whichever comes later. PWRGD2 is reset by PWRGD1
going high or EN2 going low. This pin is internally pulled
high by a 50μA current source.
RESET (Pin 5): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull
GATE, SS, TIMER, SQTIMER low and the PWRGD outputs
high. The RESET pulse must be wide enough to discharge
any voltage on the TIMER pin below VTMRL. After the reset
of a latched fault, the chip waits for the interlock conditions
before recovering as described in Interlock Conditions in
the Operation section.
PWRGD1 (Pin 3): Power Good Status Output One. At startup, PWRGD1 latches active low and starts the power good
sequence when the DRAIN pin is below 2.39V and GATE
is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN
(UVLO), RESET going high or circuit breaker fault time-out.
This pin is internally pulled high by a 50μA current source.
SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/dt.
A 20X attenuated version of the SS pin voltage is presented
to the current limit amplifier. This attenuated voltage limits
the MOSFET’s drain current through the sense resistor
during the soft-start current limiting. At the beginning of
425353afe
8
LTC4253/LTC4253A
PIN FUNCTIONS
the start-up cycle, the SS capacitor (CSS) is ramped by a
22μA (28μA for the LTC4253A) current source. The GATE
pin is held low until SS exceeds 20 • VOS = 0.2V. SS is
internally shunted by a 100k RSS which limits the SS pin
voltage to 2.2V (50k resistor and 1.4V for the LTC4253A).
This corresponds to an analog current limit SENSE voltage
of 100mV (60mV for the LTC4253A). If the SS capacitor
is omitted, the SS pin ramps up in about 250μs (140μs
for the LTC4253A). The SS pin is pulled low under any of
the following conditions: UVLO at VIN, UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high.
SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin.
Load current is monitored by a sense resistor RS connected
between SENSE and VEE, and controlled in three steps. If
SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200μA + 8 • IDRN) TIMER pull-up current.
If SENSE exceeds VACL, the analog current-limit amplifier
pulls GATE down to regulate the MOSFET current at VACL/
RS. In the event of a catastrophic short-circuit, SENSE may
overshoot VACL. If SENSE reaches VFCL (200mV), the fast
current-limit comparator pulls GATE low with a strong
pull-down. To disable the circuit breaker and current limit
functions, connect SENSE to VEE.
VEE (Pin 8): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
GATE (Pin 9): N-channel MOSFET Gate Drive Output. This
pin is pulled high by a 50μA current source. GATE is pulled
low by invalid conditions at VIN (UVLO), UV, OV, during the
initial timing cycle, a circuit breaker fault time-out or the
RESET pin going high. GATE is actively servoed to control
the fault current as measured at SENSE. Compensation
capacitor, CC, at GATE stabilizes this loop. A comparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, then the GATE ramps up after an overvoltage event or restart after a current limit fault. During
GATE start-up, a second comparator detects GATE within
2.8V of VIN before PWRGD1 can be set and power good
sequencing starts.
DRAIN (Pin 10): Drain Sense Input. Connecting an external
resistor, RD between this pin and the MOSFET’s drain (VOUT)
allows voltage sensing below 6.15V (5V for LTC4253A)
and current feedback to TIMER. A comparator detects if
DRAIN is below 2.39V and together with the GATE high
comparator, sets the PWRGD1 flag. If VOUT is above VDRNCL,
the DRAIN pin is clamped at approximately VDRNCL. RD
current is internally multiplied by 8 and added to TIMER’s
200μA during a circuit breaker fault cycle. This reduces
the fault time and MOSFET heating.
OV (Pin 11): Overvoltage Input. For the LTC4253, the
threshold at the OV pin is set at 6.15V with 0.3V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns
below 5.85V, GATE start-up begins without an initial timing
cycle. The LTC4253A OV threshold is set at 5.09V with
102mV hysteresis. If OV > 5.09V, GATE pulls low. When
OV returns below 4.988V, GATE start-up begins without an
initial timing cycle. If OV occurs in the middle of an initial
timing cycle, the initial timing cycle is restarted after OV
goes away. OV does not reset the latched fault or PWRGD1
flag. The internal UVLO at VIN always overrides OV. A 1nF
to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents
glitches at the GATE.
UV (Pin 12): Undervoltage Input. For the LTC4253, the
threshold at the UV pin is set at 3.225V with 0.3V hysteresis.
If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER
pull low. If UV rises above 3.225V, this initiates an initial
timing cycle followed by GATE start-up. The LTC4253A UV
threshold is set at 3.08V with 324mV hysteresis. If UV <
2.756V, PWRGD1 pulls high, both GATE and TIMER pull
low. If UV rises above 3.08V, this initiates an initial timing
cycle followed by GATE start-up. The internal UVLO at VIN
always overrides UV. A low at UV resets an internal fault
latch. A 1nF to 10nF capacitor at UV prevents transients
and switching noise from affecting the UV thresholds and
prevents glitches at the GATE pin.
425353afe
9
LTC4253/LTC4253A
PIN FUNCTIONS
TIMER (Pin 13): Timer Input. Timer is used to generate
an initial timing delay at start-up, and to delay shutdown
in the event of an output overload (circuit breaker fault).
Timer starts an initial timing cycle when the following
conditions are met: RESET is low, UV is high, OV is low,
VIN clears UVLO, TIMER pin is low, GATE pin is lower
than VGATEL, SS < 0.2V, and VSENSE – VEE < VCB. A pull-up
current of 5μA then charges CT, generating a time delay.
If CT charges to VTMRH (4V), the timing cycle terminates.
TIMER quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit breaker
cycle begins with a 200μA pull-up current charging CT. If
DRAIN is approximately 7V (6V for the LTC4253A) during this cycle, the timer pull-up has an additional current
of 8 • IDRN. If SENSE drops below 50mV before TIMER
reaches 4V, a 5μA pull-down current slowly discharges
the CT. In the event that CT eventually integrates up to
the VTMRH (4V) threshold, the circuit breaker trips, GATE
quickly pulls low and PWRGD1 pulls high. TIMER latches
high with a 5μA pull-up source. This latched fault may be
cleared by driving RESET high until TIMER is pulled low.
Other ways of clearing the fault include pulling the VIN pin
momentarily below (VLKO – VLKH), pulling TIMER low with
an external device or pulling UV below 2.925V (2.756V
for the LTC4253A).
SQTIMER (Pin 14): Sequencing Timer Input. The sequencing timer provides a delay tSQT for the power good sequencing. This delay is adjusted by connecting an appropriate
capacitor to this pin. If the SQTIMER capacitor is omitted,
the SQTIMER pin ramps from 0V to 4V in about 300μs.
EN3 (Pin 15): Power Good Status Output Three Enable.
This is a TTL compatible input that is used to control the
PWRGD3 output. When EN3 is driven low, PWRGD3 will
go high. When EN3 is driven high, PWRGD3 will go low
provided PWRGD2 has been active for for more than one
power good sequence delay (tSQT). EN3 can be used to
control the power good sequence. This pin is internally
pulled low by a 120μA current source.
PWRGD3 (Pin 16): Power Good Status Output Three.
Power good sequence starts with PWRGD1 latching active
low. PWRGD3 will latch active low after EN3 goes high
and after one power good sequence delay tSQT provided
by the sequencing timer from the time PWRGD2 goes
low, whichever comes later. PWRGD3 is reset by PWRGD1
going high or EN3 going low. This pin is internally pulled
high by a 50μA current source.
425353afe
10
LTC4253/LTC4253A
BLOCK DIAGRAM
VIN
4
VIN
VIN
–
50μA
4V
5μA
VEE
PWRGD1 3
+
14 SQTIMER
VEE
EN2 1
VIN
–
120μA
50μA
VEE
+
PWRGD2 2
SQTIMER
DELAY
0.33V
VEE
–
10 DRAIN
VEE
VIN
EN3 15
+
VIN
2.39V
8×
120μA
50μA
1×
VEE
6.15V
(5V)
1×
PWRGD3 16
VIN
SQTIMER
DELAY
1×
VEE
50μA
9 GATE
VEE
VIN
6.15V
(5.09V)
VEE
–
OV 11
+
+
UV 12
–
–
VIN
2.925V
(2.756V)
+
5μA 4V
–
+
–
–
+
LOGIC
2.8V
0.5V
VIN
200μA
+
FCL
+
–
+
–
TIMER 13
VEE
–
5μA
VEE
1V
VIN
200mV
+
VEE
22μA
(28μA)
+
ACL
–
SS 6
10mV
95k
(47.5k)
+
RSS
5k
(2.5k)
VEE
+
–
VEE
7 SENSE
CB
–
+
–
VEE
50mV
VEE
FOR COMPONENTS, CURRENTS AND VOLTAGES WITH TWO
VALUES, VALUES WITHOUT PARENTHESES REFER TO THE
LTC4253, VALUES WITH PARENTHESES REFER TO THE LTC4253A
5
8
RESET
VEE
4253 BD
425353afe
11
LTC4253/LTC4253A
OPERATION
Hot Circuit Insertion
or power conversion circuitry with an external MOSFET
switch (see Figure 1). Both inrush control and short-circuit
protection are provided by the MOSFET.
When circuit boards are inserted into a live backplane,
the supply bypass capacitors can draw huge transient
currents from the power bus as they charge. The flow
of current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4253/LTC4253A are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
A detailed schematic is shown in Figure 2. – 48V and
–48RTN receive power through the longest connector pins
and are the first to connect when the board is inserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoring whether or not the connector is seated. The top
of the divider detects –48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
Initial Start-Up
The LTC4253/LTC4253A reside on a removable circuit
board and control the path between the connector and load
PLUG-IN BOARD
+
–48RTN
LTC4253
LTC4253A
+
ISOLATED
DC/DC
CONVERTER
MODULE
+
CLOAD
–
–48V
BACKPLANE
LOW
VOLTAGE
CIRCUITRY
–
4253 F01
Figure 1. Basic LTC4253/LTC4253A Hot Swap Topology
–48RTN
(LONG PIN)
RIN
2.5k
15k(1/4W)/6
DIN††
DDZ13B*
PUSH
RESET
–48RTN
(SHORT PIN)
VIN
R4
5.6k
CIN
1μF
R5
5.6k
CL
100μF
+
POWER
MODULE 1
R6
5.6k
POWER
MODULE 2
EN
EN
POWER
MODULE 3
EN
†
VIN
R3
432k
1%
UV
PWRGD1
OV
PWRGD2
RESET
PWRGD3
C1
10nF
EN2
SS
R9
47k
TIMER
VIN
Q1
IRF530S
GATE
VIN
SENSE
VEE
CT
0.33μF
EN2
RD 1M
R8
DRAIN
SQTIMER
CSQ
0.1μF
POWER
MODULE 2
OUTPUT
EN3
EN3
CSS 68nF
–48V
(LONG PIN)
†
LTC4253
R2
4.75k
1%
R1
38.3k
1%
†
RC
10Ω
CC
18nF
RS
0.02Ω
R7
POWER
MODULE 1
OUTPUT
†
†
4253 F02
*DIODES, INC.
†MOC207
††RECOMMENDED FOR HARSH ENVIRONMENTS.
Figure 2. –48V/2.5A Application with a Wider Operating Range
425353afe
12
LTC4253/LTC4253A
OPERATION
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met:
1. The input voltage VIN exceeds VLKO (UVLO).
2. The voltage at UV > VUVHI (VUV for the LTC4253A).
3. The voltage at OV < VOVLO (VOV – VOVHST for the
LTC4253A).
4. The input voltage at RESET < 0.8V.
5. The (SENSE – VEE) voltage < 50mV (VCB)
6. The voltage at SS is < 0.2V (20 • VOS)
7. The voltage on the TIMER capacitor (CT)
is < 1V (VTMRL).
8. The voltage at GATE is < 0.5V (VGATEL)
The first four conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
If RESET < 0.8V occurs after the LTC4253/LTC4253A come
out of UVLO (interlock condition 1) and undervoltage (interlock condition 2), GATE and SS are released without an
initial TIMER cycle once the other interlock conditions are
met (see Figure 13a). If not, TIMER begins the start-up
sequence by sourcing 5μA into CT. If VIN, UV or OV falls
out of range or RESET asserts, the start-up cycle stops
and TIMER discharges CT to less than 1V, then waits until
the aforementioned conditions are once again met. If CT
successfully charges to 4V, TIMER pulls low and both SS
and GATE pins are released. GATE sources 50μA (IGATE),
charging the MOSFET gate and associated capacitance.
The SS voltage ramp limits VSENSE to control the inrush
current. PWRGD1 pulls active low when GATE is within
2.8V of VIN and DRAIN is lower than VDRNL. This sets off
the power good sequence in which PWRGD2 and then
PWRGD3 is subsequently pulled low after a delay, adjustable through the SQTIMER capacitor CSQ or by external
control inputs EN2 and EN3. In this way, external loads
or power modules controlled by the three PWRGD signals
are turned on in a controlled manner without overloading
the power bus.
Two modes of operation are possible during the time the
MOSFET is first turned on, depending on the values of
external components, MOSFET characteristics and nominal
design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp
to –48V and the LTC4253/LTC4253A will fully enhance
the MOSFET. A second possibility is that the load current
exceeds the soft-start current limit threshold of [VSS(t)/
20 – VOS]/RS. In this case the LTC4253/LTC4253A ramp
the output by sourcing soft-start limited current into the
load capacitance. If the soft-start voltage is below 1.2V,
the circuit breaker TIMER is held low. Above 1.2V, TIMER
ramps up. It is important to set the timer delay so that,
regardless of which start-up mode is used, the TIMER
ramp is less than one circuit breaker delay time. If this
condition is not met, the LTC4253/LTC4253A may shut
down after one circuit breaker delay time.
Board Removal
When the board is withdrawn from the card cage, the UV/
OV divider is the first to lose connection. This shuts off
the MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate
there is no arcing.
Current Control
Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop (60mV for the LTC4253A); and
200mV for a fast, feedforward comparator which limits
peak current in the event of a catastrophic short-circuit.
If, due to an output overload, the voltage drop across RS
exceeds 50mV, TIMER sources 200μA into CT. CT eventually
charges to a 4V threshold and the LTC4253/LTC4253A shut
off. If the overload goes away before CT reaches 4V and
SENSE measures less than 50mV, CT slowly discharges
(5μA). In this way the LTC4253/LTC4253A’s circuit breaker
function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling characteristic
of the MOSFET.
425353afe
13
LTC4253/LTC4253A
OPERATION
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches VACL, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of VACL/RS. In current limit mode,
VOUT (MOSFET drain-source voltage drop) typically rises
and this increases MOSFET heating. If VOUT > VDRNCL,
connecting an external resistor, RD between VOUT and
DRAIN allows the fault timing cycle to be shortened by
accelerating the charging of the TIMER capacitor. The
TIMER pull-up current is increased by 8 • IDRN. Note that
because SENSE > 50mV, TIMER charges CT during this
time, and the LTC4253/LTC4253A eventually shut down.
Low impedance failures on the load side of the LTC4253/
LTC4253A, coupled with 48V or more driving potential,
can produce current slew rates well in excess of 50A/μs.
Under these conditions, overshoot is inevitable. A fast
SENSE comparator with a threshold of 200mV detects
overshoot and pulls GATE low much harder and hence
much faster than the weaker current limit loop. The VACL/
RS current limit loop then takes over and servos the current as previously described. As before, TIMER runs and
shuts down the LTC4253/LTC4253A when CT reaches 4V.
If CT reaches 4V, the LTC4253/LTC4253A latch off with a
5μA pull-up current source. The LTC4253/LTC4253A circuit
breaker latch is reset by either pulling the RESET pin active
high until TIMER goes low, pulling UV momentarily low,
dropping the input voltage VIN below the internal UVLO
threshold or pulsing TIMER momentarily low with a switch.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noise spikes from the backplane or load, input
steps caused by the connection of a second, higher voltage
supply, transient currents caused by faults on adjacent
circuit boards sharing the same power bus or the insertion
of non-hot swappable products could cause higher than
anticipated input current and temporary detection of an
overcurrent condition. The action of TIMER and CT rejects
these events allowing the LTC4253/LTC4253A to “ride out”
temporary overloads and disturbances that could trip a
simple current comparator and, in some cases, blow a fuse.
APPLICATIONS INFORMATION
SHUNT REGULATOR
A fast responding shunt regulator clamps the VIN pin to
13V (VZ). Power is derived from –48RTN by an external
current limiting resistor, RIN. A 1μF decoupling capacitor,
CIN filters supply transients and contributes a short delay
at start-up.
To meet creepage requirements RIN may be split into two
or more series connected units. This introduces a wider
total spacing than is possible with a single component
while at the same time ballasting the potential across the
gap under each resistor. The LTC4253 is fundamentally a
low voltage device that operates with –48V as its reference
ground. To further protect against arc discharge into its
pins, the area in and around the LTC4253 and all associated components should be free of any other planes such
as chassis ground, return, or secondary-side power and
ground planes.
VIN may be biased with additional current up to 30mA, to
accomodate external loading such as the PWRGD optocouplers shown in Figure 2. As an alternative to running
higher current, simply buffer VIN with an emitter follower
as shown in Figure 3. A method that cascodes the PWRGD
outputs as shown in Figure 17.
VIN is rated to handle 30mA within the thermal limits of
the package, and is tested to survive a 100μs, 100mA
425353afe
14
LTC4253/LTC4253A
APPLICATIONS INFORMATION
(Refer to Block Diagram)
pulse. To protect VIN against damage from higher amplitude spikes, clamp VIN to VEE with a 13V Zener diode.
Star connect VEE and all VEE-referred components to the
sense resistor Kelvin terminal as illustrated in Figure 3,
keeping trace lengths between VIN, CIN, DIN and VEE as
short as possible.
An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds:
OV low-to-high (VOVHI) = 6.150V
OV high-to-low (VOVLO) = 5.850V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 82V when
connected together as in the Typical Application. A resistive
divider is used to scale the supply voltage. Using 402k and
32.4k gives a typical operating range of 43.2V to 82.5V.
The undervoltage shutdown and overvoltage recovery
thresholds are then 39.2V and 78.4V. 1% divider resistors
are recommended to preserve threshold accuracy.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis
VLKH. When VIN rises above VLKO, the chip is enabled;
below (VLKO – VLKH), it is disabled and GATE is pulled low.
The UVLO function at VIN should not be confused with the
UV and OV pins. These are completely separate functions.
The resistive divider values shown set a standing current
of slightly more than 100μA and define an impedance at
UV/OV of 30kΩ. In most applications, 30kΩ impedance
coupled with 300mV UV hysteresis make the LTC4253
insensitive to noise. If more noise immunity is desired,
add a 1nF to 10nF filter capacitor from UV/OV to VEE.
UV/OV COMPARATORS (LTC4253)
A UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:
UV low-to-high (VUVHI) = 3.225V
UV high-to-low (VUVLO) = 2.925V
– 48V RTN
(LONG PIN)
R3 22k
RIN
10k
20k(1/4W)/2
CIN
1μF
PUSH
RESET
– 48V RTN
(SHORT PIN)
Q2
FZT857
VIN1
R4
2.2k
R5
2.2k
CL
100μF
R6
2.2k
DIN††
+
POWER
MODULE 1
POWER
MODULE 2
EN
DDZ13B*
EN
POWER
MODULE 3
EN
CSS 33nF
PWRGD1
OV
PWRGD2
RESET
PWRGD3
†
EN2
SS
R9
47k
CSQ
0.1μF
EN2
VIN1
RD 1M
R8
DRAIN
TIMER
Q1
IRF530S
GATE
VIN1
R7
SENSE
VEE
CT
0.68μF
POWER
MODULE 2
OUTPUT
EN3
EN3
SQTIMER
– 48V
(LONG PIN)
†
LTC4253A
UV
C1
10nF
R1
30.1k
1%
†
VIN
R2
392k
1%
RC
10Ω
CC
10nF
RS
0.02Ω
POWER
MODULE 1
OUTPUT
†
†
4253 F03
*DIODES, INC.
†
MOC207
††
RECOMMENDED FOR HARSH ENVIRONMENTS.
Figure 3. –48V/2.5A Application for the LTC4253A
425353afe
15
LTC4253/LTC4253A
APPLICATIONS INFORMATION
The separate UV and OV pins can be used for wider operating range such as 35.6V to 76.3V range as shown in
Figure 2. Other combinations are possible with different
resistors arrangement.
UV/OV COMPARATORS (LTC4253A)
A UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:
UV low-to-high (VUV) = 3.08V
UV high-to-low (VUV – VUVHST) = 2.756V
An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds:
OV low-to-high (VOV) = 5.09V
OV high-to-low (VOV – VOVHST) = 4.988V
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4253/
LTC4253A, pulls the MOSFET gate low and resets the three
latched PWRGD signals high.
An overvoltage condition is detected by the OV comparator and pulls GATE low, thereby shutting down the load,
but it will not reset the circuit breaker TIMER and PWRGD
flags. Returning from the overvoltage condition will
restart the GATE pin if all the interlock conditions except
TIMER are met. Only during the initial timing cycle does
OV condition have an effect of resetting TIMER.
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connected together as in Figure 3. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 392k and R2
= 30.1k gives a typical operating range of 43.2V to 71.4V.
The undervoltage shutdown and overvoltage recovery
thresholds are then 38.6V and 69.9V. 1% divider resistors
are recommended to preserve threshold accuracy.
DRAIN
The R1-R2 divider values shown in Figure 3 set a standing current of slightly more than 100μA and define an
impedance at UV/OV of 28kΩ. In most applications, 28kΩ
impedance coupled with 324mV UV hysteresis makes
the LTC4253A insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from
UV/OV to VEE.
When VOUT > VDRNCL, the DRAIN pin is clamped at VDRNCL
and the current flowing in RD is given by:
The UV and OV pins can also be used for a wider operating
range by adding a resistor between UV and OV as shown
in Figure 2 for the LTC4253. Other combinations are possible with different resistor arrangements.
Connecting an external resistor, RD, to this dual function
DRAIN pin allows VOUT (MOSFET drain-source voltage
drop) sensing without it being damaged by large voltage
transients. Below 5V, negligible pin leakage allows a DRAIN
low comparator to detect VOUT less than 2.39V (VDRNL).
This, together with the GATE low comparator, sets the
PWRGD flag.
IDRN ≈
VOUT − VDRNCL
RD
(1)
This current is scaled up 8 times during a circuit breaker
fault before being added to the nominal 200μA. This accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds VDRNCL and effectively
shortens the MOSFET heating duration.
425353afe
16
LTC4253/LTC4253A
APPLICATIONS INFORMATION
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor CT is used
at TIMER to provide timing for the LTC4253/LTC4253A.
Four different charging and discharging modes are available at TIMER:
1. 5μA slow charge; initial timing delay.
2. (200μA + 8 • IDRN) fast charge; circuit breaker delay.
3. 5μA slow discharge; circuit breaker “cool-off.”
4. Low impedance switch; resets the TIMER capacitor after
an initial timing delay, in UVLO, in UV and in OV during
initial timing and when RESET is high.
For initial timing delay, the 5μA pull-up is used. The
low impedance switch is turned off and the 5μA current
source is enabled when the interlock conditions are met.
CT charges to 4V in a time period given by:
4V • CT
t=
5μA
(2)
When CT reaches VTMRH ( 4V), the low impedance switch
turns on and discharges CT. A GATE start-up cycle begins
and both SS and GATE outputs are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV drop across RS,
the TIMER pin charges CT with (200μA + 8 • IDRN). If CT
charges to 4V, the GATE pin pulls low and the LTC4253/
LTC4253A latch off. The LTC4253/LTC4253A remain
latched off until the RESET pin is momentarily pulsed
high, the UV pin is momentarily pulsed low, the TIMER
pin is momentarily discharged low by an external switch
or VIN dips below UVLO and is then restored. The circuit
breaker timeout period is given by:
t=
4V • CT
200μA + 8 •IDRN
If VOUT < 5V, an internal PMOS isolates DRAIN pin leakage
current and this makes IDRN = 0 in Equation (3). If VOUT is
above VDRNCL during the circuit breaker fault period, the
charging of CT is accelerated by 8 • IDRN of Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE but, if their duration is sufficiently short, TIMER will
not reach 4V and the LTC4253/LTC4253A will not shut the
external MOSFET off. To handle this situation, the TIMER
discharges CT slowly with a 5μA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermittent overload with VOUT < 5V and an aggregate duty cycle
of more than 2.5% will eventually trip the circuit breaker
and shut down the LTC4253/LTC4253A. Figure 4 shows
the circuit breaker response time in seconds normalized
to 1μF. The asymmetric charging and discharging of CT is
a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by:
4
t
=
for D > 2.5% (4)
CT (μF) ⎡⎣( 205 + 8 •IDRN ) • D − 5 ⎤⎦
10
NORMALIZED RESPONSE TIME (s/μF)
TIMER
IDRN = 0μA
4
t
=
CT(μF) t*DRN
t%o
1
0.1
0.01
0
20
40
60
80
FAULT DUTY CYCLE, D (%)
100
4253 F04
Figure 4. Circuit Breaker Response Time
(3)
425353afe
17
LTC4253/LTC4253A
APPLICATIONS INFORMATION
POWER GOOD SEQUENCING
After the initial TIMER cycle, GATE ramps up to turn on
the external MOSFET which in turn pulls DRAIN low.
When GATE is within 2.8V of VIN and DRAIN is lower than
VDRNL, the power good sequence starts with PWRGD1 pulling active low. This starts off a 5μA pull-up on the SQTIMER
pin which ramps up until it reaches the 4V threshold then
pulls low. When the SQTIMER pin floats, this delay tSQT is
about 300μs. Connecting an external capacitor CSQ from
SQTIMER to VEE modifies the delay to:
t SQT =
4V • CSQ
5μA
(5)
PWRGD2 asserts when EN2 goes high and PWRGD1 has
asserted for more than one tSQT. When PWRGD2 successfully pulls low, SQTIMER ramps up on another delay
cycle. PWRGD3 asserts when EN2 and EN3 go high and
PWRGD2 has asserted for more than one tSQT.
All three PWRGD signals are reset in UVLO, in UV condition, if RESET is high or when CT charges up to 4V. In
addition, PWRGD2 is reset by EN2 going low. PWRGD3 is
reset by EN2 or EN3 going low. An overvoltage condition
has no effect on the PWRGD flags. A 50μA current pulls
each PWRGD pin high when reset. As power modules
signal common are different from PWRGD, optoisolation
is recommended. These three pins can sink an optodiode
current. Figure 17 shows an NPN configuration for the
PWRGD interface. A limiting base resistor should be used
for each NPN and the module enable input should have
protection from negative bias current.
SOFT-START
Soft-start is effective in limiting the inrush current during
GATE start-up. Unduly long soft-start intervals can exceed
the MOSFET’s SOA duration if powering-up into an active
load. When the SS pin floats, an internal current source
ramps SS from 0V to 2.2V in about 300μs (0V to 1.4V in
about 200μs for the LTC4253A). Connecting an external
capacitor, CSS, from SS to ground modifies the ramp to
approximate an RC response of:
–t ⎞
⎛
C
R
VSS (t) ≈ VSS ⎜ 1− e SS SS ⎟
⎜
⎟
⎝
⎠
(6)
An internal resistor divider (95k/5k for the LTC4253 and
47.5k/2.5k for the LTC4253A) scales VSS(t) down by 20
times to give the analog current limit threshold:
VACL (t) =
VSS (t)
– VOS
20
(7)
This allows the inrush current to be limited to VACL(t)/RS.
The offset voltage, VOS (10mV), ensures CSS is sufficiently
discharged and the ACL amplifier is in current limit mode
before GATE start-up. SS is discharged low during UVLO
at VIN , UV, OV, during the initial timing cycle, a latched
circuit breaker fault or the RESET pin going high.
GATE
GATE is pulled low to VEE under any of the following conditions: in UVLO, when RESET pulls high, in an undervoltage
condition, in an overvoltage condition, during the initial
timing cycle or a latched circuit breaker fault. When GATE
turns on, a 50μA current source charges the MOSFET gate
and any associated external capacitance. VIN limits the
gate drive to no more than 14.5V.
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
GATE has two comparators: the GATE low comparator looks
for <0.5V threshold prior to initial timing; the GATE high
comparator looks for <2.8V relative to VIN and, together
with DRAIN low comparator, sets PWRGD1 output during
GATE start-up.
425353afe
18
LTC4253/LTC4253A
APPLICATIONS INFORMATION
Sense
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
200μA TIMER pull-up. At 100mV (60mV for the LTC4253A)
the ACL amplifier servos the MOSFET current, and at
200mV the FCL comparator abruptly pulls GATE low in
an attempt to bring the MOSFET current under control. If
any of these conditions persists long enough for TIMER to
charge CT to 4V (see Equation 3), the LTC4253/LTC4253A
shut down and pull GATE low.
If the SENSE pin encounters a voltage greater than VACL,
the ACL amplifier will servo GATE downwards in an attempt
to control the MOSFET current. Since GATE overdrives the
MOSFET in normal operation, the ACL amplifier needs time
to discharge GATE to the threshold of the MOSFET. For a
mild overload the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV the FCL comparator
takes over, quickly discharging the GATE pin to near VEE
potential. FCL then releases, and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE undershoots.
A zero in the loop (resistor RC in series with the gate
capacitor) helps the ACL amplifier to recover.
TIMER commences charging CT (trace 4) while the analog
current limit loop maintains the fault current at 100mV/RS,
which in this case is 5A (trace 2). Note that the backplane
voltage (trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, the
PWRGD signals pull high, the load current drops to zero
and the backplane rings up to over 100V. The transient
associated with the GATE turn-off can be controlled with
a snubber to reduce ringing and a transient voltage suppressor (such as Diodes Inc. SMAT70A) to clip off large
spikes. The choice of RC for the snubber is usually done
experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET COSS.
The value of the snubber resistor is typically between 3Ω
to 100Ω.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 trace 1,
can rob charge from output capacitors on the adjacent
card. When the faulty card shuts down, current flows in
to refresh the capacitors. If LTC4253/LTC4253A are used
by the other cards, they respond by limiting the inrush
current to a value of VACL/RS. If CT is sized correctly, the
capacitors will recharge long before CT times out.
SUPPLY RING OWING
TO CURRENT OVERSHOOT
–48RTN
0.5ms
50V
SENSE
0.5ms
200mV
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5. Initially the current overshoots
the analog current limit level of VSENSE = 200mV (trace 2)
as the GATE pin works to bring VGS under control (trace 3).
The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the
backplane responds by glitching in the positive direction.
SUPPLY RING OWING
TO MOSFET TURN-OFF
GATE
0.5ms
10V
TRACE 1
ONSET OF OUTPUT
SHORT-CIRCUIT
TRACE 2
FAST CURRENT
LIMIT
TRACE 3
ANALOG
CURRENT LIMIT
TIMER
0.5ms
5V
CTIMER RAMP
LATCH OFF
TRACE 4
4253 F05
Figure 5. Output Short-Circuit Behavior of LTC4253
425353afe
19
LTC4253/LTC4253A
APPLICATIONS INFORMATION
MOSFET SELECTION
The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until
TIMER times out. These considerations take precedence
over DC current ratings. A MOSFET with adequate SOA for
a given application can always handle the required current
but the opposite may not be true. Consult the manufacturer’s
MOSFET data sheet for safe operating area and effective
transient thermal impedance curves.
MOSFET selection is a 3-step process by assuming the
absence of soft-start capacitor. First, RS is calculated and
then the time required to charge the load capacitance is
determined. This timing, along with the maximum shortcircuit current and maximum input voltage, defines an
operating point that is checked against the MOSFET’s
SOA curve.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at VSUPPLY(MIN).
RS is given by:
VCB(MIN)
(8)
RS =
IL(MAX)
where VCB(MIN) = 40mV (45mV for the LTC4253A) represents the guaranteed minimum circuit breaker threshold.
During the initial charging process, the LTC4253/LTC4253A
may operate the MOSFET in current limit, forcing (VACL)
between 80mV to 120mV (VACL is 54mV to 66mV for the
LTC4253A) across RS. The minimum inrush current is
given by:
VACL(MIN)
IINRUSH(MIN) =
(9)
RS
Maximum short-circuit current limit is calculated using
the maximum VSENSE. This gives
ISHORTCIRCUIT(MAX) =
VACL(MAX)
RS
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
for CT is calculated based on the maximum time it takes
the load capacitor to charge. That time is given by:
tCL(CHARGE) =
C • V CL • VSUPPLY(MAX)
=
I
IINRUSH(MIN)
(11)
The maximum current flowing in the DRAIN pin is given by:
IDRN(MAX) =
VSUPPLY(MAX) − VDRNCL
RD
(12)
Approximating a linear charging rate, IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3)
can be approximated with 0.5 • IDRN(MAX). Rearranging
the equation, TIMER capacitor CT is given by:
CT =
tCL(CHARGE) • (200μA + 4 •IDRN(MAX) )
4V
(13)
Returning to Equation (3), the TIMER period is calculated and used in conjunction with VSUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET.
As a numerical design example for the LTC4253, consider
a 30W load, which requires 1A input current at 36V. If
VSUPPLY(MAX) = 72V and CL = 100μF, RD = 1MΩ, Equation
(8) gives RS = 40mΩ; Equation (13) gives CT = 414nF.
To account for errors in RS, CT, TIMER current (200μA),
TIMER threshold (4V), RD, DRAIN current multiplier and
DRAIN voltage clamp (VDRNCL), the calculated value should
be multiplied by 1.5, giving the nearest standard value of
CT = 680nF.
If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A
will flow in the MOSFET for 6.3ms as dictated by CT = 680nF
in Equation (3). The MOSFET must be selected based on
this criterion. The IRF530S can handle 100V and 3A for
10ms and is safe to use in this application.
(10)
425353afe
20
LTC4253/LTC4253A
APPLICATIONS INFORMATION
where VCB(MAX) is 60mV (55mV for the LTC4253A).
From the SOA curves of a prospective MOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
t SOA(MAX)
CSS =
for the LTC4253
0.916 • RSS
(15)
t SOA(MAX)
CSS =
for the LTC4253A
2.48 • RSS
In the above example, 60mV/40mΩ gives 1.5A. tSOA for
the IRF530S is 40ms. From Equation (15), CSS = 437nF.
Actual board evaluation showed that CSS = 100nF was appropriate. The ratio ( RSS • CSS ) to tCL(CHARGE) is a good
gauge as large ratios may result in the time-out period
expiring prematurely. This gauge is determined empirically
with board level evaluation.
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 3 for the LTC4253A. It was designed for
80W and CL = 100μF.
Calculate maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, IIN(MAX) = 2.2A.
Calculate RS: from Equation (8) RS = 20mΩ.
Calculate I SHORT-CIRCUIT(MAX) : from Equation (10)
ISHORTCIRCUIT(MAX) = 3.3A.
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate CT: from Equation (13) CT = 302nF. Select
CT = 680nF, which gives the circuit breaker time-out
period tMAX = 5.9ms.
Consult MOSFET SOA curves: the IRF530S can handle 3.3A
at 100V for 8.3ms, so it is safe to use in this application.
Calculate CSS: using Equations (14) and (15) select
CSS = 33nF.
FREQUENCY COMPENSATION
The LTC4253 typical frequency compensation network
for the analog current limit loop is a series RC (10Ω)
and CC connected from GATE to VEE. Figure 6 depicts the
relationship between the compensation capacitor CC and
the MOSFET’s CISS. The line in Figure 6 is used to select
a starting value for CC based upon the MOSFET’s CISS
specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value
of CC versus the starting value are small. Nevertheless,
compensation values should be verified by board level
short-circuit testing.
As seen in Figure 5, at the onset of a short-circuit event,
the input supply voltage can ring dramatically due to series
inductance. If this voltage avalanches the MOSFET, current
continues to flow through the MOSFET to the output. The
analog current limit loop cannot control this current flow
and therefore the loop undershoots. This effect cannot be
eliminated by frequency compensation. A Zener diode is
required to clamp the input supply voltage and prevent
MOSFET avalanche.
60
COMPENSATION CAPACITOR CC (nF)
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overconservative but simple approach begins with the
maximum circuit breaker current, given by:
VCB(MAX)
ICB(MAX) =
(14)
RS
NTY100N10
50
40
IRF3710
30
20
IRF540
IRF530
IRF740
10
0
0
2000
6000
4000
MOSFET CISS (pF)
8000
4253 F06
Figure 6. Recommended Compensation
Capacitor CC vs MOSFET CISS for the LTC4253
425353afe
21
LTC4253/LTC4253A
APPLICATIONS INFORMATION
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4253/
LTC4253A’s VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way
of making connections between the LTC4253/LTC4253A
and the sense resistor. PCB layout should be balanced
and symmetrical to minimize wiring errors. In addition,
the PCB layout for the sense resistor should include good
thermal management techniques for optimal sense resistor
power dissipation.
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4253 F07
TO
SENSE
TO
VEE
Figure 7. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
VOUT and DRAIN. VIN and the PWRGD signals follow at
a slower rate as set by the VIN bypass capacitor. At time
point 2, VIN exceeds VLKO and the internal logic checks for
UV > VUVHI (VUV for the LTC4253A), OV < VOVLO (VOV –
VOVHST for the LTC4253A), RESET < 0.8V, GATE < VGATEL,
SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When
all conditions are met, initial timing starts and the TIMER
capacitor is charged by a 5μA current source pull-up. At
time point 3, TIMER reaches the VTMRH threshold and
the initial timing cycle terminates. The TIMER capacitor
is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL,
SENSE < VCB and SS < 20 • VOS must be satisfied before
the GATE start-up cycle begins. SS ramps up as dictated
by RSS • CSS (as in Equation 6); GATE is held low by the
analog current limit (ACL) amplifier until SS crosses 20 •
VOS. Upon releasing GATE, 50μA sources into the external
MOSFET gate and compensation network. When the GATE
voltage reaches the MOSFET’s threshold, current flows
into the load capacitor at time point 5. At time point 6,
load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the
GATE voltage is servoed, the SENSE voltage is regulated
at VACL(t) (Equation 7) and soft-start limits the slew rate
of the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, circuit breaker
TIMER activates. The TIMER capacitor, CT, is charged by
a (200μA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At
time point 8, the load current falls and the SENSE voltage
drops below VACL(t). The analog current limit loop shuts
off and the GATE pin ramps further. At time point 9, the
SENSE voltage drops below VCB, the fault TIMER ends,
followed by a 5μA discharge cycle (cool-off). The duration
between time points 7 and 9 must be shorter than one
circuit breaker delay to avoid fault time-out during GATE
ramp-up. When GATE ramps past the VGATEH threshold
at time point A, PWRGD1 pulls low. At time point B, GATE
reaches its maximum voltage as determined by VIN. At time
point A, SQTIMER starts its ramp-up to 4V. Having satisfied the requirement that PWRGD1 is low for more than
one tSQT, PWRGD2 pulls low after EN2 pulls high above
the VIH threshold at time point C. This sets off the second
SQTIMER ramp-up. Having satisfied the requirement that
PWRGD2 is low for more than one tSQT, PWRGD3 pulls
low after EN3 pulls high at time point D.
425353afe
22
LTC4253/LTC4253A
APPLICATIONS INFORMATION
VIN CLEARS VLKO, CHECK UV > VUVHI (VUV FOR THE LTC4253A), OV < VOVLO (VOV – VOVHST FOR THE LTC4253A),
RESET < 0.8V, GATE < VGATEL, SENSE < VCB44t7OS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB"/%44t7OS
1 2
3 4 56
7 89 A B
C
D
GND – VEE OR
(–48RTN) – (–48V)
UV/OV
VIN
VLKO
VTMRH
˜"t*DRN
5μA
TIMER
5μA
VTMRL
50μA
GATE
SS
VIN – VGATEH
50μA
VGATEL
5μA
t7ACL + VOS)
t7CB + VOS)
t7OS
VACL
SENSE
VCB
VOUT
VDRNCL
DRAIN
VDRNL
50μA
PWRGD1
PWRGD2
PWRGD3
VSQTMRH
5μA
SQTIMER
VSQTMRH
5μA
VIH
EN2
VIH
EN3
INITIAL TIMING
GATE
START-UP
4253 F08
Figure 8. System Power-Up Timing (All Waveforms Are Referenced to VEE)
425353afe
23
LTC4253/LTC4253A
APPLICATIONS INFORMATION
Live Insertion with Short Pin Control of UV/OV
connections are firmly established before the LTC4253/
LTC4253A are activated. At time point 1, the power pins
make contact and VIN ramps through VLKO. At time point 2,
the UV/OV divider makes contact and its voltage exceeds
In the example shown in Figure 9, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
UV CLEARS VUVHI (VUV FOR THE LTC4253A), CHECK OV < VOVHI (VOV FOR THE LTC4253A), RESET < 0.8V, GATE < VGATEL,
SENSE < VCB44t7OS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB"/%44t7OS
1
2
3 456
7
89 A B
C
D
GND – VEE OR
(–48RTN) – (–48V)
UV/OV
VUVHI
VIN
VLKO
VTMRH
˜"t*DRN
5μA
TIMER
5μA
VTMRL
50μA
GATE
SS
50μA
VGATEL
5μA
VIN – VGATEH
t7ACL + VOS)
t7CB + VOS)
t7OS
VACL
VCB
SENSE
VOUT
VDRNCL
DRAIN
VDRNL
50μA
PWRGD1
PWRGD2
PWRGD3
VSQTMRH
5μA
SQTIMER
5μA
VSQTMRL
VSQTMRH
VSQTMRL
EN2
EN3
INITIAL TIMING
GATE
START-UP
4253 F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)
425353afe
24
LTC4253/LTC4253A
APPLICATIONS INFORMATION
VUVHI (VUV for the LTC4253A). In addition, the internal logic
checks for OV < VOVHI (VOV for the LTC4253A), RESET <
0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and
TIMER < VTMRL. When all conditions are met, initial timing
starts and the TIMER capacitor is charged by a 5μA current
source pull-up. At time point 3, TIMER reaches the VTMRH
threshold and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point 4, the VTMRL
threshold is reached and the conditions of GATE < VGATEL,
SENSE < VCB and SS < 20 • VOS must be satisfied before
the GATE start-up cycle begins. SS ramps up as dictated
by RSS • CSS; GATE is held low by the analog current
limit amplifier until SS crosses 20 • VOS. Upon releasing
GATE, 50μA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed and the SENSE voltage is regulated at VACL(t)
and soft-start limits the slew rate of the load current. If the
SENSE voltage (VSENSE – VEE) reaches the VCB threshold
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, CT is charged by a (200μA + 8 • IDRN)
current pull-up. As the load capacitor nears full charge,
load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below VCB and the fault TIMER ends, followed by a 5μA
discharge current source (cool-off). When GATE ramps
past VGATEH threshold at time point A, PWRGD1 pulls low,
starting off the PWRGD sequence. PWRGD2 pulls low at
time point C when EN2 is high and PWRGD1 is low for
more than one tSQT. PWRGD3 pulls low at time point D
when EN2 and EN3 is high and PWRGD2 is low for more
than one tSQT. At time point B, GATE reaches its maximum
voltage as determined by VIN.
Undervoltage Timing
In Figure 10 when the UV pin drops below VUVLO (VUV –
VUVHST for the LTC4253A) at time point 1, the LTC4253/
LTC4253A shut down with TIMER, SS and GATE pulled
low. If current has been flowing, the SENSE pin voltage
decreases to zero as GATE collapses. When UV recovers
and clears VUVHI (VUV for the LTC4253A) at time point 2,
an initial time cycle begins followed by a start-up cycle.
VIN Undervoltage Lockout Timing
VIN undervoltage lockout comparator, UVLO has a similar
timing behavior as the UV pin timing except it looks at
VIN < (VLKO – VLKH) to shut down and VIN > VLKO to start.
In an undervoltage lockout condition, both UV and OV
comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI
(VOV for the LTC4253A) as shown at time point 1 of Figure 11, the TIMER and PWRGD status are unaffected; SS
and GATE pull down; load disconnects. At time point 2,
OV recovers and drops below the VOVLO (VOV – VOVHST
for the LTC4253A) threshold; GATE start-up begins. If
the overvoltage glitch is long enough to deplete the load
capacitor, time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 12a, the TIMER capacitor charges at 200μA if
the SENSE pin exceeds VCB but VDRN is less than 5V. If
the SENSE pin returns below VCB before TIMER reaches
the VTMRH threshold, TIMER is discharged by 5μA. In
Figure 12b, when TIMER exceeds VTMRH, GATE pulls
down immediately and the chip shuts down. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach VTMRH followed by GATE pull down
and the chip shuts down. During chip shutdown, the
LTC4253/LTC4253A latch TIMER high with a 5μA pull-up
current source.
425353afe
25
LTC4253/LTC4253A
APPLICATIONS INFORMATION
UV DROPS BELOW VUVLO (VUV – VUVHST FOR THE LTC4253A). GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UV CLEARS VUVHI (VUV FOR THE LTC4253A), CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB44t7OS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB"/%44t7OS
1
UV
2
VUVLO
3 4 56
89 A B
C
VTMRH
˜"t*DRN
5μA
VTMRL
5μA
50μA
GATE
SS
D
VUVHI
5μA
TIMER
7
VIN – VGATEH
50μA
VGATEL
t7ACL + VOS)
t7CB + VOS)
t7OS
VACL
SENSE
VCB
VDRNCL
DRAIN
VDRNL
50μA
PWRGD1
PWRGD2
PWRGD3
VSQTMRH
5μA
SQTIMER
VSQTMRL
5μA
VSQTMRH
VSQTMRL
EN2
EN3
INITIAL TIMING
GATE
START-UP
4253 F10
Figure 10. Undervoltage Timing (All Waveforms Are Referenced to VEE)
425353afe
26
LTC4253/LTC4253A
APPLICATIONS INFORMATION
OV OVERSHOOTS VOVHI (VOV FOR THE LTC4253A). GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED
OV DROPS BELOW VOVLO (VOV – VOVHST FOR THE LTC4253A), CHECK GATE < VGATEL, SENSE < VCB"/%44t7OS
1
2 34
VOVHI
OV
5
67 8 9
VOVLO
VTMRH
˜"t*DRN
TIMER
5μA
5μA
50μA
GATE
VGATEL
VIN – VGATEH
50μA
t7ACL + VOS)
t7CB + VOS)
SS
t7OS
VACL
VCB
SENSE
GATE
START-UP
4253 F11
Figure 11. Overvoltage Timing (All Waveforms Are Referenced to VEE)
CB TIMES-OUT
1
2
VTMRH
˜"t*DRN
TIMER
5μA
1
VTMRH
˜"t*DRN
TIMER
CB TIMES-OUT
2
1
2
3
VTMRH
˜"t*DRN
TIMER
5μA
GATE
GATE
GATE
SS
SS
SS
SENSE
VACL
VACL
VCB
VCB
SENSE
VACL
VCB
SENSE
VOUT
VOUT
DRAIN
DRAIN
VOUT
DRAIN
PWRGD1
PWRGD1
PWRGD1
VDRNCL
CB FAULT
VDRNCL
CB FAULT
(12a) Momentary Circuit Breaker Fault
4
(12b) Circuit Breaker Time-Out
CB FAULT
CB FAULT
4253 F12
(12c) Multiple Circuit Breaker Fault
Figure 12. Circuit Breaker Timing Behavior (All Waveforms Are Referenced to VEE)
425353afe
27
LTC4253/LTC4253A
APPLICATIONS INFORMATION
Resetting a Fault Latch
A latched circuit breaker fault of the LTC4253/LTC4253A
has the benefit of a long cooling time. The latched fault can
be reset by pulsing the RESET pin high until the TIMER pin
is pulled below VTMRL(1V) as shown in Figure 13b. After
the RESET pulse, SS and GATE ramp up without an initial
timing cycle provided the interlock conditions are satisfied.
Alternative methods of reset include using an external
switch to pulse the UV pin below VUVLO (VUV – VUVHST
for the LTC4253A) or the VIN pin below (VLKO – VLKH).
Pulling the TIMER pin below VTMRL and the SS pin to 0V
then simultaneously releasing them also achieves a reset.
An initial timing cycle is generated for reset by pulsing the
UV pin or VIN pin, while no initial timing cycle is generated
for reset by pulsing of the TIMER and SS pins.
Using Reset as an ON/OFF Switch
The asynchronous RESET pin can be used as an ON/OFF
function to cut off supply to the external power modules
or loads controlled by the LTC4253/LTC4253A. Pulling
RESET high will pull GATE, SS, TIMER and SQTIMER
low and the PWRGD signal high. The supply is fully cut
off if the RESET pulse is maintained wide enough to fully
discharge the GATE and SS pins. As long as RESET is
high, GATE, SS, TIMER and SQTIMER are strapped to VEE
and the supply is cut off. When RESET is released, if the
LTC4253/LTC4253A are in UVLO, UV, OV or VSENSE > VCB,
turn-on is delayed until the interlock conditions are met
before recovering as described in the Operation, Interlock
Conditions section. If not, the GATE pin will ramp up in a
soft start cycle without going through an initial cycle as
in Figure 13c.
Analog Current Limit and Fast Current Limit
In Figure 14a, when SENSE exceeds VACL, GATE is regulated
by the analog current limit amplifier loop. When SENSE
drops below VACL, GATE is allowed to pull up. In Figure 14b,
when a severe fault occurs, SENSE exceeds VFCL and GATE
immediately pulls down until the analog current amplifier
establishes control. If the severe fault causes VOUT to exceed
VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows
into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 200μA. This
accelerated TIMER current of (200μA + 8 • IDRN) produces
a shorter circuit breaker fault delay. Careful selection of
CT, RD and MOSFET helps prevent SOA damage in a low
impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 300μs (0V to 1.4V
in about 200μs for the LTC4253A) at GATE start-up, as
shown in Figure 15a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation 6), as
shown in Figure 15b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from VTMRH to VTMRL
(time points 1 and 2), by the OV pin falling below the VOVLO
(VOV – VOVHST for the LTC4253A) threshold after an OV
condition or by the RESET pin falling < 0.8V after a Reset
condition. When the SS pin is below 0.2V, the analog current limit amplifier keeps GATE low. Above 0.2V, GATE is
released and 50μA ramps up the compensation network
and GATE capacitance at time point 4. Meanwhile, the SS
pin voltage continues to ramp up. When GATE reaches
the MOSFET’s threshold, the MOSFET begins to conduct.
Due to the MOSFET’s high gm, the MOSFET current quickly
reaches the soft-start control value of VACL(t) (Equation 7).
At time point 6, the GATE voltage is controlled by the current
limit amplifier. The soft-start control voltage reaches the
circuit breaker voltage, VCB at time point 7 and the circuit
breaker TIMER activates. As the load capacitor nears full
charge, load current begins to decline below VACL(t). The
current limit loop shuts off and GATE releases at time
point 8. At time point 9, SENSE voltage falls below VCB
and TIMER deactivates.
Large values of CSS can cause premature circuit breaker
time-out as VACL(t) may marginally exceed the VCB potential
during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A
more serious side effect of a large CSS value is that SOA
duration may be exceeded during soft-start into a low
impedance load. A soft-start voltage below VCB will not
activate the circuit breaker TIMER.
425353afe
28
50μA
VIL
67 8 9
50μA
˜"t*DRN
5
VIN – VGATEH
5μA
5μA
SS
GATE
TIMER
DRAIN
RESET
VIL
(13a) Reset Forcing Start-Up without
Initial TIMER Cycle
VUVHI
RESET PULSE
WIDTH MUST FULLY
DISCHARGE TIMER
VIH
VUVHI
RESET
UV/OV
Figure 13. Reset Functions (All Waveforms Are Referenced to VEE)
(13b) Reset of the LTC4253/LTC4253A’s Latched Fault
RESET
UV/OV
VIN
VLKO
50μA
VDRNCL
VDRNL
VIN
VLKO
DRAIN
SENSE
VIN
VDRNL
VDRNCL
VCB
VCB
SENSE
VACL
VACL
t7OS
PWRGD1
50μA
t7OS
PWRGD1
UV/OV
1
VGATEL
VTMRL
50μA
VIL
50μA
67 8 9
VDRNL
VDRNCL
VCB
VACL
VIN – VGATEH
5μA
(13c) Reset as an ON/OFF Switch
RESET PULSE
WIDTH MUST FULLY
DISCHARGE GATE AND SS
VIH
VUVHI
VLKO
50μA
t7OS
5
˜"t*DRN
2 34
t7CB + VOS)
VGATEL
VTMRL
2 34
t7ACL + VOS)
SS
GATE
TIMER
VTMRH
t7CB + VOS)
5μA
1
t7ACL + VOS)
VIN – VGATEH
5μA
5μA
RESET < VIL, CHECK UVLO, UV, OV CONDITION, VSENSE < VCB
t7CB + VOS)
50μA
50μA
˜"t*DRN
56 7 8
RESET < VIL, CHECK UVLO, UV, OV CONDITION, GATE < VGATEL,
SENSE < VCB44t7OS AND TIMER < VTMRL
t7ACL + VOS)
VGATEL
VTMRL
4
LATCHED TIMER RESET BY
RESET PULLING HIGH
PWRGD1
DRAIN
SENSE
SS
GATE
TIMER
1 23
RESET < VIL, CHECK UVLO, UV, OV CONDITION, GATE < VGATEL,
SENSE < VCB44t7OS AND TIMER < VTMRL
4253 F13
5μA
LTC4253/LTC4253A
APPLICATIONS INFORMATION
425353afe
29
LTC4253/LTC4253A
APPLICATIONS INFORMATION
CB TIMES-OUT
12
34
1
VTMRH
˜"t*DRN
TIMER
2
VTMRH
˜"t*DRN
TIMER
5μA
GATE
GATE
SS
VACL
SENSE
VFCL
SENSE
VCB
VACL
VCB
VOUT
VOUT
VDRNCL
DRAIN
DRAIN
PWRGD1
PWRGD1
4253 F14
(14a) Analog Current Limit Fault
(14b) Fast Current Limit Fault
Figure 14. Current Limit Behavior (All Waveforms Are Referenced to VEE)
END OF INITIAL TIMING CYCLE
12 3 4 5 6 7
7a
END OF INITIAL TIMING CYCLE
8 9
10
11
12 3 4 5 6
VTMRH
5μA
˜"t*DRN
TIMER
7
8 9
VTMRL
50μA
GATE
50μA
VIN – VGATEH
GATE
VIN – VGATEH
VGS(th)
50μA
t7ACL + VOS)
SS
11
5μA
˜"t*DRN
TIMER
VTMRL
VGS(th)
10
VTMRH
50μA
t7ACL + VOS)
SS
t7CB + VOS)
t7OS
t7CB + VOS)
t7OS
VACL
SENSE
VCB
VACL
SENSE
VCB
VDRNCL
DRAIN
VDRNL
VDRNCL
DRAIN
VDRNL
50μA
PWRGD1
50μA
PWRGD1
4253 F15
(15a) Without External CSS
(15b) With External CSS
Figure 15. Soft-Start Timing (All Waveforms Are Referenced to VEE)
425353afe
30
LTC4253/LTC4253A
APPLICATIONS INFORMATION
Power Limit Circuit Breaker
Figure 16 shows the LTC4253A in a power limit circuit
breaking application. The SENSE pin is modulated by board
voltage VSUPPLY. The D1 Zener voltage, VZ, is set to be the
same as the lowest operating voltage, VSUPPLY(MIN) = 43V.
If the goal is to have the high supply operating voltage,
VSUPPLY(MAX) = 71V give the same power as available at
VSUPPLY(MIN), then resistors R3 and R4 are selected by:
VCB
R4
=
R3 VSUPPLY(MAX)
(16)
RIN
2.5k
15k(1/4W)/6
– 48V RTN
(LONG PIN)
VIN
CIN
1μF
DIN††
DDZ13B*
SUPPLY(MIN) + VSUPPLY(MAX)
2
(17)
•POWER AT VSUPPLY(MIN)
= 1.064 • POWER AT VSUPPLY(MIN)
when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX))
= 57V
R3
31.6k
C2
100μF
R5
5.6k
)
4 • VSUPPLY(MIN) • VSUPPLY(MAX)
R6
5.6k
+
C3
0.1μF
R7
5.6k
POWER
MODULE 1
POWER
MODULE 2
D1
BZV85C43
EN
POWER
MODULE 3
EN
VIN
R2
392k
1%
†
†
†
LTC4253A
RESET
(LONG PIN)
OV
PWRGD1
UV
PWRGD2
RESET
PWRGD3
C1
10nF
CSS 33nF
EN2
SS
CSQ
0.1μF
EN2
VIN
RD 1M
R9
DRAIN
TIMER
GATE
Q1
IRF530S
VIN
RS
0.02Ω
†
R8
SENSE
VEE
CT
0.68μF
POWER
MODULE 2
OUTPUT
EN3
EN3
SQTIMER
– 48V
(LONG PIN)
(V
POWER(MAX) =
EN
– 48V RTN
(SHORT PIN)
R1
30.1k
1%
If R4 is 22Ω, then R3 is 31.6k. The peak circuit breaker
power limit is:
R4
22
RC
10Ω
POWER
MODULE 1
OUTPUT
†
4253 F16
CC
10nF
*DIODES, INC.
Figure 16. Power Limit Circuit Breaker Application
†MOC207
††
RECOMMENDED FOR HARSH ENVIRONMENTS.
425353afe
31
LTC4253/LTC4253A
APPLICATIONS INFORMATION
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWER(FAULT) =
( VSUPPLY ) • ⎡ V
RS
⎢
⎣
ACL
− (VSUPPLY − VZ ) •
R4 ⎤
R3 ⎥⎦
(18)
Circuit Breaker with Foldback Current Limit
Figure 17 shows the LTC4253A in a foldback current limit
application. When VOUT is shorted to the –48V RTN supply,
current flows through resistors R3 and R4. This results in
a voltage drop across R4 and a corresponding reduction
in voltage drop across the sense resistor, RS, as the ACL
amplifier servos the sense voltage between the SENSE and
VEE pins to about 60mV. The short-circuit current through
RS reduces as the VOUT voltage increases during an output
short-circuit condition. Without foldback current limiting
resistor R4, the current is limited to 3A during analog
current limit. With R4, the short-circuit current is limited
to 0.5A when VOUT is shorted to 71V.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
w 45s
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
425353afe
32
LTC4253/LTC4253A
REVISION HISTORY
REV
DATE
DESCRIPTION
D
2/11
Obsoleted LTC4253A
(Revision history begins at Rev D)
PAGE NUMBER
Revised Application drawings
E
3/12
2
12, 14, 15, 21,
25 to 32, 34
Replaced Shunt Regulator section
14
Not recommended for new designs
1
425353afe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC4253/LTC4253A
TYPICAL APPLICATION
+
RIN
10k
20k(1/4W)/2
– 48V RTN
(LONG PIN)
VIN
CIN
1μF
– 48V RTN
(SHORT PIN)
R6
100k
R7
100k
C3
0.1μF
POWER
MODULE 1
EN
VIN EN2 EN3
R2
392k
1%
RESET
(LONG PIN)
OV
PWRGD1
UV
PWRGD2
RESET
PWRGD3
C1
10nF
DIN††
DDZ13B*
LTC4253A
CSQ
0.1μF
†
RD
3.3M
4253 F17
VOUT
TIMER
Q1
IRF530S
GATE
SENSE
VEE
CT
1μF
– 48V
(LONG PIN)
EN
†
R3
38.3k
SQTIMER
POWER
MODULE 3
†
SS
R8
47k
POWER
MODULE 2
EN
DRAIN
CSS 33nF
R1
30.1k
1%
R5
100k
C2
100μF
R4
22Ω
RC
10Ω
CC
10nF
RS
0.02Ω
*DIODES, INC.
†FMMT493
††RECOMMENDED FOR HARSH ENVIRONMENTS.
Figure 17. –48V/2.5A Application with Foldback Current Limiting and Transistor Enabled Sequencing without Feedback
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640AH/LT1640AL
Negative High Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
LT1641-1/LT1641-2
Positive High Voltage Hot Swap Controllers in SO-8
Supplies from 9V to 80V, Autoretry/Latched Off
LTC1642A
Fault Protected Hot Swap Controller
3V to 16.5V, Overvoltage Protection up to 33V
LT4250
–48V Hot Swap Controller
Active Current Limiting, Supplies from –20V to –80V
LTC4251/LTC4251-1/
LTC4251-2
–48V Hot Swap Controllers in SOT-23
Fast Active Current Limiting, Supplies from –15V
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
–48V Hot Swap Controllers in MS8/MS10
Fast Active Current Limiting, Supplies from –15V, Drain
Accelerated Response, 1% Accurate UV/OV Thresholds
425353afe
34 Linear Technology Corporation
LT 0312 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002