Preliminary Revised November 1999 74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs (Preliminary) General Description Features The LVTH652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. (See Functional Description). ■ Input and output interface capability to systems at 5V VCC The LVTH652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Outputs source/sink −32 mA/+64 mA This bus/octal buffer and line driver is designed for lowvoltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH652 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Latch-up performance exceeds 500 mA ■ Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Functionally compatible with the 74 series 652 Ordering Code: Order Number Package Number 74LVTH652WM M24B 74LVTH652MTC MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS012018 www.fairchildsemi.com 74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs (Preliminary) November 1999 74LVTH652 Preliminary Pin Descriptions Pin Names A0–A7 Connection Diagram Description Data Register A Inputs/ 3-STATE Outputs B0–B7 Data Register B Inputs/ CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs 3-STATE Outputs Truth Table (Note 1) Inputs OEAB OEBA Inputs/Outputs CPAB CPBA SAB SBA L H H or L H or L X X L H N N X X A0 thru A7 Input B0 thru B7 Input Operating Mode Isolation Store A and B Data X H N H or L X X Input Not Specified Store A, Hold B H H N N X X Input Output Store A in Both Registers L X H or L N X X Not Specified Input Hold A, Store B L L N N X X Output Input Store B in Both Registers L L X X X L Output Input L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Real-Time B Data to A Bus Store B Data to A Bus Input Output Real-Time A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus Stored A Data to B Bus N = LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Preliminary Data on the A or B data bus, or both can be stored in the internal D-type flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the LVTH652. Real-Time Transfer Bus A to Bus B Real-Time Transfer Bus B to Bus A OEAB L OEBA L CPAB CPBA X X SAB X SBA OEAB OEBA CPAB CPBA SAB SBA L H H X X L X Transfer Storage Data to A or B Storage OEAB OEBA CPAB CPBA SAB SBA X H N X X X OEAB OEBA CPAB CPBA SAB SBA L X X N X X H L H or L H or L H H L H N N X X 3 www.fairchildsemi.com 74LVTH652 Functional Description 74LVTH652 Preliminary Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V HIGH Level Output Current −32 mA LOW Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 4 Preliminary Symbol TA =−40°C to +85°C VCC Parameter (V) Min Units Max −1.2 VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 II(HOLD) II(OD) Output LOW Voltage Bushold Input Minimum Drive IOFF Power OFF Leakage Current Power Up/Down 3-STATE VO ≤ 0.1V or VO ≥ VCC − 0.1V V IOH = −32 mA V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 3.0 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 4) −500 µA (Note 5) 3.6 10 µA VI = 5.5V Control Pins 3.6 ±1 µA VI = 0V or VCC Data Pins 3.6 −5 µA VI = 0V 1 µA VI = VCC 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 0–1.5V ±100 µA −5 µA VO = 0.0V VO = 3.6V Input Current IPU/PD V 0.8 0.2 Current to Change State II 2.0 2.7 3.0 Bushold Input Over-Drive V Conditions Input Clamp Diode Voltage VOL 2.7 II = −18 mA VIK Output Current VO = 0.5V to 3.0V VI = GND or VCC IOZL 3-STATE Output Leakage Current 3.6 IOZH 3-STATE Output Leakage Current 3.6 5 µA IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ V O ≤ 5.5V ∆ICC Increase in Power Supply Current Outputs Disabled 3.6 (Note 6) 0.2 mA One Input at VCC − 0.6V Other Inputs at VCC or GND Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 7) TA = 25°C VCC (V) Min Typ Conditions Max Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVTH652 DC Electrical Characteristics 74LVTH652 Preliminary AC Electrical Characteristics TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3V ± 0.3V Min fMAX Maximum Clock Frequency 150 tPLH Propagation Delay Data to Output 1.8 Max VCC = 2.7V Min Max 150 4.7 1.8 MHz 5.6 tPHL Clock to A or B 1.8 4.7 1.8 5.6 tPLH Propagation Delay Data to Output 1.3 3.5 1.3 4.1 tPHL Data to A or B 1.3 3.5 1.3 4.1 tPLH Propagation Delay Data to Output 1.5 4.9 1.5 6.0 tPHL SBA or SAB to A or B 1.5 4.9 1.5 6.0 tPZH Output Enable Time 1.1 5.2 1.1 6.5 tPZL OE to A or B 1.1 5.2 1.1 6.5 tPHZ Output Disable Time 2.3 5.5 2.3 6.1 tPLZ OE to A or B 2.3 5.5 2.3 5.9 tPZH Output Enable Time 1.3 4.7 1.3 5.7 tPZL OE to A or B 1.3 4.7 1.3 5.7 tPHZ Output Disable Time 1.5 5.6 1.5 6.7 tPLZ OE to A or B 1.5 5.6 1.5 6.3 tW Pulse Duration tS Setup Time tH Hold Time Capacitance Symbol Units Clock HIGH or LOW 3.3 3.3 Data HIGH or LOW before CP 1.2 1.5 CLR HIGH before CP 1.6 2.2 Data HIGH or LOW after CP 0.8 0.8 ns ns ns ns ns ns ns ns ns ns (Note 9) Typical Units CIN Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 9: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 6 Preliminary 74LVTH652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead (0.300’ Wide) Molded Small Outline Package, SOIC JEDEC Package Number M24B 7 www.fairchildsemi.com 74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs (Preliminary) Preliminary Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Molded Small Outline Package, TSSOP JEDEC Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8