Revised April 1999 74LCX652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs General Description Features The LCX652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. ■ 5V tolerant inputs and outputs The LCX652 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V − 3.6V VCC specifications provided ■ 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX652WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LCX652MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LCX652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS011998.prf Description A0–A7, B0–B7 A and B Inputs/3-STATE Outputs CPAB, CPBA Clock Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs www.fairchildsemi.com 74LCX652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs February 1994 74LCX652 Logic Symbols IEEE/IEC Truth Table (Note 2) Inputs OEAB OEBA L H L H X H H H L X L L Inputs/Outputs CPAB CPBA H or L H or L H or L H or L SAB SBA A0 thru A7 X X X X X X Input Not Specified X X Input Output Store A in Both Registers X X Not Specified Input Hold A, Store B X X Output Input Store B in Both Registers Output Input L L X X X L L L X H or L X H H H X X L X H H H or L X H X H L H or L H or L H H Input Operating Mode B0 thru B7 Input Isolation Store A and B Data Store A, Hold B Real-Time B Data to A Bus Store B Data to A Bus Input Output Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 2: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. www.fairchildsemi.com 2 Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceiver and receiver. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OEAB OEBA CPAB CPBA SAB SBA L L X X X OEAB OEBA CPAB CPBA SAB SBA L H H Transfer Storage Data to A or B L H or L H or L X L X Storage OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA H X H H 3 X H L X L H X X X X X X X X www.fairchildsemi.com 74LCX652 Functional Description 74LCX652 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Symbol Parameter Value Conditions VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL (Note 5) Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused inputs or I/Os must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol Parameter Conditions VCC (V) VIH VIL VOH VOL HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA TA = −40°C to +85°C Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 V 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 0.55 IOL = 24 mA 3.0 Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 0 10 VI = V IH or VIL Power-Off Leakage Current VI or VO = 5.5V 5 V VCC − 0.2 IOH = −8 mA II IOFF Units Max V µA µA µA www.fairchildsemi.com 74LCX652 Absolute Maximum Ratings(Note 3) 74LCX652 DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input TA = −40°C to +85°C Min Units Max VI = VCC or GND 2.3 − 3.6 10 3.6V ≤ VI, VO ≤ 5.5V (Note 6) 2.3 − 3.6 ±10 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 6: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C; RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min fMAX Maximum Clock Frequency 150 tPHL Propagation Delay 1.5 Max Min Max Min Max 7.0 1.5 8.0 1.5 8.4 Units MHz tPLH Bus to Bus 1.5 7.0 1.5 8.0 1.5 8.4 tPHL Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5 ns ns tPLH Clock to Bus 1.5 8.5 1.5 9.5 1.5 10.5 tPHL Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5 tPLH Select to Bus 1.5 8.5 1.5 9.5 1.5 10.5 tPZL Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 1.5 8.5 1.5 9.5 1.5 10.5 Output Disable Time 1.5 8.5 1.5 9.5 1.5 10.5 1.5 8.5 1.5 9.5 1.5 10.5 tS Setup Time 2.5 2.5 4.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.3 3.3 4.0 ns tOSHL Output to Output Skew (Note 7) tPZH tPLZ tPHZ 1.0 tOSLH ns ns ns ns 1.0 Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions VCC (V) TA = 25°C Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF www.fairchildsemi.com Conditions 6 74LCX652 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 7 www.fairchildsemi.com 74LCX652 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 8 74LCX652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 9 www.fairchildsemi.com 74LCX652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.