FAIRCHILD HUFA75639S3ST

HUFA75639S3ST_F085A
Data Sheet
March 2012
56A, 100V, 0.025 Ohm, N-Channel
UltraFET Power MOSFETs
Features
• 56A, 100V
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable
and battery-operated products.
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
HUFA75639S3ST_F085A
PACKAGE
BRAND
TO263AB
75639S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75639S3ST.
S
Packaging
DRAIN
(FLANGE)
GATE
SOURCE
JEDEC TO-263AB
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2012 Fairchild Semiconductor Corporation
HUFA75639S3ST_F085A Rev. C1
HUFA75639S3ST_F085A
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
100
100
±20
56
Figure 4
Figures 6, 14, 15
200
1.35
-55 to 175
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 56A, VGS = 10V (Figure 9)
-
0.021
0.025
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
0.74
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-247
-
-
30
oC/W
TO-220, TO-263
-
-
62
oC/W
VDD = 50V, ID ≅ 56A,
RL = 0.89Ω, VGS = 10V,
RGS = 5.1Ω
-
-
110
ns
-
15
-
ns
tr
-
60
-
ns
td(OFF)
-
20
-
ns
tf
-
25
-
ns
tOFF
-
-
70
ns
-
110
130
nC
-
57
75
nC
-
3.7
4.5
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
td(ON)
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
VDD = 50V,
ID ≅ 56A,
RL = 0.89Ω
Ig(REF) = 1.0mA
(Figure 13)
Gate to Source Gate Charge
Qgs
-
9.8
-
nC
Gate to Drain “Miller” Charge
Qgd
-
24
-
nC
©2012 Fairchild Semiconductor Corporation
HUFA75639S3ST_F085A Rev. C1
HUFA75639S3ST_F085A
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
2000
-
pF
-
500
-
pF
-
65
-
pF
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
SYMBOL
PARAMETER
Source to Drain Diode Voltage
MIN
TYP
MAX
UNITS
ISD = 56A
-
-
1.25
V
trr
ISD = 56A, dISD/dt = 100A/µs
-
-
110
ns
QRR
ISD = 56A, dISD/dt = 100A/µs
-
-
320
nC
VSD
Reverse Recovery Time
Reverse Recovered Charge
TEST CONDITIONS
1.2
60
1.0
50
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
40
30
20
10
0.2
0
0
0
25
50
75
100
125
150
25
175
50
TC , CASE TEMPERATURE (oC)
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2012 Fairchild Semiconductor Corporation
HUFA75639S3ST_F085A Rev. C1
HUFA75639S3ST_F085A
Typical Performance Curves
(Continued)
IDM , PEAK CURRENT (A)
1000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
100
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
300
1000
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
100
100µs
10
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
VDSS(MAX) = 100V
10
100
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0.001
1
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
200
1
0.1
0.01
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
100
100
80
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 6V
VGS = 20V
VGS = 10V
60
VGS = 7V
40
VGS = 5V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0
0
1
2
3
4
5
6
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
©2012 Fairchild Semiconductor Corporation
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
80
175oC
60
40
20
25oC
-55oC
0
7
0
1.5
3.0
4.5
6.0
7.5
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
HUFA75639S3ST_F085A Rev. C1
HUFA75639S3ST_F085A
Typical Performance Curves
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 56A
VGS = VDS, ID = 250µA
NORMALIZED GATE
2.5
2.0
1.5
1.0
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
3.0
(Continued)
1.0
0.8
0.5
0
0.6
-80
-40
0
40
80
120
160
200
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.2
3000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
ID = 250µA
2500
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
0
1.1
1.0
2000
CISS
1500
1000
COSS
500
CRSS
0.9
-80
0
-40
0
40
80
120
160
200
0
10
TJ , JUNCTION TEMPERATURE (oC)
20
30
40
50
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 56A
ID = 37A
ID = 18A
2
VDD = 50V
0
0
10
20
30
40
50
60
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2012 Fairchild Semiconductor Corporation
HUFA75639S3ST_F085A Rev. C1
HUFA75639S3ST_F085A
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
-
VGS
VDS
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
IG(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2012 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
HUFA75639S3ST_F085A Rev. C1
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™
TINYOPTO™
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Saving our world, 1mW/W/kW at a time™
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Solutions for Your Success™
MICROCOUPLER™
TRUECURRENT®*
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®
SuperFET®
MicroPak2™
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MillerDrive™
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SuperSOT™-6
MotionMax™
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SuperSOT™-8
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®*
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2.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Definition
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I61
©2012 Fairchild Semiconductor Corporation
HUFA75639S3ST_F085A Rev. C1