FXMA2102 Dual Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Features Description Bi-Directional Interface between Any Two Levels: 1.65 V to 5.5 V Direction Control not Needed The FXMA2102 is a high-performance configurable dual-voltage-supply translator for bi-directional voltage translation over a wide range of input and output voltages levels. System GPIO Resources Not Required when OE Tied to VCCA Intended for use as a voltage translator between I2CBus® complaint masters and slaves. I2C 400 pF Buffer / Repeater Open-Drain Inputs / Outputs Supports I2C Clock Stretching & Multi-Master I2C Bus Isolation A/B Port VOL = 175 mV (Typical), VIL = 150 mV, IOL = 6 mA Accommodates Standard-Mode and Fast-Mode I2C-Bus Devices Fully Configurable: Inputs and Outputs Track VCC Control Input (/OE) Referenced to VCCA. The device is designed so that the A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional A/B port voltage translation between any two levels from 1.65 V to 5.5 V. VCCA can equal VCCB from 1.65V to 5.5V. The OE pin is referenced to VCCA. Either VCC can be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The two ports of the device have automatic direction sense capability. Either port may sense an input signal and transfer it as an output signal to the other port. Non-Preferential Power-Up; Either VCC May Be Powered-Up First Outputs Switch to 3-State if Either VCC is at GND ESD Protection Exceeds: - 8 kV HBM ESD (per JESD22-A114) - 2 kV CDM (per JESD22-C101) Tolerant Output Enable: 5 V Packaged in 8-Terminal Leadless MicroPak™ (1.6 mm x 1.6 mm) and Ultrathin MLP (1.2 mm x 1.4 mm) Ordering Information Part Number FXMA2102L8X FXMA2102UMX Operating Temperature Range Top Mark -40 to +85°C XN © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 Package 8-Lead MicroPak™, 1.6 mm Wide 8-Lead Ultrathin MLP, 1.2 mm x 1.4 mm Packing Method 5000 Units on Tape and Reel www.fairchildsemi.com FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications August 2012 Figure 1. Block Diagram, 1 of 2 Channels © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Block Diagram www.fairchildsemi.com 2 VCCB B0 B1 OE 7 6 5 8 GND 4 1 2 3 VCCA A0 A1 Figure 2. MicroPak™ (Top-Through View) Figure 3. UMLP (Top-Through View) Pin Definitions Pin # Name Description 1 VCCA A-Side Power Supply 2, 3 A0, A1 A-Side Inputs or 3-State Outputs 4 GND Ground 5 OE 6, 7 B1, B0 B-Side Inputs or 3-State Outputs 8 VCCB B-Side Power Supply Output Enable Input (Referenced to VCCA ) Truth Table Control Outputs OE LOW Logic Level 3-State HIGH Logic Level Normal Operation Note: 1. If the OE pin is driven LOW, the FXMA2102 is disabled and the A0, A1, B0, and B1 pins (including dynamic drivers) are forced into 3-state. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Pin Configuration www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. –0.5 7.0 A Port –0.5 7.0 B Port –0.5 7.0 Control Input (OE) –0.5 7.0 An Outputs 3-State –0.5 7.0 Bn Outputs 3-State –0.5 7.0 An Outputs Active –0.5 VCCA + 0.5V Bn Outputs Active –0.5 VCCB + 0.5V VCCA, VCCB Supply Voltage VIN VO DC Input Voltage Output Voltage(2) IIK DC Input Diode Current IOK DC Output Diode Current IOH / IOL At VIN < 0 V –50 At VO < 0 V –50 At VO > VCC +50 DC Output Source/Sink Current –50 +50 Unit V V mA mA mA ICC DC VCC or Ground Current per Supply Pin ±100 mA PD Power Dissipation 0.129 mW +150 °C At 400 KHz TSTG Storage Temperature Range ESD Electrostatic Discharge Capability –65 Human Body Model, JESD22-A114 8 Charged Device Mode, JESD22-C101 2 kV Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCCA, VCCB Power Supply Operating VIN Input Voltage Min. Max. Unit 1.65 5.50 V A Port 0 5.5 B Port 0 5.5 Control Input (OE) 0 VCCA 8-Lead MicroPak™ 279.0 8-Lead Ultrathin MLP 301.5 ΘJA Thermal Resistance TA Free Air Operating Temperature –40 +85 V C°/W FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Absolute Maximum Ratings °C Note: 3. All unused inputs and I/O pins must be held at VCCI or GND. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 4 Power-Up/Power-Down Sequencing The recommended power-up sequence is: FXM translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0 V, outputs are in a high-impedance state. The control input (OE) is designed to track the VCCA supply. A pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. The size of the pulldown resistor is based upon the current-sinking capability of the device driving the OE pin. 1. Apply power to the first VCC. 2. Apply power to the second VCC. 3. Drive the OE input HIGH to enable the device. The recommended power-down sequence is: 1. Drive OE input LOW to disable the device. 2. Remove power from either VCC. 3. Remove power from other VCC. Note: 4. Alternatively, the OE pin can be hardwired to VCCA to save GPIO pins. If OE is hardwired to VCCA, either VCC can be powered up or down first. Application Circuit FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Functional Description Figure 4. Application Circuit © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 5 is a slave on the B port, the Npassgates act as a low resistive short between both ports until either of the port’s VCC/2 thresholds are reached. After the RC time constant has reached the VCC/2 threshold of either port, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the LOW-to-HIGH (LH) direction, accelerating the rising edge. The resulting rise time resembles the scope shot in Figure 5. Effectively, two distinct slew rates appear in rise time. The first slew rate (slower) is the RC time constant of the bus. The second slew rate (much faster) is the dynamic driver accelerating the edge. The FXMA2102 has open-drain I/Os and requires external pull-up resistors on the four data I/O pins, as shown in Figure 4. If a pair of data I/O pins (An/Bn) is not used, both pins should be tied to GND (or both to VCC). In this case, pull-down or pull-up resistors are not required. The recommended values for the pull-up resistors (RPU) are 1 KΩ to 10 KΩ; however, depending on the total bus capacitance, the user is free to vary the pull-up resistor value to meet the maximum I2C edge rate per the I2C specification (UM10204 rev. 03, June 19, 2007). For example, the maximum edge rate (30% 70%) during fast mode (400 kbit/s) is 300 ns. If bus capacitance is approaching the maximum 400 pF, lower the RPU value to keep the rise time below 300 ns (Fast Mode). Section 7.1 of the I2C specification provides an excellent guideline for pull-up resistor sizing. If both the A and B ports of the translator are HIGH, a high-impedance path exists between the A and B ports because both the Npassgates are turned off. If a master or slave device decides to pull SCL or SDA LOW, that device’s driver pulls down (Isink) SCL or SDA until the edge reaches the A or B port VCC/2 threshold. When either the A or B port threshold is reached, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the HIGH-to-LOW (HL) direction, accelerating the falling edge. Theory of Operation The FXMA2102 is designed for high-performance level shifting and buffer / repeating in an I2C application. Figure 1 shows that each bi-directional channel contains two series-Npassgates and two dynamic drivers. This hybrid architecture is highly beneficial in an I2C application where auto-direction is a necessity. For example, during the following three I2C protocol events: Clock Stretching Slave’s ACK Bit (9th bit = 0) following a Master’s Write Bit (8th bit = 0) Clock Synchronization and Multi Master Arbitration the bus direction needs to change from master to slave to slave to master without the occurrence of an edge. If there is an I2C translator between the master and slave in these examples, the I2C translator must change direction when both A and B ports are LOW. The Npassgates can accomplish this task very efficiently because, when both A and B ports are LOW, the Npassgates act as a low resistive short between the two (A and B) ports. Due to I2C’s open-drain topology, I2C masters and slaves are not push/pull drivers. Logic LOWs are “pulled down” (Isink), while logic HIGHs are “let go” (3-state). For example, when the master lets go of SCL (SCL always comes from the master), the rise time of SCL is largely determined by the RC time constant, where R = RPU and C = the bus capacitance. If the FXMA2102 is attached to the master [on the A port] in this example, and there © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 Figure 5. FXMA2102 Waveform C: 600 pF, RPU: 2.2 K FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Application Notes www.fairchildsemi.com 6 VOL vs. IOL The FXMA2102 dynamic drivers have enough current sourcing capability to drive a 400 pF capacitive bus. This is beneficial for instances when an I2C buffer / repeater is required. The I2C specification stipulates a maximum bus capacitance of 400 pF. If an I2C segment exceeds 400 pF, an I2C buffer / repeater is required to split the segment into two segments, each of which is less than 400 pF. Figure 5 is a scope shot of an FXMA2102 driving a lumped load of 600 pF. Notice the (30% - 70%) rise time is only 112 ns (RPU = 2.2 K). This is well below the maximum edge rate of 300 ns. Not only does the FXMA2102 drive 400 pF, but it also provides excellent headroom below the I2C specification maximum edge rate of 300 ns. The I2C specification mandates a maximum VIL (IOL of 3 mA) of VCC • 0.3 and a maximum VOL of 0.4 V. If there is a master on the A port of an I2C translator with a VCC of 1.65 V and a slave on the I2C translator B port with a VCC of 3.3 V, the maximum VIL of the master is (1.65 V x 0.3) 495 mV. The slave could legally transmit a valid logic LOW of 0.4 V to the master. If the I2C translator’s channel resistance is too high, the voltage drop across the translator could present a VIL to the master greater than 495 mV. To complicate matters, the I2C specification states that 6 mA of IOL is recommended for bus capacitances approaching 400 pF. More IOL increases the voltage drop across the I2C translator. The I2C application benefits when I2C translators exhibit low VOL performance. Figure 6 depicts typical FXMA2102 VOL performance vs. the competition, given a 0.4 V VIL. Figure 6. VOL vs. IOL © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Buffer / Repeater Performance www.fairchildsemi.com 7 2 The FXMA2102 supports I C-Bus isolation for the following conditions: Bus isolation if bus clear Bus isolation if either VCC goes to ground Either VCC to GND If slave #2 is a camera that is suddenly removed from the I2C bus, resulting in VCCB transitioning from a valid VCC (1.65 V – 5.5 V) to 0 V, the FXMA2102 automatically forces SCL and SDA on both its A and B ports into 3-state. Once VCCB has reached 0V, full I2C communication between the master and slave #1 remains undisturbed. Bus Clear 2 Because the I C specification defines the minimum SCL frequency of DC, the SCL signal can be held LOW forever; however, this condition shuts down the I2C bus. The I2C specification refers to this condition as “Bus Clear”. In Figure 7, if slave #2 holds down SCL forever, the master and slave #1 are not able to communicate, because the FXMA2102 passes the SCL stuck-LOW condition from slave #2 to slave #1 as well as the Figure 7. Bus Isolation © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications master. However, if the OE pin is pulled LOW (disabled), both ports (A and B) are 3-stated. This results in the FXMA2102 isolating slave #2 from the master and slave #1, allowing full communication between the master and slave #1. 2 I C-Bus® Isolation www.fairchildsemi.com 8 TA = –40°C to +85°C. Symbol Parameter VIHA High Level Input Voltage A VIHB High Level Input Voltage B VILA Low Level Input Voltage A VILB Low Level Input Voltage B VOL Low Level Output Voltage VCCA (V) VCCB (V) Min. Data Inputs An 1.65–5.50 1.65–5.50 VCCA – 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.7 x VCCA Data Inputs Bn 1.65–5.50 1.65–5.50 VCCB – 0.4 Data Inputs An 1.65–5.50 1.65–5.50 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.3 x VCCA V Data Inputs Bn 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 0.4 V 1.65–5.50 1.65–5.50 ±1.0 µA VIN or VO = 0 V to 5.5 V 0 5.50 ±2.0 VIN or VO = 0 V to 5.5 V 5.50 0 ±2.0 An, Bn VO = 0 V to 5.5 V, OE = VIL 5.50 5.50 ±2.0 An VO = 0 V to 5.5 V, OE = Don’t Care 5.50 0 ±2.0 Bn VO = 0 V to 5.5 V, OE = Don’t Care 0 5.50 ±2.0 VIN = VCCI or GND, IO = 0 1.65–5.50 1.65–5.50 5.0 µA ICCZ VIN = VCCI or GND, IO = 0, Quiescent Supply Current(7) OE = VIL 1.65–5.50 1.65–5.50 5.0 µA ICCA VIN = 5.5 V or GND, IO = 0, Quiescent Supply Current(6) OE = Don’t Care, Bn to An 0 1.65–5.50 –2.0 1.65–5.50 0 2.0 ICCB VIN = 5.5 V or GND, IO = 0, Quiescent Supply Current(6) OE = Don’t Care, An to Bn 1.65–5.50 0 –2.0 0 1.65–5.50 2.0 IL IOFF IOZ ICCA/B Input Leakage Current Condition Quiescent Supply Current(7,8) Unit V V VIL = 0.15 V IOL = 6 mA Control Input OE, VIN = VCCA or GND An Power Off Leakage Current Bn 3-State Output Leakage(6) Max. Notes: 5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical Characteristics. 6. “Don’t Care” indicates any valid logic level. 7. VCCI is the VCC associated with the input side. 8. Reflects current per supply, VCCA or VCCB. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 µA µA µA µA FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications DC Electrical Characteristics www.fairchildsemi.com 9 Output Rise / Fall Time Output load: CL = 50 pF, RPU = 2.2 kΩ, push / pull driver, and TA = -40°C to +85°C. VCCO(10) Symbol Parameter 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Unit Typ. Typ. Typ. Typ. trise Output Rise Time; A Port, B (11) Port 3 4 5 7 ns tfall Output Fall Time; A Port, B Port(12) 1 1 1 1 ns Notes: 9. Output rise and fall times guaranteed by design simulation and characterization; not production tested. 10. VCCO is the VCC associated with the output side. 11. See Figure 12. 12. See Figure 13. ( ) Maximum Data Rate 13 Output load: CL = 50 pF, RPU = 2.2 kΩ, push / pull driver, and TA = -40°C to +85°C. VCCB VCCA 4.5 V to 5.5 V 3.0 V to 3.6 V 2.3 V to 2.7 V 1.65 V to 1.95 V Direction 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Min. Min. Min. Min. A to B 50 50 40 30 B to A 50 50 40 40 A to B 50 50 40 19 B to A 50 50 40 40 A to B 40 40 30 19 B to A 40 40 30 30 A to B 40 40 30 19 B to A 30 30 19 19 Note: 13. F-toggle guaranteed by design simulation; not production tested. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 Unit MHz MHz MHz MHz FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Dynamic Output Electrical Characteristics www.fairchildsemi.com 10 Output Load: CL = 50 pF, RPU = 2.2 kΩ, and TA = -40°C to +85°C. VCCB Symbol Parameter 4.5 to 5.5 V 3.0 to 3.6 V 2.3 to 2.7 V 1.65 to 1.95 V Unit Typ. Max. Typ. Max. Typ. Max. Typ. Max. VCCA = 4.5 to 5.5 V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) 1 1 2 2 4 3 65 5 0.50 3 3 4 4 5 5 100 9 1.50 1 2 3 2 6 4 65 6 0.50 3 4 5 5 10 7 105 10 1.00 1 3 4 2 5 5 65 7 0.50 3 5 6 6 9 8 105 12 1.00 1 4 5 5 7 10 65 9 0.50 3 7 7 7 15 15 105 16 1.00 VCCA = 3.0 to 3.6 V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) 2.0 1.5 2.0 2.0 4.0 4.0 100 5 0.5 5.0 3.0 4.0 4.0 8.0 8.0 115 10 1.5 1.5 1.5 2.0 2.0 5.0 6.0 100 4 0.5 3.0 4.0 4.0 4.0 9.0 9.0 115 8 1.0 1.5 2.0 2.0 2.0 6.0 8.0 100 5 0.5 3.0 6.0 5.0 5.0 11.0 11.0 115 10 1.0 1.5 3.0 3.0 3.0 7.0 10.0 100 9 0.5 3.0 9.0 5.0 5.0 15.0 14.0 115 15 1.0 VCCA = 2.3 to 2.7 V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) 2.5 1.5 2.0 2.0 5.0 4.0 100 65 0.5 5.0 3.0 5.0 5.0 10.0 8.0 115 110 1.5 2.5 2.0 2.0 2.0 5.0 4.5 100 65 0.5 5.0 4.0 5.0 5.0 10.0 9.0 115 110 1.0 2.0 3.0 2.0 2.0 6.0 5.0 100 65 0.5 4.0 6.0 5.0 5.0 12.0 10.0 115 115 1.0 1.0 5.0 3.0 3.0 9.0 9.0 100 12 0.5 3.0 10.0 6.0 6.0 18.0 18.0 115 25 1.0 VCCA = 1.65 to 1.95 V A to B tPLH B to A A to B tPHL B to A OE to A tPZL OE to B OE to A tPLZ OE to B tskew A Port, B Port(14) 4 1.0 5 4 11 6 75 75 0.5 7 2.0 8 8 15 14 115 115 1.5 4 1.0 3 3 11 6 75 75 0.5 7 2.0 7 7 14 12 115 115 1.0 5 1.5 3 3 14 6 75 75 0.5 8 3.0 7 7 28 12 115 115 1.0 5 5.0 3 3 14 9 75 75 0.5 10 10.0 7 7 23 16 115 115 1.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications AC Characteristics ns ns ns Note: 14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 15). Skew is guaranteed, but not tested. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 11 TA = +25°C. Symbol Parameter Condition Typ. Unit CIN Input Capacitance Control Pin (OE) VCCA = VCCB = GND 2.2 pF CI/O Input/Output Capacitance, An, Bn VCCA = VCCB = 5.0 V, OE = GND, VA = VB = 5.0 V 13.0 pF Cpd Power Dissipation Capacitance VCCA = VCCB = 5.0 V, VIN = 0 V or VCC, f = 400 KHz 13.5 pF Figure 8. AC Test Circuit Table 1. Table 2. Propagation Delay Table Test Input Signal Output Enable Control tPLH, tPHL Data Pulses VCCA tPZL (OE to An, Bn) 0V LOW to HIGH Switch tPLZ (OE to An, Bn) 0V HIGH to LOW Switch VCCO CL RL 1.8 ± 0.15 V 50 pF 2.2 kΩ 2.5 ± 0.2 V 50 pF 2.2 kΩ 3.3 ± 0.3 V 50 pF 2.2 kΩ 5.0 ± 0.5 V 50 pF 2.2 kΩ AC Load Table © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Capacitance www.fairchildsemi.com 12 DATA IN VCCI Vmi DATA OUT VCCO DATA OUT Waveform for Inverting and Non-Inverting Functions(15) Vmi VOL Symbol VCC Vmi(16) VCCI / 2 Vmo VCCO / 2 VX 0.5 x VCCO VY 0.1 x VCCO GND Vx VOL VY Figure 10. 3-STATE Output Low Enable Time(15) VCCA tPLZ DATA OUT GND tPZL Vmo OUTPUT CONTROL VCCA Vmi tpxx tpxx Figure 9. OUTPUT CONTROL GND (15) Figure 11. 3-STATE Output High Enable Time Figure 12. Active Output Rise Time Figure 13. Active Output Fall Time VCCO DATA OUTPUT Vmo Vmo GND tperiod DATA IN VCCI / 2 VCCI / 2 tskew VCCI GND DATA OUTPUT F-toggle rate, f = 1 / tperiod tskew VCCO Vmo Vmo GND tskew = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin) Figure 14. F-Toggle Rate FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Timing Diagrams Figure 15. Output Skew Time Notes: 15. Input tR = tF = 2.0 ns, 10% to 90% at VIN = 1.65 V to 1.95 V; Input tR = tF = 2.0 ns, 10% to 90% at VIN = 2.3V to 2.7 V; Input tR = tF = 2.5 ns, 10% to 90%, at VIN = 3.0 V to 3.6 V only; Input tR = tF = 2.5 ns, 10% to 90%, at VIN = 4.5 V to 5.5V only. 16. VCCI = VCCA for control pin OE or Vmi = (VCCA / 2). © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 13 0.10 2X C A 1.6 B 1.6 INDEX AREA 0.10 2X C TOP VIEW 0.55 MAX 0.05 0.05 0.00 DETAIL A 8X(0.09) C 8X 0.05 Recommended Landpattern C (0.20) 1.0 2 1 4 (0.1) C 8 0.35 0.25 3X(0.2) 0.35 0.25 0.5 3 4 7 6 5 (0.15) 0.15 8X 0.25 0.10 0.05 C A B C 0.35 0.25 DETAIL A PIN #1 TERMINAL SCALE: 2X BOTTOM VIEW Notes: 1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y.14M-1994 4. PIN 1 FLAG, END OF PACKAGE OFFSET 5. DRAWING FILE NAME: MKT-MAC08AREV4 MAC08AREV4 Figure 16. 8-Lead MicroPak™, 1.6 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape & Reel Format for MicroPak™ Always visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 14 0.10 C 1.40 2X A 1.45 0.725 0.40 B 1.25 0.45 1.20 0.625 (7X) 0.35 0.10 C TOP VIEW 0.25 (8X) 2X RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C (0.15) 0.10 0.05 C 0.025 0.00 SEATING C PLANE 0.20 45° SIDE VIEW 0.30 0.10 DETAIL : A SCALE : 2X (0.20) 2 DETAIL A A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. 5 1 PIN#1 IDENT NOTES: 0.35 0.25 (7X) 4 8 6 0.40 BOTTOM VIEW C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 0.25 (8X) 0.15 0.10 0.05 C A B C D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. DRAWING FILENAME: MKT-UMLP08Arev3. PACKAGE EDGE LEAD OPTION 1 SCALE : 2X Figure 17. LEAD OPTION 2 SCALE : 2X 8-Lead Ultrathin MLP, 1.2 mm x 1.4 mm Product-Specific Dimensions Symbol from JEDEC MO-220 Description NOM Value A Overall Height 0.55 A1 PKG Standoff 0.012 A3 Lead Thickness 0.15 b Lead Width 0.2 D Body Length (X) 1.4 E Body Width (Y) 1.2 L Lead Length 0.3 e Lead Pitch 0.4 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape & Reel Format for MicroPak™ Always visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/dwg/UM/UMLP08A.pdf. © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5 www.fairchildsemi.com 15 FXMA2102 — Dual-Supply, 2-Bit Voltage Translator / Buffer / Repeater / Isolator for I2C Applications 16 www.fairchildsemi.com © 2010 Fairchild Semiconductor Corporation FXMA2102 • Rev. 1.0.5