FXMA108 Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signals Levels, 3-State Outputs and Auto Direction Sensing Features Description Bi-Directional Interface between Two Levels from 1.65V to 5.5V Fully Configurable: Inputs and Outputs Track VCC Outputs Remain in 3-State Until Active VCC Level is Reached The FXMA108 is a configurable dual-voltage supply translator designed for both uni-directional and bidirectional voltage translation between two logic levels. The device allows translation between voltages as high as 5.5V to as low as 1.65V. The A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional voltage translation over a variety of voltage levels: 1.8V, 2.5V, 3.3V, and 5.0V. Outputs Switch to 3-State if Either VCC is at GND Control Input (/OE) is Referenced to VCCA Voltage ESD Protection Exceeds: Non-Preferential Power-Up; Either VCC may be Powered-Up First Power-Off Protection Bus Hold On Data Inputs Eliminates the Need for Pull-Up Resistors Packaged in 20-Terminal DQFN Direction Control Not Needed 80Mbps Throughput when Translating between 2.5V and 5.0V The device remains in 3-state until both VCCs reach active levels, allowing either VCC to be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed. The /OE input, when high, disables both the A and B Side by placing them in a 3-state condition. The /OE input is supplied by VCCA. The FXMA108 supports bi-directional translation without the need for a direction control pin. The two sides of the device have auto-direction-sense capability. Either port may sense an input signal and transfer it as an output signal to the other port. − 8kV Human Body Model (B Port I/O to GND) (JESD22-A114 & Mil Std 883e 3015.7) Applications − 5kV Human Body Model (A Port I/O to GND) (JESD22-A114 & Mil Std 883e 3015.7) − 2kV Charged Device Model (ESD STM 5.3) (JESD22-C101) Cell Phones, PDA, Digital Camera, Portable GPS, and Storage Ordering Information Part Number Operating Temperature Range FXMA108BQX -40 to 85°C © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 Package 20-Lead, DQFN, JEDEC MO-241, 2.5x4.5mm Packing Method 3000 Units Tape and Reel www.fairchildsemi.com FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels July 2010 Figure 1. Block Diagram Functional Table Control Outputs /OE LOW Logic Level Normal Operation HIGH Logic Level 3-State © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Functional Diagram www.fairchildsemi.com 2 VCCA VCCB 20 1 A0 2 19 B0 A1 3 18 B1 A2 4 17 B2 A3 5 16 B3 A4 6 15 B4 A5 7 14 B5 A6 8 13 B6 A7 9 12 B7 10 11 GND /OE Figure 2. Pin Configuration (Top Through View) Pin Definitions Pin # Name Description 1 VCCA 2 A0 A-Side Inputs or 3-State Outputs 3 A1 A-Side Inputs or 3-State Outputs 4 A2 A-Side Inputs or 3-State Outputs 5 A3 A-Side Inputs or 3-State Outputs 6 A4 A-Side Inputs or 3-State Outputs 7 A5 A-Side Inputs or 3-State Outputs A-Side Power Supply 8 A6 A-Side Inputs or 3-State Outputs 9 A7 A-Side Inputs or 3-State Outputs 10 GND Ground 11 /OE Output Enable Input 12 B7 B-Side Inputs or 3-State Outputs 13 B6 B-Side Inputs or 3-State Outputs 14 B5 B-Side Inputs or 3-State Outputs 15 B4 B-Side Inputs or 3-State Outputs 16 B3 B-Side Inputs or 3-State Outputs 17 B2 B-Side Inputs or 3-State Outputs 18 B1 B-Side Inputs or 3-State Outputs 19 B0 B-Side Inputs or 3-State Outputs 20 VCCB DAP NC FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Pin Configuration B-Side Power Supply No Connect © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VO Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IOH/IOL ICC TSTG ESD Conditions Min. Max. VCCA -0.5 7.0 VCCB -0.5 7.0 I/O Side A and B -0.5 7.0 Control Input (/OE) -0.5 7.0 Output 3-State -0.5 7.0 Output Active (An) (1) -0.5 VCCA +0.5 Output Active (Bn) (1) -0.5 VCCB +0.5 VIN < 0V -50 VO < 0V -50 VO > VCC +50 DC Output Source/Sink Current Electrostatic Discharge Capability V V V mA mA -50 +50 mA ±100 mA -65 +150 °C DC VCC or Ground Current (Per Supply Pin) Storage Temperature Range Unit Human Body Model, JESD22A114, and Mil Std 883e 3015.7 B Port I/O to GND 8000 Human Body Model, JESD22A114 and Mil Std 883e 3015.7 A Port I/O to GND 5000 Charged Device Model, JESD22-C101 per ESD STM 5.3 V 2000 Note: 1. IO absolute maximum ratings must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Power Supply VIN Input Voltage TA Operating Temperature, Free Air dt/dV Input Edge Rate Conditions Operating VCCA or VCCB Side A and B Control Input (/OE) VCCA/B=1.65 to 5.5V Typ. Max. Unit 1.65 5.50 V 0 5.5 V 0 VCCA V -40 +85 °C 10 ns/V Note: 2. All unused inputs and input/outputs must be held at VCCI or GND. VCCI is the VCC associated with the input side. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Absolute Maximum Ratings www.fairchildsemi.com 4 The recommended power-down sequence is: Fairchild translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (/OE) is designed to track the VCCA supply. A pull-up resistor tying /OE to VCCA should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down. The size of the pull-up resistor is based upon the current-sinking capability of the device driving the /OE pin. 1. 2. 3. Pull-Up/Pull-Down Resistors Do not use pull-up or pull-down resistors. This device has bus-hold circuits: pull-up or pull-down resistors are not recommended because they interfere with the output state. The current through these resistors may exceed the hold drive, II(HOLD) and/or II(OD) bus-hold currents. The bus-hold feature eliminates the need for extra resistors. The recommended power-up sequence is: 1. 2. 3. Apply power to the first VCC. Apply power to the second VCC. Drive the /OE input LOW to enable the device. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 Drive /OE input HIGH to disable the device. Remove power from either VCC. Remove power from the other VCC. FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Power-Up/Power-Down Sequence www.fairchildsemi.com 5 TA=-40°C to +85°C. Symbol Parameter VIHA High Level Input Voltage Conditions Data Inputs An Control Pin /OE VCCA (V) VCCB (V) 1.65 - 5.50 1.65 - 5.50 Data Inputs Bn 1.65 - 5.50 1.65 - 5.50 VILA Data Inputs An Control Pin /OE 1.65 - 5.50 1.65 - 5.50 VILB VOHA VOHB VOLA VOLB II(HOLD) II(ODH) II(ODL) High Level (3) Output Voltage Low Level Output (3) Voltage Bushold Input Minimum Drive Current Bushold Input Overdrive High (4) Current Bushold Input Overdrive Low (5) Current Max. Units 0.65 x VCCA V VIHB Low Level Input Voltage Min. 0.65 x VCCB 0.35 x VCCA V Data Inputs Bn 1.65 - 5.50 1.65 - 5.50 0.35 x VCCB IOH=-20µA 1.65 - 5.50 1.65 - 5.50 VCCA - 0.4 IOH=-20µA 1.65 - 5.50 1.65 - 5.50 VCCB - 0.4 IOL=20µA 1.65 - 5.50 1.65 - 5.50 0.4 IOL=20µA 1.65 - 5.50 1.65 - 5.50 0.4 V V VIN=1.60V 4.5 4.5 140 VIN=2.90V 4.5 4.5 -140 VIN=1.05V 3.0 3.0 75 VIN=1.95V 3.0 3.0 -75 VIN=0.80V 2.3 2.3 45 VIN=1.50V 2.3 2.3 -45 VIN=0.57V 1.65 1.65 25 VIN=1.07V 1.65 1.65 -25 5.5 5.5 750 3.6 3.6 450 2.7 2.7 300 1.95 1.95 200 5.5 5.5 -750 3.6 3.6 -450 2.7 2.7 -300 1.95 1.95 -200 Data Inputs An, Bn Data Inputs An, Bn μA μA FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels DC Electrical Characteristics Continued on the following page… © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 www.fairchildsemi.com 6 TA=-40°C to +85°C. Symbol II IOFF IOZ ICCA/B ICCZ ICCA ICCB Parameter Conditions VCCA (V) VCCB (V) Min. Max. Units µA Input Leakage Current Control Inputs /OE VIN=VCCA or GND 1.65 - 5.50 5.5 ±1 Power Off Leakage Current An, VO=0V to 5.5V 0 5.5 ±2 Bn, VO=0V to 5.5V 5.5 0 ±2 An, Bn VO=0V or 5.5V, /OE VIH 5.5 5.5 ±5 An, VO=0V or 5.5V, /OE=GND 5.5 0 ±5 Bn, VO=0V or 5.5V, /OE=GND 0 5.5 ±5 VIN=VCCI or GND, IO=0 /OE=GND 1.65 - 5.50 1.65 - 5.50 10 µA VIN=VCCI or GND, IO=0 /OE=VIH 1.65 - 5.50 1.65 - 5.50 10 µA VIN=VCCB or GND, IO=0 B-to-A Direction /OE=GND 0 1.65 - 5.50 -10 VIN=VCCA or GND, IO=0 A-to-B 1.65 - 5.50 0 10 VIN=VCCA or GND, IO=0 A-to-B Direction /OE=GND 1.65 - 5.50 0 -10 VIN=VCCB or GND, IO=0 B-to-A 0 3-State Output Leakage Quiescent Supply ( 6,7) Current Quiescent Supply ( 6,7) Current Quiescent Supply Current µA µA µA 1.65 - 5.50 Notes: 3. This is the output voltage for static conditions. 4. An external driver must source at least the specified current to switch LOW-to-HIGH. 5. An external driver must source at least the specified current to switch HIGH-to-LOW. 6. VCCI is the VCC associated with the input side. 7. Reflects current per supply, VCCA or VCCB. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 µA 10 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels DC Electrical Characteristics (Continued) www.fairchildsemi.com 7 A Port (An) Output Load: CL=15pF, RL ≥ 1MΩ. TA=-40°C to +85°C Symbol Parameter VCCA=4.5V to 5.5V VCCA=3.0V to 3.6V VCCA=2.3V to 2.7V VCCA=1.65V to 1.95V Max. Max. Max. Max. Units trise Output Rise (9) Time A Side 2.5 3.0 3.5 4.0 ns tfall Output Fall Time (10) A Side 2.5 3.0 3.5 4.0 ns Units B Port (Bn) Output Load: CL=15pF, RL ≥ 1MΩ. TA=-40°C to +85°C Symbol Parameter VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Max. Max. Max. Max. trise Output Rise 9) Time B Side 3.5 3.5 3.5 4.0 ns tfall Output Fall Time (10) B Side 3.5 3.5 3.5 4.0 ns Notes: 8. Dynamic output characteristics are guaranteed, but not tested in production. 9. See Figure 8. 10. See Figure 9. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Dynamic Output Electrical Characteristics(8) www.fairchildsemi.com 8 VCCA=4.5V to 5.5V, Output Load (see Table 2) TA=-40°C to +85°C Symbol VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Min. Max. A-to-B Side 1.5 5.0 1.75 6.0 2.0 6.5 2.6 10.5 B-to-A Side 1.5 5.0 1.75 6.0 2.0 6.5 2.6 10.5 Parameter Units tPLH ,tPHL tPZL, tPZH tskew ns /OE-to-A, /OE-to-B A Port, B Side (11) 1.7 1.7 1.7 1.7 µs 0.5 0.5 0.5 0.5 ns Note: 11. Skew is the variation of propagation delay between output signals and applies only to output signals on the same Side (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW). Skew is guaranteed, but not tested in production (see Figure 11 ). VCCA=3.0V to 3.6V, Output Load (see Table 2) TA=-40°C to +85°C Symbol VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Min. Max. A-to-B Side 2.0 5.5 2.2 6.5 2.4 7.5 2.6 11.0 B-to-A Side 2.0 5.5 2.2 6.5 2.4 7.5 2.6 11.0 Parameter Units tPLH, tPHL ns tPZL, tPZH /OE-to-A, /OE-to-B 1.7 1.7 1.7 1.7 µs tskew A Side, (12) B Side 0.7 0.7 0.7 0.7 ns Note: 12. Skew is the variation of propagation delay between output signals and applies only to output signals on the same Side (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW). Skew is guaranteed, but not tested in production (see Figure 11). © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels AC Characteristics www.fairchildsemi.com 9 VCCA=2.3V to 2.7V, Output Load (see Table 2) TA=-40°C to +85°C Symbol VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Min. Max. A-to-B Side 2.0 6.5 2.2 7.7 2.4 8.5 2.6 11.0 B-to-A Side 2.0 7.0 2.2 7.5 2.4 8.5 2.6 12.0 Parameter Units tPLH, tPHL ns tPZL, tPZH /OE- to-A /OE-to-B 1.7 1.7 1.7 1.7 µs tskew A Side, (13) B Side 0.7 0.7 0.7 0.7 ns Note: 13. Skew is the variation of propagation delay between output signals and applies only to output signals on the same Side (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW). Skew is guaranteed but not tested in production (see Figure 11). VCCA=1.65V to 1.95V, Output Load (see Table 2) TA=-40°C to +85°C Symbol VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Min. Max. Min. Max. Min. Max. Min. Max. A-to-B Side 2.0 10.0 2.2 11.0 2.4 12.0 2.6 14.0 B-to-A Side 2.0 10.0 2.2 10.5 2.4 11.0 2.6 14.0 Parameter Units tPLH, tPHL ns tPZL, tPZH /OE-to-A /OE to B 1.7 1.7 1.7 1.7 µs tskew A Side, (14) B Side 1.2 1.2 1.2 1.2 ns Note: 14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same Side (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW). Skew is guaranteed, but not tested in production (see Figure 11). © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels AC Characteristics (Continued) www.fairchildsemi.com 10 For output load, see Table 2. TA=-40°C to +85°C VCCA VCCB=4.5V to 5.5V VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V Min. Min. Min. Min. A-to-B 100 100 80 60 B-to-A 100 100 80 80 A-to-B 100 100 80 60 B-to-A 100 100 80 80 A-to-B 80 80 60 40 B-to-A 80 80 60 60 A-to-B 80 80 60 40 B-to-A 60 60 40 40 Direction Units VCCA=4.5V to 5.5V VCCA=3.0V to 3.6V Mbps VCCA=2.3V to 2.7V VCCA=1.65V to 1.95V Notes: 15. Maximum data rate is guaranteed, but not tested in production. 16. Maximum data rate is specified in megabits per second with all outputs switching, (see Figure 10). It is equivalent to two times the F-toggle frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz. Capacitance TA=+25°C. Symbol Parameter CIN Input Capacitance, Control Pin /(OE) CI/O Input / Output Capacitance CPD Power Dissipation Capacitance © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 Conditions An Bn VCCA=VCCB=GND VCCA=VCCB=5.0V, /OE=VCCA VCCA=VCCB=5.0V, VIN=0V or VCC, f=10MHz Typical Unit 3 pF 4 5 28 pF pF FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Maximum Data Rate(15, 16) www.fairchildsemi.com 11 The FXMA108 I/O architecture benefits the end user, beyond level translation, in the following three ways: Bus Hold Minimum Drive Current Specifies the minimum amount of current the bus hold driver can source/sink. The bus hold minimum drive current (IHOLD) is VCC dependent and guaranteed in the DC Electrical tables. The intent is to maintain a valid output state in a static mode, but that can be overridden when an input data transition occurs. Auto Direction without an external direction pin. Drive Capacitive Loads. Automatically shifts to a higher current drive mode only during “Dynamic Mode” or HL / LH transitions. Lower Power Consumption. Automatically shifts to low-power mode during “Static Mode” (no transitions), lowering power consumption. Bus Hold Input Overdrive Drive Current Specifies the minimum amount of current required (by an external device) to overdrive the bus hold in the event of a direction change. The bus hold overdrive (IODH, IODL) is VCC dependent and guaranteed in the DC Electrical tables. The FXMA108 does not require a direction pin. Instead, the I/O architecture detects input transitions on both side and automatically transfers the data to the corresponding output. For example, for a given channel, if both A and B side are at a static LOW, the direction has been established as A Æ B, and a LH transition occurs on the B port; the FXMA108 internal I/O architecture automatically changes direction from A Æ B to B Æ A. Dynamic Output Current The strength of the output driver during LH / HL transitions is captured in Figure 3 (IOLH, IOHD). The plot depicts the FXMA108 typical dynamic output current with a lumped capacitance of 4pF. During HL / LH transitions, or “Dynamic Mode,” a strong (typically 30mA) output driver drives the output channel in parallel with a weak (typically 100µA) output driver. After a typical delay of approximately 10ns – 50ns, the strong driver is turned off, leaving the weak driver enabled for holding the logic state of the channel. This weak driver is called the “bus hold.” “Static Mode” is when only the bus hold drives the channel. The bus hold can be over ridden (typically 500µA) in the event of a direction change. The strong driver allows the FXMA108 to quickly charge and discharge capacitive transmission lines during dynamic mode. Static mode conserves power, where ICC is typically < 5µA. Figure 3. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 Because the strong output driver is turned on only during LH / HL transitions, the actual drive current is difficult to measure directly. Approximate the drive current with the following formula: IOHD ≈ (CI / O) × 0.6 *VCCO ΔVOUT = (CI / O) × tRISE Δt (1) where CI/O = the typical lumped capacitance and VCCO is the supply voltage of the output driver. FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels I/O Architecture Benefit Typical Dynamic Output Current www.fairchildsemi.com 12 VCC TEST SIGNAL DUT C1 Figure 4. Table 1. Table 2. R1 AC Test Circuit Test Circuit Parameters Test Input Signal Output Enable Control tPLH, tPHL Data Pulses 0V tPZL 0V HIGH-to-LOW Switch tPZH VCCI HIGH-to-LOW Switch VCCO C1 R1 1.8V ± 0.15V 15pF 1MΩ 2.5V ± 0.2V 15pF 1MΩ 3.3 ± 0.3V 15pF 1MΩ 5.0 ± 0.5V 15pF 1MΩ AC Load Table © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels AC Tests and Waveforms www.fairchildsemi.com 13 Figure 5. Waveform for Inverting and Non-Inverting Functions Notes: 17. Input tR = tF = 2.0ns, 10% to 90%. 18. Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 5.5V only. Figure 6. 3-State Output Low Enable Time for Low Voltage Logic Notes: 19. Input tR = tF = 2.0ns, 10% to 90%. 20. Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 5.5V only. Figure 7. 3-State Output High Enable Time for Low Voltage Logic Notes: 21. Input tR = tF = 2.0ns, 10% to 90%. 22. Input tR = tF = 2.5ns, 10% to 90%, at VIN = 3.0V to 5.5V only. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels AC Tests and Waveforms www.fairchildsemi.com 14 Symbol VMI VCC (23) VCCI/2 VMO VCCO/2 VX 0.9 x VCCO VY 0.1 x VCCO Note: 23. VCCI = VCCA for control pin /OE or VMI = (VCCA /2). Figure 8. Active Output Rise Time Figure 10. Figure 11. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 Figure 9. Maximum Data Rate Active Output Fall Time FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels AC Tests and Waveforms (Continued) Output Skew Time www.fairchildsemi.com 15 Figure 12. 20-Lead, DQFN, JEDEC MO-241, 2.5x4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 www.fairchildsemi.com 16 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels 17 www.fairchildsemi.com © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1 FXMA108 — Dual-Supply, 8-Bit Signal Translator with Configurable Voltage Supplies and Signal Levels 18 www.fairchildsemi.com © 2010 Fairchild Semiconductor Corporation FXMA108 • Rev. 1.0.1