FAIRCHILD FQD12N20LTM

FQD12N20LTM_F085
200V Logic Level N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply, motor control.
•
•
•
•
•
•
•
9.0A, 200V, RDS(on) = 0.28Ω @VGS = 10 V
Low gate charge ( typical 16 nC)
Low Crss ( typical 17 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Low level gate drive requirement allowing direct
opration from logic drivers
• Qualified to AEC Q101
• RoHS Compliant
D
!
"
G
Absolute Maximum Ratings
Symbol
VDSS
ID
!
D-PAK
S
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
IDM
Drain Current
VGSS
Gate-Source Voltage
IAR
Avalanche Current
dv/dt
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
TJ, TSTG
TL
"
"
!
TC = 25°C unless otherwise noted
FQD12N20LTM_F085
200
- Continuous (TC = 100°C)
PD
! "
- Pulsed
(Note 1)
Units
V
9.0
A
5.7
A
36
A
± 20
V
(Note 1)
9.0
A
(Note 2)
5.5
2.5
V/ns
W
55
0.44
-55 to +150
W
W/°C
°C
300
°C
Power Dissipation (TC = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
Max
2.27
Units
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient *
--
50
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
110
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2010 Fairchild Semiconductor Corporation
FQD12N20LTM_F085 Rev. B
1
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FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
June 2010
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
200
--
--
V
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
--
0.14
VDS = 200 V, VGS = 0 V
--
--
1
µA
VDS = 160 V, TC = 125°C
--
--
10
µA
Gate-Body Leakage Current, Forward
VGS = 20 V, VDS = 0 V
--
--
100
nA
Gate-Body Leakage Current, Reverse
VGS = -20 V, VDS = 0 V
--
--
-100
nA
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
1.0
--
2.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 4.5 A
VGS = 5 V, ID = 4.5 A
--
0.22
0.25
0.28
0.32
Ω
gFS
Forward Transconductance
VDS = 30 V, ID = 4.5 A
--
11.6
--
S
--
830
1080
pF
--
120
155
pF
--
17
22
pF
IDSS
IGSSF
IGSSR
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
(Note 3)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 100 V, ID = 11.6 A,
RG = 25 Ω
(Note 3, 4)
VDS = 160 V, ID = 11.6 A,
VGS = 5 V
(Note 3, 4)
--
15
40
ns
--
190
390
ns
--
60
130
ns
--
120
250
ns
--
16
21
nC
--
2.8
--
nC
--
7.6
--
nC
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Electrical Characteristics
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
9.0
A
ISM
--
--
36
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 9.0 A
Drain-Source Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 11.6 A,
dIF / dt = 100 A/µs
(Note 3)
--
--
1.5
V
--
128
--
ns
--
0.56
--
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. ISD ≤ 11.6A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
3. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
4. Essentially independent of operating temperature
FQD12N20LTM_F085 Rev. B
2
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VGS
10 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
Bottom : 3.0 V
Top :
ID , Drain Current [A]
1
10
ID, Drain Current [A]
1
10
0
10
※ Notes :
1. 250μs Pulse Test
2. TC = 25℃
-1
10
150℃
0
25℃
10
-55℃
※ Notes :
1. VDS = 30V
2. 250μs Pulse Test
-1
-1
0
10
10
1
10
10
0
2
4
6
8
10
VGS, Gate-Source Voltage [V]
VDS , Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
1.2
1
VGS = 5 V
0.9
VGS = 10V
0.6
0.3
0.0
0
10
150℃
25℃
※ Notes :
1. VGS = 0V
2. 250μs Pulse Test
-1
0
6
12
18
24
30
10
36
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID , Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
1800
12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1500
1200
Capacitance [pF]
IDR, Reverse Drain Current [A]
10
10
VGS, Gate-Source Voltage [V]
RDS(on) [ Ω ],
Drain-Source On-Resistance
1.5
Ciss
900
Coss
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
600
Crss
300
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Typical Characteristics
VDS = 40V
VDS = 100V
8
VDS = 160V
6
4
2
※ Note : ID = 11.6 A
0
-1
10
0
10
0
1
10
Figure 5. Capacitance Characteristics
FQD12N20LTM_F085 Rev. B
0
5
10
15
20
25
30
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 6. Gate Charge Characteristics
3
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(Continued)
1.2
3.0
RDS(ON) , (Normalized)
Drain-Source On-Resistance
BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = 10 V
2. ID = 5.8 A
0.5
0.0
-100
200
-50
0
50
100
150
200
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
9.0
2
Operation in This Area
is Limited by R DS(on)
7.5
100 µs
1
10
10 µs
ID, Drain Current [A]
ID, Drain Current [A]
10
1 ms
10 ms
DC
0
10
※ Notes :
o
1. TC = 25 C
6.0
4.5
3.0
1.5
o
2. TJ = 150 C
3. Single Pulse
-1
10
0
1
10
0.0
25
2
10
10
50
100
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
0
※ N o te s :
1 . Z θ J C ( t ) = 2 . 2 7 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T JM - T C = P D M * Z θ JC(t)
0 .2
0 .1
0 .0 5
10
-1
PDM
0 .0 2
t1
0 .0 1
Z
θ JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
VDS, Drain-Source Voltage [V]
s in g le p u ls e
10
-5
10
-4
10
-3
10
-2
10
-1
t2
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
FQD12N20LTM_F085 Rev. B
4
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FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Typical Characteristics
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Typical Characteristics
IAS, AVALANCHE CURRENT (A)
20
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
o
STARTING TJ = 25 C
o
STARTING TJ = 125 C
1
0.001
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
Figure 12. Unclamped Inductive
Switching Capability
FQD12N20LTM_F085 Rev. B
5
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50KΩ
12V
200nF
VGS
Same Type
as DUT
Qg
5V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RG
5V
RL
VDS
90%
VDD
VGS
VGS
DUT
10%
td(on)
tr
t on
FQD12N20LTM_F085 Rev. B
6
td(off)
t off
tf
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Gate Charge Test Circuit & Waveform
www.fairchildsemi.com
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VGS
VGS
( Driver )
I SD
( DUT )
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Peak Diode Recovery dv/dt Test Circuit & Waveforms
di/dt
IRM
Body Diode Reverse Current
VDS
( DUT )
Body Diode Recovery dv/dt
VSD
VDD
Body Diode
Forward Voltage Drop
FQD12N20LTM_F085 Rev. B
7
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DPAK
MIN0.55
0.91 ±0.10
9.50 ±0.30
0.50 ±0.10
0.76 ±0.10
0.50 ±0.10
1.02 ±0.20
2.30TYP
[2.30±0.20]
(1.00)
(3.05)
(2XR0.25)
(0.10)
2.70 ±0.20
6.10 ±0.20
9.50 ±0.30
6.60 ±0.20
(5.34)
(5.04)
(1.50)
(0.90)
2.30 ±0.20
(0.70)
2.30TYP
[2.30±0.20]
(0.50)
2.30 ±0.10
0.89 ±0.10
MAX0.96
(4.34)
2.70 ±0.20
0.80 ±0.20
0.60 ±0.20
(0.50)
6.10 ±0.20
5.34 ±0.30
0.70 ±0.20
6.60 ±0.20
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
Package Dimensions
0.76 ±0.10
FQD12N20LTM_F085 Rev. B
8
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and (c) whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
FQD12N20LTM_F085 200V Logic Level N-Channel MOSFET
TRADEMARKS
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Definition of Terms
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Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change in
any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes
at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I48
FQD12N20LTM_F085 Rev. B
9
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