KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTRODUCTION KS0078 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2, or 4 lines with 5 × 8 or 6 × 8 dots format. FUNCTIONS • Character type dot matrix LCD driver & controller • Internal driver : 34 common and 120 segment signal output • Easy interface with 4-bit or 8-bit MPU • Clock synchronized serial Interface • 5 × 8 dot matrix possible • 6 × 8 dot matrix possible • Bi-directional shift function • All character reverse display • Display shift per line • Voltage converter for LCD drive voltage : 13 V max (2 times / 3 times) • Various instruction functions • Automatic power on reset FEATURES • Internal Memory - Character Generator ROM (CGROM) : 9,600 bits (240 characters × 5 × 8 dot) - Character Generator RAM (CGRAM) : 64 x 8 bits (8 characters × 5 × 8 dot) - Segment Icon RAM (SEGRAM) : 16 × 8 bits (96 icons max.) - Display Data RAM (DDRAM) : 96 × 8 bits (96 characters max.) • Low power operation - Power supply voltage range : 2.7 ~ 5.5 V (VDD) - LCD Drive voltage range : 3.0 ~ 13.0 V (VDD - V5) • CMOS process • Programmable duty cycle : 1/17, 1/33 (refer to Table 1.) • Internal oscillator with an external resistor • Bare chip available KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Table 1. Programmable duty cycles 5-dot font width Display Line Duty Ratio Numbers Single-chip Operation Displayable characters Possible icons 1 1/17 1 line of 48 characters 80 2 1/33 2 lines of 48 characters 80 4 1/33 4 lines of 24 characters 80 6-dot font width Display Line Duty Ratio Numbers Single-chip Operation Displayable characters Possible icons 1 1/17 1 line of 40 characters 96 2 1/33 2 lines of 40 characters 96 4 1/33 4 lines of 20 characters 96 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD BLOCK DIAGRAM IE OSC1 OSC2 Oscillator Power On Reset (POR) Timing Generator RESET IM 8 / RS/ CS E/ SCLK RW/ SID / 7 Instruction Register Instruction Decoder (IR) System Interface Serial 4 bit 8 bit Address Counter Display Data 34 bit RAM (DDRAM) Shift 96 x 8 bits Register Common COM0 COM33 Driver 7 / 7 / 8 / 8 DB4 DB7 DB3 DB1 Data Register 8 / Input/ Output Buffer / (DR) Busy Flag / 8 / 3 / 7 / 8 120 bit 120 bit Shift Latch Segment Register Circuit Driver SEG1 SEG120 / 8 DB0/ SOD SegmentRAM (SEGRAM) 16 bytes Ch aracter Gen erator RAM(CGRAM) 64 b ytes Ch aracter Gen erator ROM(CGROM) 960 0 b its Vci C1 V5OUT2 V5OUT3 LCD Driver Voltage Selector / 5 Voltage Converter C2 Cursor and Blink Controller / 5/6 Parallel / Serial Converter and Smooth Scroll Circuit V1 - V5 VDD GND (VSS) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 PAD CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Y (0, 0) X chip size : 5340 x 8740 PAD size :100 x 100 unit : µm 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 VDD OSC2 OSC1 RESET IM IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vci C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD LOCATION PAD PAD NO. NAME COORDINATE X- Y- PAD PAD NO. NAME COORDINATE X- Y- PAD PAD NO. NAME COORDINATE X- Y- PAD PAD NO. NAME D B0 / COORDINATE X- Y- - 5 00 -4 1 1 9 1 S E G7 9 -2 5 04 3540 24 S E G 1 02 -2 5 0 4 665 47 C O M 13 -2 5 0 4 - 2 322 70 2 SEG 8 0 -2 5 04 341 25 S E G 1 03 -2 5 0 4 540 48 C O M 14 -2 5 0 4 - 2 447 71 D B1 - 3 75 -4 1 1 9 3 SEG 8 1 -2 5 04 329 26 S E G 1 04 -2 5 0 4 415 49 C O M 15 -2 5 0 4 - 2 572 72 D B2 - 2 50 -4 1 1 9 4 SEG 8 2 -2 5 04 316 27 S E G 1 05 -2 5 0 4 290 50 C O M 16 -2 5 0 4 - 2 697 73 D B3 - 1 25 -4 1 1 9 5 SEG 8 3 -2 5 04 304 28 S E G 1 06 -2 5 0 4 165 51 C O M 25 -2 5 0 4 - 2 822 74 D B4 0 -4 1 1 9 6 SEG 8 4 -2 5 04 291 29 S E G 1 07 -2 5 0 4 40 52 C O M 26 -2 5 0 4 - 2 947 75 D B5 125 -4 1 1 9 7 SEG 8 5 -2 5 04 279 30 S E G 1 08 -2 5 0 4 -8 4 53 C O M 27 -2 5 0 4 - 3 072 76 D B6 250 -4 1 1 9 8 SEG 8 6 -2 5 04 266 31 S E G 1 09 -2 5 0 4 - 2 09 54 C O M 28 -2 5 0 4 - 3 197 77 D B7 375 -4 1 1 9 9 SEG 8 7 -2 5 04 254 32 S E G 1 10 -2 5 0 4 - 3 34 55 C O M 29 -2 5 0 4 - 3 322 78 Vci 500 -4 1 1 9 10 SEG 8 8 -2 5 04 241 33 S E G 1 11 -2 5 0 4 - 4 59 56 C O M 30 -2 5 0 4 - 3 447 79 C2 625 -4 1 1 9 11 SEG 8 9 -2 5 04 229 34 S E G 1 12 -2 5 0 4 - 5 84 57 C O M 31 -2 5 0 4 - 3 572 80 C1 750 -4 1 1 9 12 SEG 9 0 -2 5 04 216 35 S E G 1 13 -2 5 0 4 - 7 09 58 C O M 32 -2 5 0 4 - 3 697 81 VSS 2 875 -4 1 1 9 13 SEG 9 1 -2 5 04 204 36 S E G 1 14 -2 5 0 4 - 8 34 59 C O M 33 -2 5 0 4 - 3 822 82 V5 OU T 2 1 0 00 -4 1 1 9 14 SEG 9 2 -2 5 04 191 37 S E G 1 15 -2 5 0 4 - 9 59 60 VD D - 1 750 - 4 119 83 V5 OU T 3 1 1 25 -4 1 1 9 15 SEG 9 3 -2 5 04 179 38 S E G 1 16 -2 5 0 4 -1 084 61 OSC 2 - 1 625 - 4 119 84 V5 1 2 50 -4 1 1 9 16 SEG 9 4 -2 5 04 166 39 S E G 1 17 -2 5 0 4 -1 209 62 OSC 1 - 1 500 -4 1 1 9 85 V4 1 3 75 -4 1 1 9 17 SEG 9 5 -2 5 04 154 40 S E G 1 18 -2 5 0 4 -1 334 63 R ES E T - 1 375 -4 1 1 9 86 V3 1 5 00 -4 1 1 9 1415 SO D 18 SEG 9 6 -2 5 04 142 41 S E G 1 19 -2 5 0 4 -1 459 64 IM - 1 250 -4 1 1 9 87 V2 1 6 25 -4 1 1 9 19 SEG 9 7 -2 5 04 129 42 S E G 1 20 -2 5 0 4 -1 584 65 IE - 1 125 -4 1 1 9 88 V1 1 7 50 -4 1 1 9 20 SEG 9 8 -2 5 04 116 43 C OM 9 -2 5 0 4 -1 822 66 VSS 1 - 1 000 -4 1 1 9 89 C O M 24 2504 - 3 822 21 SEG 9 9 -2 5 04 104 44 C O M 10 -2 5 0 4 -1 947 67 R S/C S -8 75 -4 1 1 9 90 C O M 23 2504 - 3 697 22 SEG 1 0 -2 5 04 915 45 C O M 11 -2 5 0 4 -2 072 68 R W /S I D -7 50 -4 1 1 9 91 C O M 22 2504 - 3 572 23 SEG 1 0 -2 5 04 790 46 C O M 12 -2 5 0 4 -2 197 69 E /S C L K -6 25 -4 1 1 9 92 C O M 21 2504 - 3 447 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD COO RDINATE CONTINUED COORDINATE PAD PAD NO. NAME X- 93 C O M 20 2 5 04 94 C O M 19 95 COORDINATE PAD PAD Y- NO. NAME X- -3 3 2 2 116 SEG 1 1 2504 2 5 04 -3 197 117 SEG 1 2 C O M 18 2 5 04 -3 072 118 96 C O M 17 2 5 04 -2 947 97 COM 8 2 5 04 -2 822 98 COM 7 2 5 04 COORDINATE PAD PAD Y- NO. NAME X- -334 139 SEG 3 4 2504 2504 - 2 09 140 SEG 3 5 SEG 1 3 2504 -8 4 141 119 SEG 1 4 2504 40 120 SEG 1 5 2504 165 -2 697 121 SEG 1 6 2504 COORDINATE PAD PAD Y- NO. NAME X- Y- 2540 162 SEG 5 7 437 4 1 19 2504 2 6 65 163 SEG 5 8 312 4 1 19 SEG 3 6 2504 2 7 90 164 SEG 5 9 187 4 1 19 142 SEG 3 7 2504 2 9 15 165 SEG 6 0 62 4 1 19 143 SEG 3 8 2504 3 0 40 166 SEG 6 1 -6 2 4 1 19 290 144 SEG 3 9 2504 3 1 65 167 SEG 6 2 - 1 87 4 1 19 99 COM 6 2 5 04 -2 572 122 SEG 1 7 2504 415 145 SEG 4 0 2504 3 2 90 168 SEG 6 3 - 3 12 4 1 19 100 COM 5 2 5 04 -2 447 123 SEG 1 8 2504 540 146 SEG 4 1 2504 3 4 15 169 SEG 6 4 - 4 37 4 1 19 101 COM 4 2 5 04 -2 322 124 SEG 1 9 2504 665 147 SEG 4 2 2504 3 5 40 170 SEG 6 5 - 5 62 4 1 19 102 COM 3 2 5 04 -2 197 125 SEG 2 0 2504 790 148 SEG 4 3 2 1 87 4 1 19 171 SEG 6 6 - 6 87 4 1 19 103 COM 2 2 5 04 -2 072 126 SEG 2 1 2504 915 149 SEG 4 4 2 0 62 4 1 19 172 SEG 6 7 - 8 12 4 1 19 104 COM 1 2 5 04 -1 947 127 SEG 2 2 2504 1 0 40 150 SEG 4 5 1 9 37 4 1 19 173 SEG 6 8 - 9 37 4 1 19 105 COM 0 2 5 04 -1 822 128 SEG 2 3 2504 1 1 65 151 SEG 4 6 1 8 12 4 1 19 174 SEG 6 9 - 1 062 4 1 19 106 SEG 9 1 2 5 04 -1 584 129 SEG 2 4 2504 1 2 90 152 SEG 4 7 1 6 87 4 1 19 175 SEG 7 0 - 1 187 4 1 19 107 SEG 2 2 5 04 -1 459 130 SEG 2 5 2504 1 4 15 153 SEG 4 8 1 5 62 4 1 19 176 SEG 7 1 - 1 312 4 1 19 108 SEG 3 2 5 04 -1 334 131 SEG 2 6 2504 1 5 40 154 SEG 4 9 1 4 37 4 1 19 177 SEG 7 2 - 1 437 4 1 19 109 SEG 4 2 5 04 -1 209 132 SEG 2 7 2504 1 6 65 155 SEG 5 0 1 3 12 4 1 19 178 SEG 7 3 - 1 562 4 1 19 110 SEG 5 2 5 04 -1 084 133 SEG 2 8 2504 1 7 90 156 SEG 5 1 1 1 87 4 1 19 179 SEG 7 4 - 1 687 4 1 19 111 SEG 6 2 5 04 - 9 59 134 SEG 2 9 2504 1 9 15 157 SEG 5 2 1 0 62 4 1 19 180 SEG 7 5 - 1 812 4 1 19 112 SEG 7 2 5 04 - 8 34 135 SEG 3 0 2504 2 0 40 158 SEG 5 3 937 4 1 19 181 SEG 7 6 - 1 937 4 1 19 113 SEG 8 2 5 04 - 7 09 136 SEG 3 1 2504 2 1 65 159 SEG 5 4 812 4 1 19 182 SEG 7 7 - 2 062 4 1 19 114 SEG 9 2 5 04 - 5 84 137 SEG 3 2 2504 2 2 90 160 SEG 5 5 687 4 1 19 183 SEG 7 8 - 2 187 4 1 19 115 SEG 1 0 2 5 04 - 4 59 138 SEG 3 3 2504 2 4 15 161 SEG 5 6 562 4 1 19 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD DESCRIPTION PAD (NO) INPUT/ NAME DESCRIPTION INTERFACE OUTPUT VDD (60) VSS1,VSS2 (66,81) V1-V5 (88-84) Vci (78) SEG1-SEG120 (106-183, 1-42) COM0-COM33 (105-89, 43-59) OSC1,OSC2 (61,62) for logical circuit(+3V,+5V) Power supply Input Bias voltage level for LCD driving. Power supply Output Input voltage to the voltage converter to generate LCD drive voltage(Vci = 1.0 -4.5V). Segment output Segment signal output for LCD drive. LCD Output Common output Common signal output for LCD drive. LCD C1,C2 (80,79) Input (OSC1), Output (OSC2) Input RESET (63) IE (65) Input Input V5OUT2(82) Output V5OUT3(83) 0V(GND) Oscillator When use internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. External To use the voltage converter(2 times /3 times), capacitance input these pins must be connected to the external capacitance. Reset pin Initialized to Low Select pin When IE = "High", Instruction set is of selected as Table 6. instruction When IE = "Low", Instruction set is selected as set Table 10. Two times The value of Vci is converted two times. To converter use three times converter, the same output capacitance as that of C1-C2 should be connected here. Three times The value of Vci is converted three times. converter output External resistor/oscillator (OSC1) External capacitance - V5 capacitance V5 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD PAD DESCRIPTION (continued) PAD (NO) INPUT/ OUTPUT IM (64) Input RS/CS (67) Input NAME Interface mode selection Register select/ Chip select DESCRIPTION Select Interface mode with the MPU. In IM = "Low" : Serial mode, In IM = "High" : 4-bit/8-bit bus mode. In bus mode, used as register selection input. In RS/CS = "High", Data register is selected. In RS/CS = "Low", Instruction register is selected. In serial mode, used as chip selection input. INTERFACE - MPU In RS/CS = "Low", selected. When RS/CS = "High", not selected.(Low access enable) RW/SID (68) Input E/SCLK (69) Input DB0/SOD (70) Input_Output/ Output DB1-DB3 (71-73) DB4-DB7 (74-77) Input. Output In bus mode, used as read/write selection input. Read_write/ In RW/SID = "High", read operation. When Serial input data RW/SID = "Low", write operation. In serial mode, used for data input pin. MPU Read_write enable/Serial clock In bus mode, used as read_write enable signal. In serial mode, used as serial clock input pin. MPU Data bus 0 bit/Serial output data In 8-bit bus mode, used as lowest bi-directional data bit. During 4-bit bus mode, Open this pin. In serial mode, used as serial data output pin. If not in read operation, open this pin. MPU In 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode or serial mode, open these pins. MPU In 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for Busy Flag output. During serial mode, open these pins. MPU Data bus 1- 7 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FUNCTION DESCRIPTION System Interface This chip has all three kinds interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit) is selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low"). Table 2. Various kinds of operations according to RS and R/W bits. RS R/W Operation 0 0 Instruction Write operation (MPU writes Instruction code into IR) 0 1 Read Busy flag(DB7) and address counter (DB0 ~ DB6) 1 0 Data Write operation (MPU writes data into DR) 1 1 Data Read operation (MPU reads data from DR) Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High(Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Display Data RAM (DDRAM) DDRAM stores display data of maximum 96 × 8 bits (96 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Fig-1.) Fig-1. DDRAM Address 1) Display of 5-dot font width character ♦ 5-dot 1 line display In the case of 1 line display with 5-dot font, the address range of DDRAM is 00H ~ 5FH. (Refer to Fig-2) ! "! Fig-2. 1-line X 48ch. display KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ♦ 5-dot 2 line display In the case of 2 line display with 5-dot font, the address range of DDRAM is 00H ~ 2FH, 40H ~ 6FH. (refer to Fig-3) ! "! Fig-3. 2-line X 48ch. display (5-dot font width) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ♦ 5-dot 4 line display In the case of 4 line display with 5-dot font, the address range of DDRAM is 00H ~ 17H, 20H ~ 37H, 40H ~ 57H, 60H ~ 77H. (refer to Fig-4) Fig-4. 4-line X 24ch. display (5-dot font width) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) Display of 6-dot font width character ♦ 6-dot 1 line display In the case of 1 line display with 6-dot font, the address range of DDRAM is 00H ~ 5FH. (refer to Fig-5) ! "! Fig-5. 1-line X 40ch. display KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ♦ 6-dot 2 line display In the case of 2 line display with 6-dot font, the address range of DDRAM is 00H ~ 2FH, 40H ~ 6FH. (refer to Fig-6) ! "! Fig-6. 2-line X 40ch. display (6-dot font width) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ♦ 6-dot 4 line display In the case of 4 line display with 6-dot font, the address range of DDARM is 00H ~ 17H, 20H ~ 37H, 40H ~ 57H, 60H ~ 77H. (refer to Fig-7) !! " Fig-7. 4-line X 20ch. display (6-dot font width) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations. Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0~DB6 Cursor/Blink Control Circuit It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD Driver Circuit LCD Driver circuit has 34 common and 120 segment signals for LCD driving. Data from SEGRAM/CGRAM/CGROM is transferred to 120-bit segment latch serially, which is stored to 120-bit shift latch. When each common is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. In 1-line display mode, COM0 ~ COM17 have 1/17 duty, and in 2-line or 4-line mode, COM0 ~ COM33 have 1/33 duty ratio. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CGROM (Character Generator ROM) CGROM has 5 × 8-dot 240 character pattern. (refer to Table 3) Table 3. CGROM Character Code Table KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD CGRAM (Character Generator RAM) CGRAM has up to 5 × 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used. (Refer to Table 4) Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM) 1) 5 × 8 dot Character pattern !" ! !# !# ( $ $( $ $ $ $ $ $ * * ) * * ) ) , , ) , , $ %&' , KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 6 × 8 dot Character pattern #$ # ! * & + - - * #% * #% & & & + & & & & & + - + - '() 1. When BE(Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In displaying 5-dot font width, when B1 = "1", enabled dots of P0 ~ P4 will blink, and When B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen. In displaying 6-dot font width, when B1 = "1", enabled dots of P0 ~ P5 will blink, and When B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen. 2. "X" : Don't care KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD SEGRAM (Segment Icon RAM) SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17) makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data. (refer to Table 5 and Fig-8) Table 5. Relationship between SEGRAM address and display pattern * ! ! " # " # ! " ! " # # ! " # ! " # ! " # ! " # " ! # ! " # " # ! ! " # " # ! " ! " # # " " " " " ! " " " "" "# # ! " # " # # # # # # 1. B1, B0 : Blinking control bit Control Bit BE B1 B0 0 X X 1 0 0 1 0 1 1 1 X Blinking Port 5-dot font width No blink No blink D4 D4 ~ D0 6-dot font width No blink No blink D5 D5 ~ D0 2. S1~S80 : Icon pattern ON/OFF in 5-dot font width S1~S96 : Icon pattern ON/OFF in 6-dot font width 3. "X" : Don't care KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 1) 5-dot font width (FW = 0) S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 7 6 S E G 7 7 S E G 7 8 S E G 7 9 S E G 8 0 S E G 1 1 1 S E G 1 1 2 S E G 1 1 3 S E G 1 1 4 S E G 1 1 5 S E G 1 1 6 S E G 1 1 7 S E G 1 1 8 S E G 1 1 9 S E G 1 2 0 2) 6-dot font width (FW = 1) S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 9 1 S S S S S E E E E E G G G G G 9 9 9 9 9 2 3 4 5 6 S E G 1 0 9 S E G 1 1 0 S E G 1 1 1 S E G 1 1 2 S E G 1 1 3 S S S S E E E E G G G G 1 1 1 1 1 1 1 1 4 5 6 7 S S S E E E G G G 1 1 1 1 1 2 8 9 0 Fig-8. Relationship between SEGRAM and segment display KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INSTRUCTION DESCRIPTION OUTLINE To overcome the speed difference between internal clock of KS0078 and MPU clock, KS0078 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 6/10) Instruction can be divided largely four kinds, (1) KS0078 function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal RAM (3) data transfer instructions with internal RAM (4) others . The address of internal RAM is automatically increased or decreased by 1. When IE = "High", KS0078 is operated according to Instruction Set 1(Table 6) and when IE = "Low", KS0078 is operated according to Instruction Set 2(Table 10). * Note : During internal operation, Busy Flag (DB7) is read High. Busy Flag check must precede the next instruction. When you make a MPU program with checking the Busy Flag(DB7), it must be necessary 1/2Fosc for executing the next instruction by falling E signal after the Busy Flag(DB7) goes to “Low”. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (1) INSTRUCTION DESCRIPTION 1 (IE = "High") Table 6. Instruction Set 1 Instruction RE Instruction Code Description (fosc = 270 kHz) R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Clear Display Return Home Power Down Mode Entry Mode Set Execution Time X 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. 1.53ms 0 0 0 0 0 0 0 0 0 1 X Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. 1.53ms 1 0 0 0 0 0 0 0 0 1 PD Set power down mode bit. PD = "1" :power down mode set, PD = "0" :power down mode disable 39µs 0 0 0 0 0 0 0 0 1 I/D 1 0 0 0 0 0 0 0 1 1 S Assign cursor moving direction. I/D = "1" : increment, I/D = "0" : decrement and display shift enable bit. S = "1" : make display shift of the enabled lines by the DS4 -DS1 bits in the Shift Enable instruction. S = "0":display shift disable 39µs Segment bi-direction function. BID BID = "1" : Seg120 → Seg1, BID = "0" : Seg1 → Seg120. Display ON/OFF Control Extended function set 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D FW C B/W B NW Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode. 39µs 39µs KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (Table 6. continued) Instruction Code Instruction RE Description (fosc = 270 kHz) R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Cursor or Display Shift 0 0 0 0 0 0 1 S/C R/L Shift Enable 1 0 0 0 0 0 1 DS4 DS3 DS2 DS1 Scroll Enable 1 0 0 0 0 0 1 HS4 HS3 HS2 HS1 0 0 0 0 0 1 DL 1 0 0 0 0 1 N X X RE(0) DH REV Function Set DL N RE(1) BE 0 Execution Time Cursor or display shift. S/C = "1" : display shift, S/C = "0" : cursor shift, R/L = "1" : shift to right, R/L = "0" : shift to left. (when DH = "1") Determine the line for display shift . DS1 = "1/0": 1st line display shift enable/disable DS2 = "1/0": 2nd line display shift enable/disable DS3 = "1/0": 3rd line display shift enable/disable DS4 = "1/0": 4th line display shift enable/disable. (when DH = "0") Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable. Set interface data length (DL = "1" : 8-bit, DL = "0" : 4-bit), numbers of display line when NW = "0", (N = "1" : 2-line, N = "0" : 1-line), extension register, RE("0"), shift/scroll enable DH = "1" : display shift enable DH = "0" : dot scroll enable. reverse bit REV = "1" : reverse display, REV = "0" : normal display. Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable 39µs 39µs 39µs 39µs 39µs KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (Table 6. continued) Instruction Code Instruction RE Description Execution Time (fosc = 270 kHz) R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Set CGRAM Address 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter. 39µs Set SEGRAM Address 1 0 0 0 1 Set SEGRAM address in address counter. 39µs Set DDRAM Address 0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39µs Set Scroll Quantity 1 0 0 1 Set the quantity of horizontal dot scroll. 39µs X X AC3 AC2 AC1 AC0 X SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Read Busy flag and Address X 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write Data X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data X 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = “1” : busy state, BF = “0” : ready state. Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM). 0µs 43µs 43µs * Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the “E” signal after the Busy Flag (DB7) goes to “Low”. 2. “X” Don’t care KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 1) Display Clear Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home : (RE = 0) Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. site and return display to its original status, if shifted. Contents of DDRAM does not change. Return cursor to its original 3) Power Down Mode Set : (RE = 1) Power down mode enable bit set instruction. When PD = "High", it makes KS0078 suppress current consumption except the current needed for data storage by executing next three functions. 1. make the output value of all the COM/SEG ports VDD 2. make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to "Low" 3. disable voltage converter to remove the current through the divide resistor of power supply. This instruction can be used as power sleep mode. When PD = "Low", power down mode becomes disabled. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 4) Entry Mode Set ♦ (RE = 0) ./ + + + + + + + + Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the Shift Enable instruction is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not performed. ♦ (RE = 1) -. * *( * * * * * * Set the data shift direction of segment in the application set. BID : Data Shift Direction of Segment When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG120. When BID = "High", segment data shift direction is set to reverse from SEG120 to SEG1. By using this instruction, the efficiency of application board area can be raised. * The BID setting instruction is recommended to be set at the same time level of function set instruction. * DB1 bit must be set to "1". KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 5) Display ON/OFF Control ( RE = 0 ) # + Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off. 6) Extended Function Set ( RE = 1 ) FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of CGRAM.(refer to Fig-9) When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270 kHz, inversion has 370 ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 6-bit 6-bit s CGROM c ont e (5-dot ) CGRAM 8 b i t character f ont (6-dot ) 8 b i t - character - p a (CGRAM) (CGROM) Fig-9. 6-dot font width CGROM/CGRAM 7) Cursor or Display Shift (RE = 0) Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data.(Refer to Table 7) During 2-line mode display, cursor moves to the 2nd line after 48th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 24th digit of the current line. Note that display shift is performed simultaneously in all the line enabled by DS1 DS4 in the Shift Enable instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. During low power consumption mode, display shift may not be performed normally. Table 7. Shift patterns according to S/C and R/L bits S/C R/L 0 0 Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Operation 0 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 1 0 Shift all the display to the left, cursor moves according to the display 1 1 Shift all the display to the right, cursor moves according to the display KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 8) Shift/Scroll Enable (RE = 1) ♦ (DH = 0) HS : Horizontal Scroll per Line Enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8) ♦ (DH = 1) DS : Display Shift per Line Enable This instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each line. If DS1 and DS2 is set to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4) are set to "Low" (disable), no display is shifted. Table 8. Relationship between DS and COM signal Enable bit Enabled common signals Description during shift HS1/DS1 COM1 ~ COM8 HS2/DS2 COM9 ~ COM16 The part of display line that corresponds to enabled HS3/DS3 COM17 ~ COM24 common signal can be shifted. HS4/DS4 COM25 ~ COM32 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 9) Function Set ♦ (RE = 0) DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low". DH : Display shift enable selection bit. When DH = "High", enable display shift per line. When DH = "Low", enable smooth dot scroll. This bit can be accessed only when IE pin input is "High". REV : Reverse enable bit When REV = "High", all the display data are reversed. i.e. all the black and black dots become white. When REV = "Low", the display mode set normal display. white dots become KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ♦ (RE = 1) DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of shift/scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM. 10) Set CGRAM Address (RE = 0) Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 11) Set SEGRAM Address (RE = 1) Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 12) Set DDRAM Address (RE = 0) Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "5FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H" to "6FH". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "37H" in the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line. 13) Set Scroll Quantity (RE = 1) Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 9). In this case of KS0078 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots. Table 9. Scroll quantity according to HDS bits SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 0 0 0 0 0 0 Function No shift 0 0 0 0 0 1 shift left by 1-dot 0 0 0 0 1 0 shift left by 2-dot 0 0 0 0 1 1 shift left by 3-dot : : : : : : : 1 0 1 1 1 1 shift left by 47-dot 1 1 X X X X shift left by 48-dot KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 14) Read Busy Flag & Address #$ % % % % % % % This instruction shows whether KS0078 is in internal operation or not. If the resultant BF is High, the internal operation is in progress and you have to wait until BF to be Low, which by then the next instruction can be performed. In this instruction you can read the value of address counter. 15) Write data to RAM Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 16) Read data from RAM Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, the correct RAM data can be obtained from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 as in read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by read instruction. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (2) INSTRUCTION DESCRIPTION 2 (IE = "LOW") Table 10. Instruction Set 2 Instruction Code Instruction RE Description Execution Time (fosc = 270 kHz) R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Clear Display X 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. 1.53ms Return Home X 0 0 0 0 0 0 0 0 1 X Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. 1.53ms Entry Mode Set Display ON/OFF Control Extended function set Cursor or Display Shift X 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 D I/D C S B FW B/W NW S/C R/L X X Assign cursor moving direction. I/D = "1" : increment, I/D = "0" : decrement. and display shift enable bit. S = "1" :make entire display shift of all lines during DDRAM write, S = "0":display shift disable Set display/cursor/blink on/off D = "1" : display on, D = "0" : display off, C = "1" : cursor on, C = "0" : cursor off, B = "1" : blink on, B = "0" : blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1" : 6-dot font width, FW = "0" : 5-dot font width, B/W = "1" : black/white inverting of cursor enable, B/W = "0" : black/white inverting of cursor disable NW = "1" : 4-line display mode, NW = "0" : 1-line or 2-line display mode Cursor or display shift. S/C = “1” : display shift, S/C = “0” : cursor shift, R/L = “1” : shift to right, R/L = “0” : shift to left 39µs 39µs 39µs 39µs KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD (Table 10. continued) Instruction RE Instruction Code Description (fosc = 270 kHz) R R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S Scroll Enable 1 HS4 HS3 HS2 HS1 Execution Time Determine the line for horizontal smooth scroll. HS1 = "1/0" : 1st line dot scroll enable/disable HS2 = "1/0" : 2nd line dot scroll enable/disable HS3 = "1/0" : 3rd line dot scroll enable/disable HS4 = "1/0" : 4th line dot scroll enable/disable Set interface data length DL = "1" : 8-bit, DL = "0" : 4-bit numbers of display line when NW = "0", N = "1" : 2-line, N = "0" : 1-line extension register, RE("0"), 1 0 0 0 0 0 0 0 0 0 0 1 DL 1 0 0 0 0 1 Set CGRAM Address 0 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set SEGRAM Address 1 0 0 0 1 Set DDRAM Address 0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. 39µs Set Scroll Quantity 1 0 0 1 X Set the quantity of horizontal dot scroll. 39µs N RE(0) X X Function Set X DL N RE(1) BE 0 Read Busy flag and Address X 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write Data X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data X 1 1 D7 D6 D5 D4 D3 D2 D1 D0 39µs Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0" : CGRAM/SEGRAM blink enable/disable 39µs Set CGRAM address in address counter. 39µs X AC3 AC2 AC1 AC0 Set SEGRAM address in address counter. QC5 QC4 QC3 QC2 QC1 QC0 39µs Can be known whether during internal operation or not by reading BF. The contents of address counter can also be read. BF = “1” : busy state, BF = “0” : ready state. Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM). 39µs 0µs 43µs 43µs * Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the “E” signal after the Busy Flag (DB7) goes to “Low”. 2. “X” Don’t care KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 1) Display Clear Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line of the display. And entry mode is set to increment mode (I/D = "1"). 2) Return Home Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. site and return display to its original status, if shifted. Contents of DDRAM does not change. Return cursor to its original 3) Entry Mode Set Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM/SEGRAM operates identically to the DDRAM, when reading from or writing to CGRAM/SEGRAM. When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not moving. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of entire display is not performed. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 4) Display ON/OFF Control ( RE = 0 ) Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off. 5) Extended Function Set ( RE = 1 ) FW : Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of CGRAM.(Refer to Fig-10) When FW = "Low", 5-dot font width is set. B/W : Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270 kHz, inversion has 370 ms intervals. NW : 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 6-bit 6-bit s CGROM CGRAM character c f ont e (5-dot ) character f ont (6-dot ) 8 b i t - 8 b i t - p a (CGRAM) (CGROM) Fig-10. 6-dot font width CGROM/CGRAM 6) Cursor or Display Shift (RE = 0) Shift right/left cursor position or display, without writing or reading of display data. This instruction is used to correct or search display data.(Refer to Table 7) During 2-line mode display, cursor moves to the 2nd line after 48th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 24th digit of the current line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. Table 11. Shift patterns according to S/C and R/L bits S/C R/L 0 0 Shift cursor to the left, ADDRESS COUNTER is decreased by 1 Operation 0 1 Shift cursor to the right, ADDRESS COUNTER is increased by 1 1 0 Shift all the display to the left, cursor moves according to the display 1 1 Shift all the display to the right, cursor moves according to the display KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 7) Scroll Enable (RE = 1) HS : Horizontal Scroll per Line Enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8) 8) Function Set c (RE = 0) DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data by two times. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, t means 4-line mode independent of N bit. RE : Extended function registers enable bit At this instruction, RE must be "Low". KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD d (RE = 1) DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, it is required to transfer 4-bit data twice. N : Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", 1-line display mode is set. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, 4-line mode independent of N bit. RE : Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll enable instruction and BE bits of function set register can be accessed. BE : CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM. 9) Set CGRAM Address (RE = 0) Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 10) Set SEGRAM Address (RE = 1) Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 11) Set DDRAM Address (RE = 0) Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "5FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "2FH", and DDRAM address in the 2nd line is from "40H" to "6FH". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "17H" in the 1st line, from "20H" to "37H" in the 2nd line, from "40H" to "57H" in the 3rd line and from "60H" to "77H" in the 4th line. 12) Set Scroll Quantity (RE = 1) Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 12). In this case of KS0078 execute dot smooth scroll from 1 to 48 dots. Table 12. Scroll quantity according to HDS bits SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Function 0 0 0 0 0 0 No shift 0 0 0 0 0 1 shift left by 1-dot 0 0 0 0 1 0 shift left by 2-dot 0 0 0 0 1 1 shift left by 3-dot : : : : : : : 1 0 1 1 1 1 shift left by 47-dot 1 1 X X X X shift left by 48-dot KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 13) Read Busy Flag & Address This instruction shows whether KS0078 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and should wait until BF to become “Low”. which by then the next instruction can be performed. In this instruction value of address counter can also be read. 14) Write data to RAM Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 15) Read data from RAM Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, as the direction of AC is not determined. If the RAM data is read severa l times without RAM address set instruction before read operation, the correct RAM data from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, AC is increased/decreased by 1 like read operation after this. In this time, AC indicates the next address position, but the previous data can only be read by read instruction. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INTERFACE WITH MPU KS0078 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. Hence, both types of 4 or 8-bit MPU can be used. In case of 4-bit bus mode, data transfer is performed by twice to transfer 1 byte data. (1) When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by twice. Busy Flag outputs "High" after the second transfer is ended. (2) When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7. (3) If IM is set to "Low", serial transfer mode is set. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Interface with MPU in Bus Mode 1) Interface with 8-bits MPU If 8-bits MPU is used, KS0078 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7 need to interface each other. Example of timing sequence is shown below. !"!# $ !"!# Fig 11. Example of 8-bit Bus Mode Timing Sequence 2) Interface with 4-bits MPU If 4-bits MPU is used, KS0078 can connect directly with this. In this case, port E, RS, R/W and DB4 to DB7 need to interface each other. The transfer is performed by twice. Example of timing sequence is shown below. RS R/W E Internal signal DB7 Internal operation D7 D3 INSTRUCTION Busy AC3 Busy Flag Check No Busy AC3 Busy Flag Check D7 D3 INSTRUCTION Fig 12. Example of 4-bit Bus Mode Timing Sequence KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD Interface with MPU in Serial Mode When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing transfer clock), SID (serial input data), and SOD (serial output data), are used. If KS0078 is to be used with other chips, chip select port (CS) can be used. By setting CS to "Low", KS0078 can receive SCLK input. If CS is set to "High", KS0078 reset the internal transfer counter. Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write control bit (R/W), register selection bit (RS), and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are detected by KS0078, it makes serial transfer counter reset and ready to receive next information. The next input data are register selection bit that determine which register will be used, and read write control bit that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (Refer to Fig 13. Fig 14) (1) Write Operation (R/W = 0) After start byte is transferred from MPU to KS0078, 8-bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. To transfer several bytes continuously without changing RS bit and R/W bit, start byte transfer is needed only at first starting time. i.e., after first start byte is transferred, real data succeeding can be transferred. (2) Read Operation (R/W = 1) After start byte is transferred to KS0078, MPU can receive 8-bit data through the SOD port at a time from the LSB. Wait time is needed to insert between start byte and data reading, as internal reading from RAM requires some delay. Continuous data reading is possible such as serial write operation. It also needs only one start bytes, only if you insert some delay between reading operations of each byte. During the reading operation, KS0078 observes succeeding 5 "High" from MPU. If it is detected, KS0078 restarts serial operation at once and ready to receive RS bit. So in continuous reading operation, SID port must be "Low". KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD . / ! 0% ! 0% 0 0% "# $% '(( & & / ! 0% ! 0% 0 0% / ! /%% )! "# $% '(( Fig 13. Timing Diagram of Serial Data Transfer KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD * * * * * * * +, +, - . +, - . - . * - . - . - . Fig 14. Timing Diagram of Continuous Data Transfer KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD APPLICATION INFORMATION ACCORDING TO LCD PANEL 1) LCD Panel : 48 character x 1 line format (5-dot font,1/17 duty) 2) LCD Panel : 48 character x 2 line format (5-dot font, 1/33 duty) KS0078 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 3) LCD Panel : 24 character x 4 line format (5-dot font, 1/33 bias) KS0078 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 4) LCD Panel : 20 character x 4 line format (6-dot font, 1/33 bias) KS0078 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING 1) Initializing by Internal Reset Circuit When the power is turned on, KS0078 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. c Display Clear instruction Write "20H" to all DDRAM d Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode RE = 0 : Extension register disable BE = 0 : CGRAM/SEGRAM blink OFF DH = 0 : Horizontal scroll enable REV = 0 : Normal display (Not reversed display) e Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF f Set Entry Mode instruction I/D = 1 : Increment by 1 S = 0 : No entire display shift BID = 0 : Normal direction segment port g Set Extension Function instruction FW = 0 : 5-dot font width character display B/W = 0 : Normal cursor (8th line) NW = 0 : Not 4-line display mode, 2-line mode is set because of N("1") h Enable Shift instruction HS = 0000 : Scroll per line disable DS = 0000 : Shift per line disable i Set scroll Quantity instruction SQ = 000000 : Not scroll 2) Initializing by Hardware RESET input When RESET pin = "Low", KS0078 can be initialized like the case of power on reset. During the power on reset operation, this pin is ignored. KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD INITIALIZING BY INSTRUCTION 1) 8-bit interface mode Power on Condition: 270 kHz Wait for more than 20 ms after VDD rises to 4.5V (DL=“1”) Function set DL RS 0 RW DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 DL (1) N 0 x x N 0 4-bit interface 1 8-bit interface 0 1-line mode 1 2-line mode Wait for more than 39 µs D Dsplay ON/OFF Control RS 0 RW DB7 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 D C C B B 0 display off 1 display on 0 cursor off 1 cursor on 0 blink off 1 blink on Wait for more than 39 µs Clear Dsplay RS RW DB7 0 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 Wait for more than Entry Mode Set RS 0 I/D RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S S 0 decrement mode 1 increment mode 0 entire shift off 1 entire shift on Initialization end KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) 4-bit interface mode Power on Condition: 270 kHz Wait for more than 20 ms after VDD rises to 4.5V (DL=“0”) Function set DL RS 0 RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL (0) x x x x N 0 4-bit interface 1 8-bit interface 0 1-line mode 1 2-line mode Wait for more than 39µs Function set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 x x x x 0 0 N x x x x x x x Wait for more than 39µs D Dsplay ON/OFF Control RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 x x x x 0 0 1 D C B x x x x C B 0 display off 1 display on 0 cursor off 1 cursor on 0 blink off 1 blink on Wait for more than 39µs Clear Dsplay RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 x x x x 0 0 0 0 0 1 x x x x Wait for more than 1.53ms Entry ModeSet RS I/D RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 x x x x 0 0 0 1 I/D S x x x x S 0 decrement mode 1 increment mode 0 entire shift off 1 entire shift on Initialization end KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE 1) IE = "Low" ! " # $$ %& %'( *$ +,!- ,- ./0 ) ) # 1231** & #3&# . 4 $5 '4 '4 ' '4 4 + '4 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ! !"#$ %& ! !%& '% ()$ () !"#$ !%& )*# + KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD '4 + '4 6 '4 &# # "7 &# #"7 7 ) ) '4 + 5 ) & # KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 2) IE = "High" ! " # $$ %$ &'!( )*+ )1 %$ '2( ' %$ )*+ # ,-,%% . #.# /0 KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ! KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD " #$%$ &'(()* '(() #$%$ &'(() KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD %&-## ()*# .//01.//0 2 )-) (.//0 , ! !"#$ %& !"#$ !%& #& ! !"#$ %& !"#$ !%& #& ! !"#$ %& !"#$ !%& #& ! !"#$ %& !"#$ !%& #& KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD % ' *+ $ ! % ,'- ( .//012.//0 $ % &' ( ) $ ! ! % &' ( ) $ ! ! % ' *+ $ ! % ,'- ( .//012.//0 $ KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ) *+ # %'' $ %& " # '' ( (& !" # !" # !" # KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD FRAME FREQUENCY 1) 1/17 duty cycle 000 000 V DD #1 Item Display Font Width 5-dot font width 6-dot font width 1-line selection period 240 clocks 288 clocks Frame frequency 66.2Hz 55.1Hz * fosc = 270 kHz (1 clock = 3.7) 2) 1/33 duty cycle 333 333 V DD &4 Item Display Font Width 5-dot font width 6-dot font width 1-line selection period 120 clocks 144 clocks Frame frequency 68.2Hz 56.8Hz * fosc = 270 kHz (1 clock = 3.7) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD POWER SUPPLY FOR DRIVING LCD PANEL 1) When an external power supply is used 2) When an internal booster is used (Boosting twice) (Boosting three times) VDD VDD + VCI - GND V1 C1 V2 C2 V3 V5OUT2 V4 V5OUT3 V5 1µF + 1 µF + * VDD R + VCI R - GND V1 C1 V2 C2 V3 V5OUT2 V4 V5OUT3 V5 1 µF + R0 R R 1µF + 1 µF + Can be detached If not using powr down mode VDD R R R0 R R Can be detached If not using powr down mode 1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three times. 2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice. 3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to Table 13) Table 13. Duty Ratio and Power Supply for LCD Driving Item Data Number of lines 1 2 or 4 Duty ration 1/17 1/33 BIas 1/5 1/6.7 R R R R0 R 2.7R Divided resistance KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD MAXIMUM ABSOLUTE RATE Characteristic Symbol Value Unit Power Supply Voltage (1) VDD -0.3 to +7.0 V Power Supply Voltage (2) VLCD VDD -15.0 to VDD +0.3 V Input Voltage VIN -0.3 to VDD +0.3 V Operating Temperature TOPR -30 to +85 °C Storage Temperature TSTG -55 to +125 °C * Voltage greater than above may damage to the circuit (VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5) KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7V to 5.5V, Ta=-30 to +85°C) Characteristic Symbol Condition Min Operating Voltage Supply Current Input Voltage (1) VIH1 (Except OSC1) VIL1 Input Voltage (2) VIH2 Typ Max VDD - IDD Internal oscillation or external clock. Unit 2.7 - 5.5 V - 0.15 0.3 mA - 0.7VDD - VDD VDD=2.7 to 3.0 -0.3 - 0.2VDD (VDD=3.0V,fosc=270KHz) VDD=3.0 to 5.5 -0.3 - 0.6 - 0.7VDD - VDD (OSC1) VIL2 - - - 0.2VDD Output Voltage (1) VOH1 IOH=-0.1mA 0.75VDD - - (DB0 to DB7) VOL1 IOL=0.1 mA - - 0.2VDD Output Voltage(2) VOH2 IO=-40 µA 0.8VDD - - (except DB0 to DB7) VOL1 IO=40 µA - - 0.2VDD Voltage Drop VdCOM IO= ± 0.1mA - - 1 VdSEG - V V V V - - 1 Input Leakage Current IIL VIN=0V to VDD -1 - 1 Low Input Current IIN VIN=0V, VDD=3V -10 -50 -120 Internal Clock fOSC Rf=91kΩ ± 2% 190 270 350 KHz 125 270 410 KHz - 45 50 55 % - - 0.2 µs Ta = 25 °C, C=1 µF, -3.0 -4.2 - V -4.3 -5.1 - µA (PULL UP) (external Rf) External Clock (VDD=5V) fEC duty tR, tF Voltage Converter Out2 VOUT2 (Vci = 4.5V) Voltage Converter Out3 IOUT = 0.25mA, VOUT3 fOSC=270KHz (Vci = 2.7V) Voltage Converter Input Vci LCD Driving Voltage VLCD VDD-V5 1.0 - 4.5 1/5 Bias 3.0 - 13.0 1/6.7 Bias 3.0 - 13.0 V KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD AC Characteristics (VDD = 4.5 to 5.5V, Ta=-30 to +85 °C) Mode Item Symbol Min Typ Max E Cycle Time tc, 500 - - E Rise / Fall Time tR, tF - - 20 E Pulse Width (High, Low) tw 230 - - (1) Write Mode R/W and RS Setup Time tsu1 40 - - (refer to Fig-15) R/W and RS Hold Time tH1 10 - - Data Setup Time tsu2 60 - - Data Hold Time tH2 10 - - E Cycle Time tc 500 - - E Rise / Fall Time tR,tF - - 20 E Pulse Width (High, Low) tw 230 - - (2) Read Mode R/W and RS Setup Time tsu 40 - - (refer to Fig-16) R/W and RS Hold Time tH 10 - - Data Output Delay Time tD - - 160 Data Hold Time tDH 5 - - Serial Clock Cycle Time tc 0.5 - 20 Serial Clock Rise/Fall Time tR,tF - - 50 Serial Clock Width (High, Low) tw 200 - - (3) Serial Chip Select Setup Time tsu1 60 - - Interface Mode Chip Select Hold Time tH1 20 - - (refer to Fig-17) Serial Input Data Setup Time tsu2 100 - - Serial Input Data Hold Time t H2 100 - - Serial Output Data Delay Time tD - - 160 Serial Output Data Hold Time tDH 5 - - Unit ns ns µs ns KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD AC Characteristics (continued) (VDD=2.7 to 4.5V, Ta=-30 to +85 °C) Mode Item Symbol Min Typ Max E Cycle Time tc, 1000 - - E Rise / Fall Time tR, tF - - 25 E Pulse Width (High, Low) tw 450 - - (4) Write Mode R/W and RS Setup Time tsu1 60 - - (refer to Fig-15) R/W and RS Hold Time th1 20 - - Data Setup Time tsu2 195 - - Data Hold Time tH2 10 - - E Cycle Time tc 1000 - - E Rise / Fall Time tR,tF - - 25 E Pulse Width (High, Low) tw 450 - - (5) Read Mode R/W and RS Setup Time tsu 60 - - (refer to Fig-16) R/W and RS Hold Time tH 20 - - (6) Serial Data Output Delay Time tD - - 360 Data Hold Time tDH 5 - - Serial Clock Cycle Time tc 1 - 20 Serial Clock Rise/Fall Time tR,tF - - 50 Serial Clock Width (High, Low) tw 400 - - Chip Select Setup Time tsu1 60 - - Interface Mode Chip Select Hold Time tH1 20 - - (refer to Fig-17) Serial Input Data Setup Time tsu2 200 - - Serial Input Data Hold Time t H2 200 - - Serial Output Data Delay Time tD - - 360 Serial Output Data Hold Time tDH 5 - - Unit ns ns µs ns KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD VIH1 RS VIL1 tH1 tsu1 R/W VIL1 VIL1 tH1 tw tF VIH1 E VIH1 VIL1 VIL1 VIL1 tH2 tSU2 tR VIH1 DB0~DB7 VIH1 Valid Data VIL1 VIL1 tc Fig-15. Write Mode VIH1 RS VIL1 tH tSU R/W VIH1 VIH1 tH tW tF VIH1 E VIL1 tR DB0~DB7 VIH1 VIL1 VIL1 tDH tD VOH1 VOL1 Valid Data VOH1 VOL1 tC Fig-16. Read Mode KS0078 34COM/120SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD tC CS VIL1 tSU1 VIH1 VIL1 SCLK tW tR tF VIH1 VIL1 VIH1 VIL1 tSU2 VIL1 tH1 tW VIH1 VIL1 tH2 SID tDH tD VOH1 VOL1 SOD Fig-17. Serial Interface Mode Reset Timing (VDD = 2.7 to 5.5V, Ta = -30 to +85) Item Symbol Min Typ Max Unit Reset low level width (Refer to Fig-18) tRES 10 - - ms tRES RESET VIL1 VIL1 Fig-18. Reset Timing Diagram