Ordering number : EN8302A LC875J64C LC875J56C LC875J48C CMOS IC ROM 64K/56K/48K byte, RAM 2048 byte on-chip 8-bit 1-chip Microcontroller Overview The SANYO LC875J64C/56C/48C are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64K/56K/48K byte ROM, 2048 byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 26-source 10-vector interrupt feature. Features ROM • 65536 × 8-bits • 57344 × 8-bits • 49152 × 8-bits (LC875J64C) (LC875J56C) (LC875J48C) RAM • 2048 × 9-bits (LC875J64C/56C/48C) Minimum Bus Cycle • 83.3ns (12MHz) VDD=3.0 to 5.5V • 125ns (8MHz) VDD=2.5 to 5.5V • 500ns (2MHz) VDD=2.2 to 5.5V Note : The bus cycle time here refers to the ROM read speed. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.03 20707HKIM 20060222-S00014 No.8302-1/23 LC875J64C/875J56C/875J48C Minimum Instruction Cycle Time • 250ns (12MHz) VDD=3.0 to 5.5V • 375ns (8MHz) VDD=2.5 to 5.5V • 1.5µs (2MHz) VDD=2.2 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units • Normal withstand voltage input port • Dedicated oscillator ports • Reset pins • Power pins 46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn, PWM2, PWM3, XT2) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels Mode 1: 16-bit timer with an 8-bit prescaler * Timer 8 is not supported in this version of Emulator. Please use on-chip-debugger (only supported in flash-ROM version) for debugging when developing software. • Base Timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) No.8302-2/23 LC875J64C/875J56C/875J48C UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator AD Converter: 8-bits × 11 channels PWM: Multifrequency 12-bit PWM × 2 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts • 26 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/UART1 receive/T8L/T8H 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM2, PWM3 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (list of interrupt source flag function) 3) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the diagram above). Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions • 16-bits × 8-bits (5 tCYC execution time) • 24-bits × 16-bits (12 tCYC execution time) • 16-bits ÷ 8-bits (8 tCYC execution time) • 24-bits ÷ 16-bits (12 tCYC execution time) No.8302-3/23 LC875J64C/875J56C/875J48C Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • Frequency variable RC oscillation circuit (internal): For system clock For system clock, with internal Rf For low-speed system clock, with internal Rf For system clock System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz). Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit ROM Correction Function • Executes the correction program on detection of a match with the program counter value. • Correction program area size : 128 bytes Package Form • QIP64E (14 × 14): • TQFP64J (10 × 10): Development Tools • Evaluation chip: • Emulator: • On-chip debugger: Lead-free type Lead-free type LC87EV690 EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP ICE-B877300 + SUB875800 + POD64QFP or POD64SQFP TCB87-TypeA or TCB87-TypeB + LC87F5JC8A No.8302-4/23 LC875J64C/875J56C/875J48C Package Dimensions Package Dimensions unit : mm (typ) 3159A unit : mm (typ) 3310 12.0 17.2 14.0 33 64 17 17 1 0.35 0.15 1.2 MAX (2.7) 0.125 (1.25) (1.0) SANYO : TQFP64J(10X10) 0.1 3.0max 0.18 (1.0) 0.8 16 0.5 16 0.1 1 0.5 32 17.2 14.0 64 49 10.0 32 49 33 12.0 48 0.8 10.0 48 SANYO : QIP64E(14X14) No.8302-5/23 LC875J64C/875J56C/875J48C PB1 PB0 VSS3 VDD3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 P86/AN6 P85/AN5 P84/AN4 P83/AN3 Pin Assignment 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 49 32 PB2 P71/INT1/T0HCP/AN9 50 31 PB3 P72/INT2/T0IN 51 30 PB4 P73/INT3/T0IN 52 29 PB5 RES 53 28 PB6 XT1/AN10 54 27 PB7 XT2/AN11 55 26 P27/INT5/T1IN VSS1 56 25 P26/INT5/T1IN CF1 57 24 P25/INT5/T1IN CF2 58 23 P24/INT5/T1IN/INT7/T0HCP1 LC875J64C LC875J56C LC875J48C VDD1 59 22 P23/INT4/T1IN P80/AN0 60 21 P22/INT4/T1IN P81/AN1 61 20 P21/URX/INT4/T1IN 8 9 10 11 12 13 14 15 16 P05/CKO 7 P04 6 P03 5 P02 4 P01 3 P00 2 VSS2 1 VDD2 P06/T6O PWM3 17 PWM2 64 P17/T1PWMH/BUZ P11/SI0/SB0 P16/T1PWML P07/T7O P15/SCK1 P20/UTX/INT4/T1IN/INT6/T0LCP1 18 P14/SI1/SB1 19 63 P13/SO1 62 P12/SCK0 P82/AN2 P10/SO0 Top view SANYO: QIP64E(14×14) “Lead-free Type” SANYO: TQFP64J(10×10) “Lead-free Type” No.8302-6/23 LC875J64C/875J56C/875J48C System Block Diagram Interrupt control IR ROM correct Standby control CF MRC ROM Clock generator RC PLA X’tal PC SIO0 Bus interface SIO1 Port 0 ACC Timer 0 Port 1 B register Timer 1 Port 2 C register Timer 4 Port 7 ALU Timer 5 Port 8 Timer 6 ADC PSW Timer 7 INT0 to 7 Noise filter RAR Timer 8 Port B RAM Base timer Port C Stack pointer PWM2/3 UART1 Watchdog timer No.8302-7/23 LC875J64C/875J56C/875J48C Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 I/O Description Option - - Power supply pin No - + Power supply pin No • 8-bit I/O port Yes VDD2 VDD3 Port 0 I/O • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Shared pins P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O Yes • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P24: INT7 input/timer 0H capture 1 input Interrupt acknowledge type Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising & H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling Continued on next page. No.8302-8/23 LC875J64C/875J56C/875J48C Continued from preceding page. Pin Name Port 7 I/O I/O Description Option No • 4-bit I/O port • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input port: AN8 (P70), AN9 (P71) Interrupt acknowledge type Port 8 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • 7-bit I/O port No • I/O specifiable in 1-bit units P80 to P86 • Shared pins AD converter input port : AN0 (P80) to AN6 (P86) PWM2, PWM3 I/O • PWM2 and PWM3 output ports No • General-purpose I/O available Port B I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PB0 to PB7 • Pull-up resistors can be turned on and off in 1-bit units. Port C I/O • 8-bit I/O port Yes • I/O specifiable in 1-bit units PC0 to PC7 • Pull-up resistors can be turned on and off in 1-bit units. RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin No • Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. XT2 I/O • 32.768kHz crystal oscillator output pin No • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. CF1 Input CF2 Output Ceramic resonator input pin No Ceramic resonator output pin No No.8302-9/23 LC875J64C/875J56C/875J48C Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type P00 to P07 1-bit 1 P10 to P17 1-bit P20 to P27 1-bit Output Type Pull-up Resistor CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable 1 CMOS Programmable 2 Nch-open drain Programmable P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable P80 to P86 - No Nch-open drain No PWM2, PWM3 - No CMOS No PB0 to PB7 1-bit 1 CMOS Programmable 2 Nch-open drain Programmable PC0 to PC7 1-bit 1 CMOS Programmable 2 Nch-open drain Programmable Input for 32.768kHz crystal oscillator No XT1 - No (Input only) XT2 - No Output for 32.768kHz crystal oscillator No (Nch-open drain when in general-purpose output mode) Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). *1: Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.8302-10/23 LC875J64C/875J56C/875J48C Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Maximum supply VDD max VDD1, VDD2, VDD3 Input voltage VI(1) XT1, CF1 Input/output voltage VIO(1) Ports 0, 1, 2 VDD1=VDD2=VDD3 voltage min typ max -0.3 +6.5 -0.3 VDD+0.3 unit V Ports 7, 8 -0.3 Ports B, C VDD+0.3 PWM2, PWM3, XT2 Peak output IOPH(1) current High level output current Mean output CMOS output select Per 1 applicable pin IOPH(2) PWM2, PWM3 Per 1 applicable pin -20 P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2 CMOS output select Ports B, C Per 1 applicable pin IOMH(2) PWM2, PWM3 Per 1 applicable pin IOMH(3) P71 to P73 Per 1 applicable pin Total output ΣIOAH(1) P71 to P73 Total of all applicable pins current ΣIOAH(2) Port 1 Total of all applicable pins PWM2, PWM3 ΣIOAH(3) Ports 0, 2 Total of all applicable pins ΣIOAH(4) Ports 0, 1, 2 Total of all applicable pins PWM2, PWM3 Peak output -10 IOPH(3) current (Note 1-1) Ports 0, 1, 2 Ports B, C -7.5 -15 -3 -10 -25 -25 -45 ΣIOAH(5) Port B Total of all applicable pins -25 ΣIOAH(6) Port C Total of all applicable pins -25 ΣIOAH(7) Ports B, C Total of all applicable pins -45 IOPL(1) P02 to P07 Per 1 applicable pin current Ports 1, 2 20 Ports B, C PWM2, PWM3 IOPL(2) P00, P01 Per 1 applicable pin IOPL(3) Ports 7, 8 Per 1 applicable pin 30 10 XT2 Low level output current Mean output IOML(1) P02 to P07 current Ports 1, 2 (Note 1-1) Ports B, C mA Per 1 applicable pin 15 PWM2, PWM3 IOML(2) P00, P01 Per 1 applicable pin IOML(3) Ports 7, 8 Per 1 applicable pin 20 7.5 XT2 Total output ΣIOAL(1) current Port 7 Total of all applicable pins 15 P83 to P86, XT2 ΣIOAL(2) P80 to P82 Total of all applicable pins ΣIOAL(3) Ports 7, 8 Total of all applicable pins 15 20 XT2 ΣIOAL(4) Port 1 Total of all applicable pins 45 PWM2, PWM3 ΣIOAL(5) Ports 0, 2 Total of all applicable pins ΣIOAL(6) Ports 0, 1, 2 Total of all applicable pins 45 80 PWM2, PWM3 Power dissipation ΣIOAL(7) Port B Total of all applicable pins 45 ΣIOAL(8) Port C Total of all applicable pins 45 ΣIOAL(9) Ports B, C Total of all applicable pins Pd max QIP64E (14 × 14) Ta=-30 to +70°C 80 355 TQFP64J (10 × 10) Operating ambient Topr temperature Storage ambient Tstg temperature mW 255 -30 +70 -55 +125 °C Note 1-1: The mean output current is a mean value measured over 100ms. No.8302-11/23 LC875J64C/875J56C/875J48C Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Operating VDD(1) VDD1=VDD2=VDD3 supply voltage Memory VHD VDD1=VDD2=VDD3 0.245µs≤tCYC≤200µs typ max 3.0 unit 5.5 0.367µs≤tCYC≤200µs 2.5 5.5 1.47µs≤tCYC≤200µs 2.2 5.5 2.0 5.5 RAM and register contents sustained in HOLD mode. sustaining min supply voltage High level input VIH(1) voltage Ports 1, 2 P71 to P73 2.2 to 5.5 P70 port input/ 0.3VDD VDD +0.7 interrupt side VIH(2) Ports 0, 8, B, C 2.2 to 5.5 PWM2, PWM3 VIH(3) Port 70 watchdog timer side VIH(4) XT1, XT2, CF1 RES Low level input VIL(1) voltage Ports 1, 2 P71 to P73 P70 port input/ interrupt side VIL(2) Ports 0, 8, B, C PWM2, PWM3 VIL(3) Port 70 watchdog timer side VIL(4) XT1, XT2, CF1 RES Instruction cycle tCYC time (Note 2-1) External system FEXCF(1) CF1 clock frequency • CF2 pin open 0.3VDD +0.7 VDD 2.2 to 5.5 0.9VDD VDD 2.2 to 5.5 0.75VDD VDD 4.0 to 5.5 VSS 2.2 to 4.0 VSS 4.0 to 5.5 VSS 2.2 to 4.0 VSS 2.2 to 5.5 VSS 2.2 to 5.5 VSS 0.25VDD 3.0 to 5.5 0.245 200 2.5 to 5.5 0.367 200 2.2 to 5.5 1.47 200 3.0 to 5.5 0.1 12 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 2 V 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 µs • System clock frequency division ratio=1/1 • External system clock duty =50 ± 5% • CF2 pin open 3.0 to 5.5 0.2 24.4 • System clock frequency 2.5 to 5.5 0.2 16 2.2 to 5.5 0.2 4 division ratio=1/2 Oscillation FmCF(1) CF1, CF2 frequency range (Note 2-2) 12MHz ceramic oscillation See Fig. 1. FmCF(2) CF1, CF2 8MHz ceramic oscillation See Fig. 1. FmCF(3) CF1, CF2 4MHz ceramic oscillation See Fig. 1. FmRC Internal RC oscillation FmMRC Frequency variable RC oscillation source oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig. 2. MHz 3.0 to 5.5 12 2.5 to 5.5 8 2.2 to 5.5 4 2.2 to 5.5 0.3 1.0 2.2 to 5.5 16 2.2 to 5.5 32.768 2.0 kHz Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. No.8302-12/23 LC875J64C/875J56C/875J48C Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] High level input IIH(1) current IIH(2) Ports 0, 1, 2 Output disabled Ports 7, 8 Pull-up resistor off Ports B, C RES VIN=VDD (Including output Tr's off leakage PWM2, PWM3 current) XT1, XT2 IIH(3) CF1 VIN=VDD IIL(1) Ports 0, 1, 2 Output disabled Ports 7, 8 Pull-up resistor off Ports B, C RES VIN=VSS (Including output Tr's off leakage PWM2, PWM3 current) current IIL(2) XT1, XT2 typ For input port specification VIN=VSS 1 2.2 to 5.5 1 2.2 to 5.5 15 2.2 to 5.5 -1 2.2 to 5.5 -1 CF1 VIN=VSS 2.2 to 5.5 -15 High level output VOH(1) Ports 0, 1, 2 IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) Ports B, C IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(7) IOH=-1.6mA 3.0 to 5.5 VDD-0.4 VOH(8) IOH=-1mA 2.2 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 0.4 VOH(3) VOH(4) P71 to P73 VOH(5) VOH(6) PWM2, PWM3 Low level output VOL(1) Ports 0, 1, 2 voltage VOL(2) Ports B, C VOL(3) Hysteresis voltage PWM2, PWM3 IOL=1.6mA 3.0 to 5.5 2.2 to 5.5 0.4 3.0 to 5.5 0.4 VOL(4) Ports 7, 8 IOL=1.6mA VOL(5) XT2 IOL=1mA 2.2 to 5.5 0.4 VOL(6) P00, P01 IOL=30mA 4.5 to 5.5 1.5 VOL(7) IOL=5mA 3.0 to 5.5 0.4 VOL(8) IOL=2.5mA 2.2 to 5.5 VOH=0.9VDD 4.5 to 5.5 15 35 80 2.2 to 5.5 18 50 150 Rpu(1) Ports 0, 1, 2, 7 Rpu(2) Ports B, C VHYS RES 2.2 to 5.5 CP All pins µA V IOL=1mA Ports 1, 2, 7 Pin capacitance unit 2.2 to 5.5 IIL(3) Pull-up resistance max For input port specification VIN=VDD Low level input min 0.4 0.1 VDD kΩ V For pins other than that under test: VIN=VSS f=1MHz 2.2 to 5.5 10 pF Ta=25°C No.8302-13/23 LC875J64C/875J56C/875J48C Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock VDD[V] Frequency tSCK(1) Low level tSCKL(1) SCK0(P12) See Fig. 6. tSCKH(1) 2.2 to 5.5 pulse width tSCKHA(1) tCYC 4 • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected 4/3 • See Fig. 6. Output clock Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 2.2 to 5.5 pulse width tSCKHA(2) 1/2 • Continuous data transmission/reception mode tSCKH(2) • CMOS output selected +2tCYC • See Fig. 6. Data setup time Serial input unit 1 • Continuous data transmission/reception mode tsDI(1) SB0(P11), SI0(P11) Data hold time tSCKH(2) +(10/3) tCYC tCYC • Must be specified with respect 0.03 to rising edge of SIOCLK. • See Fig. 6. thDI(1) 2.2 to 5.5 0.03 Input clock Output delay tdD0(1) time SO0(P10), SB0(P11) • Continuous data (1/3)tCYC transmission/reception mode +0.05 • (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode tdD0(3) µs 1tCYC • (Note 4-1-3) 2.2 to 5.5 Output clock Serial output max 1 • See Fig. 6. Serial clock typ 2 pulse width High level min +0.05 (Note 4-1-3) (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. No.8302-14/23 LC875J64C/875J56C/875J48C 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Symbol Pin/Remarks Specification Conditions Input clock Frequency tSCK(3) Low level tSCKL(3) SCK1(P15) min See Fig. 6. High level Frequency tSCKH(3) tSCK(4) SCK1(P15) • CMOS output selected tSCKL(4) tSCK 1/2 Serial input SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. 0.03 • See Fig. 6. Data hold time thDI(2) 0.03 Output delay time Serial output C 1/2 tSCKH(4) tsDI(2) tCY 2 pulse width Data setup time unit 2 pulse width High level max 1 • See Fig. 6. Low level typ 1 pulse width pulse width Output clock Serial clock VDD[V] tdD0(4) SO1(P13), SB1(P14) µs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain (1/3)tCYC +0.05 output mode. • See Fig. 6. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.8302-15/23 LC875J64C/875J56C/875J48C Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 INT2(P72), min typ max unit are enabled. INT4(P20 to P23), 2.2 to 5.5 1 2.2 to 5.5 2 2.2 to 5.5 64 INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) INT3(P73) when • Interrupt source flag can be set. tPIL(2) noise filter time • Event inputs for timer 0 are enabled. tCYC constant is 1/1 tPIH(3) INT3(P73) when • Interrupt source flag can be set. tPIL(3) noise filter time • Event inputs for timer 0 are enabled. constant is 1/32 tPIH(4) INT3(P73) when • Interrupt source flag can be set. tPIL(4) noise filter time • Event inputs for timer 0 are enabled. 2.2 to 5.5 256 Resetting is enabled. 2.2 to 5.5 200 constant is 1/128 tPIL(5) RES µs AD Converter Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Resolution N AN0(P80) to Absolute ET AN6(P86), Conversion TCAD time AN9(P71), AD conversion time=32×tCYC AN10(XT1), (when ADCR2=0) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 VAIN 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 max unit 8 bit ±1.5 3.0 to 5.5 AN11(XT2) Analog input typ 3.0 to 5.5 (Note 6-1) AN8(P70), accuracy min 15.68 97.92 (tCYC= (tCYC= 0.49µs) 3.06µs) 23.52 97.92 (tCYC= (tCYC= 0.735µs) 3.06µs) 18.82 97.92 (tCYC= (tCYC= 0.294µs) 1.53µs) 47.04 97.92 (tCYC= (tCYC= 0.735µs) 1.53µs) VSS VDD 1 -1 LSB µs V µA Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.8302-16/23 LC875J64C/875J56C/875J48C Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/ VDD [V] • FmCF=12MHz consumption VDD1 =VDD2 current =VDD3 • FmX’tal=32.768kHz crystal Normal mode IDDOP(1) Specification Conditions Remarks min typ max unit ceramic oscillation mode 4.5 to 5.5 8 13.5 3.0 to 3.6 4.5 8 4.5 to 5.5 9.5 16 3.0 to 3.6 5.2 8.8 4.5 to 5.5 5.5 9 3.0 to 3.6 3.1 5.6 2.5 to 3.0 2.2 3.8 4.5 to 5.5 2 3.2 3.0 to 3.6 1 2 2.2 to 3.0 0.7 1.4 4.5 to 5.5 0.55 2.1 3.0 to 3.6 0.3 1.4 2.2 to 3.0 0.2 1 4.5 to 5.5 1.2 3.5 3.0 to 3.6 0.65 2.2 2.2 to 3.0 0.4 1.6 4.5 to 5.5 27 65 3.0 to 3.6 11 45 2.2 to 3.0 7 32 oscillation mode (Note 7-1) • System clock set to 12MHz side IDDOP(2) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(3) • CF1=24MHz external clock • FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side IDDOP(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(5) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal IDDOP(6) oscillation mode • System clock set to 8MHz side • Internal RC oscillation stopped IDDOP(7) • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(8) mA • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal IDDOP(9) oscillation mode • System clock set to 4MHz side • Internal RC oscillation stopped IDDOP(10) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(11) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(12) • System clock set to internal RC oscillation IDDOP(13) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(14) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal IDDOP(15) oscillation mode • Internal RC oscillation stopped • System clock set to 1MHz with IDDOP(16) frequency variable RC oscillation • 1/2 frequency division ratio IDDOP(17) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDOP(19) µA • Frequency variable RC oscillation stopped • 1/2 frequency division ratio Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.8302-17/23 LC875J64C/875J56C/875J48C Continued from preceding page. Parameter Symbol Pin/ VDD [V] • HALT mode consumption VDD1 =VDD2 current =VDD3 • FmX’tal=32.768kHz crystal oscillation mode HALT mode (Note 7-1) IDDHALT(1) Specification Conditions Remarks • FmCF=12MHz ceramic oscillation mode min typ max 4.5 to 5.5 2.7 5.5 3.0 to 3.6 1.4 3 4.5 to 5.5 3.6 7.4 3.0 to 3.6 1.9 4.1 4.5 to 5.5 2 4.2 3.0 to 3.6 1.1 2.3 2.5 to 3.0 0.7 1.5 4.5 to 5.5 1 2.1 3.0 to 3.6 0.5 1.1 2.2 to 3.0 0.3 0.7 4.5 to 5.5 0.28 1 3.0 to 3.6 0.15 0.7 2.2 to 3.0 0.1 0.5 4.5 to 5.5 1 2.9 3.0 to 3.6 0.55 1.8 2.2 to 3.0 0.35 1.4 4.5 to 5.5 19 50 3.0 to 3.6 6.2 30 2.2 to 3.0 3.6 20 4.5 to 5.5 0.015 10 7 unit • System clock set to 12MHz side IDDHALT(2) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio • HALT mode IDDHALT(3) • CF1=24MHz external clock • FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side IDDHALT(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio • HALT mode IDDHALT(5) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(6) • System clock set to 8MHz side • Internal RC oscillation stopped IDDHALT(7) • Frequency variable RC oscillation stopped • 1/1 frequency division ratio mA • HALT mode IDDHALT(8) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(9) • System clock set to 4MHz side • Internal RC oscillation stopped IDDHALT(10) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio • HALT mode IDDHALT(11) • FmCF=0Hz (oscillation stopped) IDDHALT(12) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation IDDHALT(13) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(14) • HALT mode IDDHALT(15) • FmX’tal=32.768kHz crystal oscillation mode • FmCF=0Hz (oscillation stopped) • Internal RC oscillation stopped • System clock set to 1MHz with IDDHALT(16) frequency variable RC oscillation • 1/2 frequency division ratio • HALT mode IDDHALT(17) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDHALT(19) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio HOLD mode consumption current Timer HOLD mode IDDHOLD(1) IDDHOLD(2) • HOLD mode • CF1=VDD or open (external clock mode) IDDHOLD(3) 3.0 to 3.6 0.009 2.2 to 3.0 0.006 6 IDDHOLD(4) • Timer HOLD mode 4.5 to 5.5 16 45 IDDHOLD(5) • CF1=VDD or open (external clock mode) 3.0 to 3.6 5.5 25 2.2 to 3.0 3 15 consumption current VDD1 • FmX’tal=32.768kHz crystal oscillation mode IDDHOLD(6) µA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.8302-18/23 LC875J64C/875J56C/875J48C UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Pin/Remarks Specification Conditions VDD [V] Transfer rate UBR min typ max unit 8192/3 tCYC UTX(P20), 2.2 to 5.5 URX(P21) 16/3 Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1-bit (2-bit in continuous data transmission) Parity bits: None *Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Stop bit Start bit Start of transmission Transmit data (LSB first) End of transmission UBR *Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Stop bit Start bit Start of reception Receive data (LSB first) End of reception UBR No.8302-19/23 LC875J64C/875J56C/875J48C Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Vendor Frequency Name 12MHz 8MHz 4MHz MURATA MURATA MURATA Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time Remarks C1 C2 Rf Rd1 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE12M0G52-R0 (10) (10) Open 470 3.0 to 5.5 0.1 0.5 CSTCE8M00G52-R0 (10) (10) Open 2.2k 2.7 to 5.5 0.1 0.5 Internal CSTLS8M00G53-R0 (15) (15) Open 680 2.5 to 5.5 0.1 0.5 C1, C2 Internal C1, C2 CSTCR4M00G53-R0 (15) (15) Open 3.3k 2.2 to 5.5 0.2 0.6 Internal CSTLS4M00G53-B0 (15) (15) Open 3.3k 2.2 to 5.5 0.2 0.6 C1, C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Vendor Frequency Name 32.768kHz SEIKO EPSON Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 18 Open 560k 2.2 to 5.5 1.4 3.0 Remarks Applicable MC-306 CL value = 12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 Rf XT2 Rf Rd1 C1 C2 Rd2 C3 C4 X’tal CF Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.8302-20/23 LC875J64C/875J56C/875J48C VDD Operating VDD lower limit 0V Power supply Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Reset Unpredictable Instruction execution Reset Time and Oscillation Stabilizing Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.8302-21/23 LC875J64C/875J56C/875J48C VDD RRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC’s operating voltage. RES CRES Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKH tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKLA tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.8302-22/23 LC875J64C/875J56C/875J48C SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice. PS No.8302-23/23