SANYO LC87F5864C

Ordering number : ENA0344
LC87F5864C
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5864C is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard programmable),
2048-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be
divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day
clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities),
an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two 12-bit
PWM channels, a system clock frequency divider, ROM correction function, and a 23-source 10-vector interrupt feature.
Features
„Flash ROM
• Capable of on-board-programing with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• 65536 × 8-bits (LC87F5864C)
„RAM
• 2048 × 9 bits (LC87F5864C)
„Minimum Bus Cycle
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
„Minimum Instruction Cycle Time
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 1.5µs (2MHz)
VDD=2.2 to 5.5V
*This product incorporates technology licensed from Silicon Storage Technology Inc
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.05
83006 / 42706HKIM No.A0344-1/23
LC87F5864C
„Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
„Timers
• Timer 0 : 16-bit timer/counter with a capture register
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 : 16-bit counter (with a 16-bit capture register)
• Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs
Mode 0 : 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
with an 8-bit prescaler (with toggle outputs)
Mode 1 : 8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2 : 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3 : 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used
as PWM)
• Timer 4 : 8-bit timer with a 6-bit prescaler
• Timer 5 : 8-bit timer with a 6-bit prescaler
• Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
„High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
2) Can generate output real-time
„SIO
• SIO0 : 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1 : Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
„UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
No.A0344-2/23
LC87F5864C
„AD Converter : 8 bits × 11 channels
„PWM : Multifrequency 12-bit PWM × 2-channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
„Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
„Interrupts
• 23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer0/base timer1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels : 1024 levels (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillation circuit (internal) :
• CF oscillation circuit :
• Crystal oscillation circuit :
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
„System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and
76.8µs (at a main clock rate of 10MHz).
No.A0344-3/23
LC87F5864C
„Standby Function
• HALT mode : Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode : Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base
timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
„Package Form
• VQFN64 (10 × 10): Lead-free type
• TQFP64J (7 × 7):
Lead-free type
„Development Tools
• Evaluation chip :
• Emulator :
LC87EV690
EVA62S + ECB876600D + SUB875800
„Programming Boards
• W87F58256VQ (For VQFN64 (10 × 10) package)
• W87F58256TQ7 (For TQFP64J (7 × 7) packages)
No.A0344-4/23
LC87F5864C
Package Dimensions
unit : mm
3323
TOP VIEW
SIDE VIEW
BOTTOM VIEW
10.2
10.0
33
32
8.0 Typ
8.0 Typ
10.2
10.0
0.3
49
0.5
48
Depth:0.03 MIN
0.5
0.
2
0.3
11
64
1
16
Do Not Connect
(0.8)
0.2
0.5
SIDE VIEW
0.85MAX
(1.25)
SANYO : VQFN64(10X10)
Package Dimensions
unit : mm
3289
9.0
33
32
64
17
7.0
49
1
0.4
16
0.16
9.0
48
0.5
7.0
0.125
(1.0)
0.1
1.2max
(0.5)
SANYO : TQFP64J(7X7)
No.A0344-5/23
LC87F5864C
PB2
PB3
PB4
PB5
PB6
PB7
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P07/T7O
P06/T6O
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P05/CKO
49
32
PB1
P04
50
31
PB0
P03
51
30
VSS3
P02
52
29
VDD3
P01
53
28
PC7
P00
54
27
PC6
VSS2
55
26
PC5
VDD2
56
25
PC4
PWM3
57
24
PC3
PC2
LC87F5864C
61
20
P86/AN6
P14/SI1/SB1
62
19
P85/AN5
P13/SO1
63
18
P84/AN4
P12/SCK0
64
17
P83/AN3
9 10 11 12 13 14 15 16
P70/INT0/T0LCP/AN8
8
P72/INT2/T0IN
7
P71/INT1/T0HCP/AN9
6
RES
5
P73/INT3/T0IN
4
XT1/AN10
3
VSS1
2
XT2/AN11
1
CF1
PC0
P15/SCK1
CF2
21
VDD1
60
P80/AN0
PC1
P16/T1PWML
P81/AN1
22
P82/AN2
59
P10/SO0
58
P17/T1PWMH/BUZ
P11/SI0/SB0
PWM2
23
Top view
SANYO: VQFN64 (10 × 10) “Lead-free Type”
No.A0344-6/23
PB1
PB0
VDD3
VSS3
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
P86/AN6
P85/AN5
P84/AN4
P83/AN3
LC87F5864C
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
49
32
PB2
P71/INT1/T0HCP/AN9
50
31
PB3
P72/INT2/T0IN
51
30
PB4
P73/INT3/T0IN
52
29
PB5
RES
53
28
PB6
XT1/AN10
54
27
PB7
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
LC87F5864C
57
24
P25/INT5/T1IN
CF2
58
23
P24/INT5/T1IN
VDD1
59
22
P23/INT4/T1IN
P80/AN0
60
21
P22/INT4/T1IN
P81/AN1
61
20
P21/URX/INT4/T1IN
P82/AN2
8
9 10 11 12 13 14 15 16
P05/CKO
7
P04
6
P03
5
P02
4
P01
3
P00
2
VSS2
1
VDD2
P06/T6O
PWM3
17
PWM2
64
P17/T1PWMH/BUZ
P11/SI0/SB0
P16/T1PWML
P07/T7O
P15/SCK1
63
P14/SI1/SB1
P20/UTX/INT4/T1IN
18
P13/SO1
19
P12/SCK0
62
P10/SO0
Top view
SANYO: TQFP64J (7 × 7)
“Lead-free Type”
No.A0344-7/23
LC87F5864C
System Block Diagram
Interrupt control
IR
Standby control
ROM correct
CF
Flash ROM
Clock
generator
RC
PLA
X’tal
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7
ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to INT5
Noise filter
RAR
Base timer
Port B
RAM
PWM2/3
Port C
Stack pointer
UART
Watchdog timer
No.A0344-8/23
LC87F5864C
Pin Description
Pin Name
VSS1, VSS2
I/O
Description
Option
-
- Power supply pin
No
-
+ Power supply pin
No
• 8-bit I/O port
Yes
VSS3
VDD1, VDD2
VDD3
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05 : Clock output (system clock / can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/beeper output
Port 2
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
P20 : UART transmit
P21 : UART receive
P20 to P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input
/timer 0H capture input
P24 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input
/timer 0H capture input
• Interrupt acknowledge type
Port 7
P70 to P73
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
Falling
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0344-9/23
LC87F5864C
Continued from preceding page.
Pin Name
Port 8
I/O
I/O
Description
• 7-bit I/O port
Option
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input port : AN0 (P80) to AN6 (P86)
PWM2
I/O
PWM3
Port B
• PWM2 and PWM3 output ports
No
• General-purpose I/O available
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistor can be turned on and off in 1-bit units
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0344-10/23
LC87F5864C
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
P00 to P07
1 bit
P10 to P17
1 bit
P20 to P27
1 bit
Option Type
1
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
PWM2, PWM3
-
No
CMOS
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
PB0 to PB7
PC0 to PC7
1 bit
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
XT1
-
No
Input for 32.768kHz crystal oscillator (Input only)
No
XT2
-
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose output mode)
Note 1 : Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1 : Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
Supply
For backup *2
VDD2
VDD3
VSS1
VSS2
VSS3
*2 : The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0344-11/23
LC87F5864C
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
Maximum supply
VDD max
VDD 1, VDD2, VDD3
VDD1=VDD2=VDD3
voltage
Input voltage
VI(1)
XT1, CF1
Input/output voltage
VIO(1)
Ports 0, 1, 2
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 7, 8
-0.3
Ports B, C
VDD+0.3
PWM2, PWM3, XT2
Peak output
IOPH(1)
current
High level output current
Mean output
CMOS output select
Per 1 applicable pin
IOPH(2)
PWM2, PWM3
Per 1 applicable pin
-20
P71 to P73
Per 1 applicable pin
-5
IOMH(1)
Ports 0, 1, 2
CMOS output select
Ports B, C
Per 1 applicable pin
IOMH(2)
PWM2, PWM3
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
∑IOAH(1)
P71 to P73
Total of all applicable pins
current
∑IOAH(2)
Port 1
Total of all applicable pins
PWM2, PWM3
∑IOAH(3)
Ports 0, 2
Total of all applicable pins
∑IOAH(4)
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
Peak output
-10
IOPH(3)
current
(Note 1-1)
Ports 0, 1, 2
Ports B, C
-7.5
-15
-3
-10
-25
-25
-45
∑IOAH(5)
Port B
Total of all applicable pins
-25
∑IOAH(6)
Port C
Total of all applicable pins
-25
∑IOAH(7)
Ports B, C
Total of all applicable pins
-45
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Ports 1, 2
20
Ports B, C
PWM2, PWM3
Low level output current
Mean output
mA
IOPL(2)
P00, P01
Per 1 applicable pin
30
IOPL(3)
Ports 7, 8, XT2
Per 1 applicable pin
10
IOML(1)
P02 to P07
Per 1 applicable pin
current
Ports 1, 2
(Note 1-1)
Ports B, C
15
PWM2, PWM3
Total output
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
Ports 7, 8, XT2
Per 1 applicable pin
7.5
∑IOAL(1)
Port 7
Total of all applicable pins
current
15
P83 to P86, XT2
∑IOAL(2)
P80 to P82
Total of all applicable pins
15
∑IOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
20
∑IOAL(4)
Port 1
Total of all applicable pins
45
PWM2, PWM3
∑IOAL(5)
Ports 0, 2
Total of all applicable pins
∑IOAL(6)
Ports 0, 1, 2
Total of all applicable pins
45
80
PWM2, PWM3
Power dissipation
∑IOAL(7)
Port B
Total of all applicable pins
45
∑IOAL(8)
Port C
Total of all applicable pins
45
∑IOAL(9)
Ports B, C
Total of all applicable pins
Pdmax
VQFN64(10×10)
Ta=-20 to +70°C
80
190
mW
TQFP64J(7×7)
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
188
-20
70
-55
125
°C
Note 1-1 : The mean output current is a mean value measured over 100ms.
No.A0344-12/23
LC87F5864C
Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Conditions
Specification
VDD[V]
min
typ
max
0.245µs ≤ tCYC ≤ 200µs
3.0
5.5
supply voltage
0.367µs ≤ tCYC ≤ 200µs
2.5
5.5
(Note 2-1)
1.47µs ≤ tCYC ≤ 200µs
2.2
5.5
2.0
5.5
Operating
Memory
VDD(1)
VHD
VDD1=VDD2=VDD3
VDD1=VDD2=VDD3
sustaining
unit
RAM and register contents
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.2 to 5.5
P70 port input
0.3VDD
VDD
+0.7
/interrupt side
VIH(2)
Ports 0, 8, B, C
2.2 to 5.5
PWM2, PWM3
VIH(3)
Port 70 watchdog
timer side
Low level input
VIH(4)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2
voltage
P71 to P73
P70 port input
/interrupt side
VIL(2)
Ports 0, 8, B, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
Instruction cycle
XT1, XT2, CF1, RES
tCYC
time
(Note 2-2)
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note 2-3)
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
FsX’tal
Internal RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
0.3VDD
+0.7
VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.5 to 5.5
0.367
200
2.2 to 5.5
1.47
200
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
2.2 to 5.5
0.3
V
1.0
32.768
µs
MHz
2.0
kHz
Note 2-1 : VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2 : Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3 : See Tables 1 and 2 for the oscillation constants.
No.A0344-13/23
LC87F5864C
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High level input
Symbol
IIH(1)
current
IIH(2)
Pins
Conditions
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
VIN=VDD
RES
(Including output Tr's off leakage
PWM2, PWM3
current)
XT1, XT2
For input port specification
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VSS
PWM2, PWM3
current)
current
IIL(2)
XT1, XT2
Specification
VDD[V]
min
typ
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
µA
2.2 to 5.5
-1
For input port specification
2.2 to 5.5
-1
-15
IIL(3)
CF1
VIN=VSS
2.2 to 5.5
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports B, C
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
P71 to P73
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(8)
IOH=-1mA
2.2 to 5.5
VDD-0.4
VOH(4)
VOH(5)
VOH(6)
PWM2, PWM3
V
Low level output
VOL(1)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports B, C
IOL=1.6mA
3.0 to 5.5
0.4
VOL(3)
PWM2, PWM3
IOL=1mA
2.2 to 5.5
0.4
VOL(4)
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(5)
XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(6)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(7)
IOL=5mA
3.0 to 5.5
0.4
VOL(8)
IOL=2.5mA
2.2 to 5.5
0.4
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 5.5
18
50
150
Pull-up
Rpu(1)
Ports 0, 1, 2, 7
resistance
Rpu(2)
Ports B, C
Hysteresis
VHYS
RES
voltage
Pin capacitance
2.2 to 5.5
Ports 1, 2, 7
CP
All pins
unit
(Including output Tr's off leakage
VIN=VSS
VOH(3)
max
0.1
VDD
kΩ
V
For pins other than that under test:
VIN=VSS
f=1MHz
2.2 to 5.5
10
pF
Ta=25°C
No.A0344-14/23
LC87F5864C
Serial Input/Output Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
VDD [V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
tSCKH(1)
2.2 to 5.5
pulse width
tSCKHA(1)
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
tSCKH(2)
transmission/reception mode
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output clock
Input clock
Output delay
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
thDI(1)
tdD0(1)
SO0(P10),
SB0(P11)
time
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
2.2 to 5.5
(1/3)tCYC
+0.05
µs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0344-15/23
LC87F5864C
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig. 6.
2.2 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output delay time
Serial output
tsDI(2)
unit
1
2.2 to 5.5
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
VDD [V]
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
µs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
2.2 to 5.5
output state change in
(1/3)tCYC
+0.05
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0344-16/23
LC87F5864C
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
are enabled.
min
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
typ
max
unit
INT4(P20 to P23),
INT5(P24 to P27)
tPIH(2)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is 1/1
• Event inputs for timer 0 are
tCYC
enabled.
tPIH(3)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is 1/32
• Event inputs for timer 0 are
enabled.
tPIH(4)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is 1/128
• Event inputs for timer 0 are
enabled.
tPIL(5)
RES
Resetting is enabled.
µs
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD [V]
Resolution
N
AN0(P80) to
Absolute accuracy
ET
AN6(P86),
min
typ
3.0 to 5.5
(Note 6-1)
3.0 to 5.5
Conversion time
TCAD
AD conversion time = 32 × tCYC
AN10(XT1),
(when ADCR2 = 0) (Note 6-2)
4.5 to 5.5
AN11(XT2)
3.0 to 5.5
AD conversion time = 64 × tCYC
(when ADCR2 = 1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
Analog input voltage
VAIN
3.0 to 5.5
range
Analog port input
IAINH
VAIN=VDD
3.0 to 5.5
current
IAINL
VAIN=VSS
3.0 to 5.5
unit
bit
±1.5
AN8(P70),
AN9(P71),
max
8
15.68
97.92
(tCYC=
(tCYC=
0.49µs)
3.06µs)
23.52
97.92
(tCYC=
(tCYC=
0.735µs)
3.06µs)
18.82
97.92
(tCYC=
(tCYC=
0.294µs)
1.53µs)
47.04
97.92
(tCYC=
(tCYC=
0.735µs)
1.53µs)
VSS
VDD
1
-1
LSB
µs
V
µA
Note 6-1 : The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2 : The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0344-17/23
LC87F5864C
Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
consumption
current
(Note 7-1)
IDDOP(2)
Pin/
Specification
Conditions
Remarks
VDD[V]
VDD1
• FmCF=12MHz ceramic oscillation mode
=VDD2
• FmX’tal=32.768kHz crystal oscillation mode
=VDD3
• System clock set to 12MHz side
min
typ
max
4.5 to 5.5
8.7
22
3.0 to 3.6
5
12.5
4.5 to 5.5
6.6
16.5
3.0 to 3.6
3.8
9.6
• 1/1 frequency division ratio
2.5 to 3.0
2.5
7.4
• FmCF=4MHz ceramic oscillation mode
4.5 to 5.5
2.5
6.3
3.0 to 3.6
1.4
3.5
2.2 to 3.0
0.9
2.7
4.5 to 5.5
0.75
3.1
3.0 to 3.6
0.4
1.7
• Internal RC oscillation stopped.
unit
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(4)
IDDOP(5)
IDDOP(6)
• System clock set to 8 MHz side
• Internal RC oscillation stopped.
mA
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(7)
IDDOP(8)
• System clock set to 4 MHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(9)
IDDOP(10)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
IDDOP(11)
• 1/2 frequency division ratio
2.2 to 3.0
0.28
1.35
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
4.5 to 5.5
35
115
3.0 to 3.6
18
65
2.2 to 3.0
12
46
3.6
8.2
2
4.6
2.6
5.9
1.4
3.3
1
2.5
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(13)
IDDOP(14)
• System clock set to 32.768kHz side
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FmX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
IDDHALT(2)
µA
• Internal RC oscillation stopped.
• System clock set to 12MHz side
• Internal RC oscillation stopped.
4.5 to 5.5
3.0 to 3.6
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(3)
• HALT mode
4.5 to 5.5
• FmCF=8MHz ceramic oscillation mode
IDDHALT(4)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
3.0 to 3.6
• Internal RC oscillation stopped.
IDDHALT(5)
• Frequency variable RC oscillation stopped.
2.5 to 3.0
• 1/1 frequency division ratio
IDDHALT(6)
• HALT mode
mA
4.5 to 5.5
• FmCF=4MHz ceramic oscillation mode
IDDHALT(7)
• FmX’tal=32.768kHz crystal oscillation mode
1.15
2.65
0.6
1.5
0.4
1.1
0.37
1.3
0.2
0.75
0.13
0.54
3.0 to 3.6
• System clock set to 4MHz side
• Internal RC oscillation stopped.
IDDHALT(8)
• Frequency variable RC oscillation stopped.
2.2 to 3.0
• 1/2 frequency division ratio
IDDHALT(9)
• HALT mode
4.5 to 5.5
• FmCF=0Hz (oscillation stopped)
IDDHALT(10)
• FmX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
• System clock set to internal RC oscillation
IDDHALT(11)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
2.2 to 3.0
Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0344-18/23
LC87F5864C
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(12)
Pin/
VDD[V]
VDD1
• HALT mode
consumption
=VDD2
• FmCF=0Hz (oscillation stopped)
current
=VDD3
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(13)
(Note 7-1)
Specification
Conditions
Remarks
• System clock set to 32.768kHz side
min
typ
max
4.5 to 5.5
18.5
68
3.0 to 3.6
10
38
2.2 to 3.0
6.5
26
4.5 to 5.5
0.05
20
unit
• Internal RC oscillation stopped.
IDDHALT(14)
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
VDD1
• CF1=VDD or open
IDDHOLD(2)
current
(External clock mode)
IDDHOLD(3)
Timer HOLD mode
consumption
current
• HOLD mode
IDDHOLD(4)
• Timer HOLD mode
IDDHOLD(5)
• CF1=VDD or open
(External clock mode)
IDDHOLD(6)
• FmX’tal=32.768kHz crystal oscillation mode
3.0 to 3.6
0.03
12
2.2 to 3.0
0.02
8
4.5 to 5.5
16
58
3.0 to 3.6
8.5
32
2.2 to 3.0
5
20
µA
Note 7-1 : The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Onboard
IDDFW(1)
Pin/
Remarks
VDD1
programming current
Specification
Conditions
VDD [V]
• 128-byte programming
• Erasing current included
Programming time
tFW(1)
min
typ
max
unit
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data is excluded.
UART (Full Duplex) Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
Transfer rate
UBR
Data length:
Stop bits:
Parity bits:
P20, P21
2.2 to 5.5
min
typ
16/3
max
unit
8192/3
tCYC
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Stop bit
Start of
End of
Transmit data (LSB first)
transmission
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
Receive data (LSB first)
Start of
End of
reception
reception
UBR
No.A0344-19/23
LC87F5864C
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
12MHz
8MHz
4MHz
Circuit Constant
Vendor Name
MURATA
MURATA
MURATA
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
Remarks
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
CSTCE12M0G52-R0
(10)
(10)
Open
470
2.8 to 5.5
0.05
0.15
CSTCE8M00G52-R0
(10)
(10)
Open
2.2k
2.7 to 5.5
0.05
0.15
Internal
CSTLS8M00G53-B0
(15)
(15)
Open
680
2.5 to 5.5
0.05
0.15
C1, C2
Internal
C1, C2
CSTCR4M00G53-R0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Circuit Constant
Nominal
Vendor Name
Frequency
Oscillator Name
Operating
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
510k
Voltage Range
[V]
Oscillation
Stabilization Time
typ
max
[s]
[s]
1.0
3.0
Remarks
Applicable
32.768kHz
SEIKO EPSON
MC-306
2.2 to 5.5
CL value
=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
Rf
C1
XT1
XT2
Rf
Rd1
C2
Rd2
C3
C4
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0344-20/23
LC87F5864C
VDD
Power supply
Operating VDD lower limit
0V
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0344-21/23
LC87F5864C
VDD
RRES
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKL
tSCKH
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
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LC87F5864C
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PS No.A0344-23/23