SANYO LV5065VB

Ordering number : ENA2003
Bi-CMOS IC
LV5065VB
Built-in 2-channels
DC/DC Converter Controller
Overview
The LV5065VB is a high efficiency DC/DC converter controller with 2-channels IC adopting a synchronous rectifying
system. Incorporating numerous functions on a single chip with easy external setting, it can be used for a wide variety of
applications. This device is optimal for use in internal power supply systems which are used in electronic devices,
LCD-TVs, DVD recorders, etc.
Functions
• Step-down DC/DC converter controller with 2-channel
• Built-in input UVLO circuit, Over current detection function, soft-start/soft-stop function and Start-up delay circuit
• Built-in output voltage monitor function (Under voltage protection with power good and timer latch)
• 180 degree interleaving operation during 1-phase to 2-phase
• Synchronized operation is possible (Master-slave operation is possible when using plural devices)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
Output peak current
IOUT
Allowable power dissipation
Pd max
0.95
W
Operating temperature
Topr
-20 to 85
°C
Storage temperature
Tstg
-55 to +150
°C
Mounted on a specified board *
20
V
±1.0
A
*: Specified board: 114.3mm × 76.1mm ×1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, high
voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
20812 SY 20120118-S00002 No.A2003-1/9
LV5065VB
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
Allowable terminal voltage
1
Between HDRV1,2, CBOOT1,2
25
V
and PGND
2
Between HDRV1,2, CBOOT1,2
and SW
6.5
V
3
VIN, ILIM1,2, RSNS1,2, SW1,2,
PGOOD1,2
20
V
4
VLIN5, VDD, LDRV1,2
6.5
V
5
COMP1,2, FB1,2, SS1,2,
UV_DELAY,TD1,2, CT, CLKO
VLIN5+0.3
V
Recommended Operating Condition at Ta = 25°C
Parameter
Recommended supply voltage range
Symbol
Conditions
Ratings
VIN
Unit
9.5 to 18
V
Electrical Characteristics at Ta = 25°C, VIN=12V, Unless especially specified.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
System
Reference voltage for comparing
VREF
VIN = 15
Supply current 1
ICC1
TD1,2 = 5V, VIN = 15
Supply current 2
ICC2
TD1,2 = 0V, VIN = 15
5V supply voltage
VLIN5
VIN = 15, IVIN5 = 0 to 10mA
Over-current sense comparator offset
VCLOS
Over-current sense reference current
ICL
1%
0.633
+1%
4
6
8
mA
V
0.8
1.4
2.0
mA
5.10
5.30
5.50
(Except for the Ciss charge)
-5
VIN = 12 to 15V *1
V
+5
mV
μA
60.45
65.00
69.55
-7.0
source
μA
Soft start source current
ISSSC
TD = 5V
-1.8
-3.5
Soft start sink current
ISSSK
TD = 0V
0.2
1.0
Soft start clamp voltage
VSST0
1.2
1.6
2.0
V
UV_DELAY source current
ISCUVD
UV_DELAY = 2V
-4.3
-8.6
-17.2
μA
UV_DELAY sink current
ISKUVD
UV_DELAY = 2V
0.2
1.0
1.5
2.4
3.5
V
77
82
87
%
UV_DELAY threshold voltage
VUVD
UV_DELAY operating voltage
VUVP
VUVP detection hysteresis
ΔVUVP
Over-voltage detection
VOVP
Output discharge transistor ON resistance
VSWON
100% at VFBx = VREF
mA
mA
8
100% at VFBx = VREF
%
113
118
123
%
5
10
20
Ω
10
μA
Output part
CBOOT leakage current
ICBOOT
VCBOOT = VSW + 6.5V
HDRVx LDRVx source current
ISCDRV
1.0
HDRVx LDRVx sink current
ISKDRV
1.0
HDRVx lower ON resistance
RHDRV
LDRVx lower ON resistance
Synchronous ON prevention dead time 1
A
A
Ω
IOUT = 500mA
1.5
2.5
RLDRV
IOUT = 500mA
1.5
2.5
Tdead1
LDRV OFF→HDRV ON
50
ns
Synchronous ON prevention dead time 2
Tdead2
HDRV OFF→LDRV ON
50
ns
LDRV_ON delay time
Mdead
HDRV OFF→LDRV ON at MAX_Duty
50
ns
fosc
VIN = 15, CT=270pF
170
Ω
Oscillator
Oscillation frequency
200
230
kHz
100
500
kHz
90
95
Oscillation frequency range
foscop
VIN = 15
Maximum ON duty
DON max
VIN = 15, CT=270pF
Minimum ON time
TON min
VIN = 15, CT=270pF
120
2.75
3.2
V
1
1.2
V
Upper-side voltage saw- tooth wave
VsawH
fOSC=200kHz, RSNS=VIN(0Ω)
Lower-side voltage saw-tooth wave
VsawL
fOSC=200kHz
ON time difference between CH1 to CH2
ΔTdead
5
%
ns
%
Continued on next page.
No.A2003-2/9
LV5065VB
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Error Amplifier
Error amplifier input current
IFB
COMP pin source current
ICOMPSC
-200
COMP pin sink current
ICOMPSK
Error amplifier gm
gm
Current detection amplifier gain
GISNS
-100
200
nA
-100
-18
μA
μA
18
100
500
700
900
3
4
5
0.5
1.0
umho
Logic output
Power Good low level source current
IpwrgdL
VPGOOD = 0.4V
Power Good high level leakage current
IpwrgdH
VPGOOD = 15V
TP pin threshold voltage
VONTD
When the voltage of the TD pin rises
TP pin high impedance voltage
VTDH
When VIN and VLIN5 pins are set to open
4.5
5.2
5.5
V
TD pin charge source current
ITDSC
-1.8
-3.5
-7.0
μA
TD pin discharge sink current
ITDSK
0.2
1.0
CLKO high level voltage
VCLKOH
ICLKO = 1mA
CLKO low level voltage
VCLKOL
ICLKO = 1mA
1.5
mA
2.6
10
μA
3.5
V
mA
0.7V5LIN
V
0.3V5LIN
V
Protection function
VIN UVLO Release voltage
VUVLO
UVLO Hysteresis
ΔVUVLO
3.5
4.1
4.3
mA
μA
0.4
*1: The overcurrent detection standard current source assumes it a measurement standard
Package Dimensions
unit : mm (typ)
3421
Pd max - Ta
1200
Allowable power dissipation, Pd max -- mW
8.0
0.5
6.4
4.4
30
12
0.5
0.22
0.15
0.1
(1.5)
1.7 MAX
(0.5)
Specified board: 114.3×76.1×1.6mm3
glass epoxy board.
1000
950
800
600
494
400
200
0
-20
0
20
40
60
80 85
100
Ambient temperature, Ta -- °C
SANYO : SSOP30(225mil)
SGND
COMP2
FB2
RSNS2
ILIM2
TD2
SS2
PGOOD2
CT
27
26
25
24
23
22
21
20
19
18
17
CLKO
CBOOT2
28
16
13
14
15
VIN
SW2
29
PGOOD1
HDRV2
30
UV_DELAY
PGND
LDRV2
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
VDD
LDRV1
HDRV1
SW1
CBOOT1
VLIN5
COMP1
FB1
RSNS1
ILIM1
TD1
SS1
LV5065VB
Top view
No.A2003-3/9
LV5065VB
Block Diagram
BG
BG
reference
Voltage
and
current
generator
IREF
VIN
VIN
POR
9.0V
/8.0V
Current
bias
Input
Power
Supply
VLIN5 5.3V
5V REG
(always ON)
Vref
VLIN5
Internal Bias
Vref
0.63V
4.0V
/3.5V
ILIM
Comp
COMP1
ILIM1
VIN
SENSE
Amp
CH1
output
RSNS1
PWM comp
Error Amp
FB1
0.82Vref
UV1
1.17Vref
OV1
Shifter
& latch
PWM logic
SKIP control
SW1
1.6V
Corrective
ramp
SD
SS1EN
D
SD
HDRV1
S Q
Vref
SS1
CBOOT1
R Q
Shoot through
protection
sequencer
CH1
output
VDD
LDRV1
0 deg
TD1
CONT1
POR
2.6V
ILIM
Comp
COMP2
ILIM2
VIN
SENSE
Amp
CH2
output
RSNS2
PWM comp
Error Amp
FB2
0.82Vref
UV2
1.17Vref
OV2
Shifter
& latch
PWM logic
SKIP control
SW2
1.6V
Corrective
ramp
SD
SS2EN
D
SD
HDRV2
S Q
Vref
SS2
CBOOT2
R Q
CH2
output
Shoot through
protection
sequencer
LDRV2
180 deg
PGND
TD2
POR
CONT2
2.6V
CONT1
CONT2
POR
OV1
R Q
OV2
0V
S Q
UV1
UV2
SS1EN
D
SS2EN
D
PGOOD1 PGOOD2
2.6V
UV_DELAY
UV
timeout
0
180
deg
deg
OSC
200kHz
CT
CLKO
SGND
Sync. pulse out
5V
0V
No.A2003-4/9
LV5065VB
Pin Functions
Pin No.
1
Pin name
VDD
Description
Power supply pin for the gate drive of an external lower-side MOS-FET.
This pin is connected to the VLIN5 pin through a filter.
2
LDRV
The gate drive pin of an external lower-side MOS-FET of channel 1.
This pin has the signal input part for prevention of short-through of both the upper and lower MOS-FETs.
When the voltage of this pin becomes less than 2V, the HDRV pin is turned on.
3
HDRV1
The gate drive pin for an external upper side MOS-FET of channel 1.
4
SW1
This pin is connected with the switching node of channel 1.
A source of an external upper side MOSFET and a drain of an external lower side MOS-FET are connected with this pin.
This pin becomes the return current path of the HDRV pin.
This pin is connected with a transistor drain of the discharge MOS-FET for SOFT STOP in the IC (typical 30Ω). Also, this
pin has the signal output part for the short through prevention of both the upper and lower MOS-FETs.
When this terminal voltage becomes 2V or less for PGND, the LDRV pin is turned on.
5
CBOOT1
The bootstrap capacity connection pin of channel 1.
The gate drive power of upper MOSFET is provided by this pin.
This pin is connected to the VDD pin through a diode and is connected to the SW pin through the bootstrap capacity.
6
VLIN5
The output pin of an internal regulator of 5V. The current is provided by the VIN pin.
Also, power supply of the control circuit in the IC is provided by this pin. Connect an output capacitor of 1μF between this
pin and SGND. A regulator of 5V operates, even if the IC is in the standby state. This pin is monitored by an UVLO function
and the IC starts by the voltage of 4.0V or more (the IC is off by the voltage of 3.5V or less.)
7
COMP1
The phase compensation pin of channel 1.
The output of an internal transformer conductance amplifier is connected.
Connect an external phase compensation circuit between this pin and SGND.
8
FB1
Feed back input pin of channel 1.
The minus terminal (-) of the trans conductance amplifier is connected.
The voltage generated when the output voltage was divided by a resistor is input into this pin.
The converter operates so that this pin becomes an internal reference voltage (VREF=0.63V).
Also, this pin is monitored by the comparators UVP and OVP.
When the voltage of this pin becomes less than 82% of the set voltage, the PGOOD pin is low level.
A timer of the UV_DELAY function operates. Also, when the voltage of this pin becomes more than 118% of the set voltage,
the IC latches off.
9
RSNS1
Channel 1 side input pin of the over current detection comparator / the current detection amplifier.
To detect resistance, this pin is connected to the under side of a resistor for the current detection between the VIN pin and
the DRAIN of the upper MOS-FET. Also, to use the ON resistance of MOS-FET for the current detection, connect this pin to
the SOURCE of the upper MOS-FET. To prevent the common impedance of main current to the detection-voltage, this pin
is connected by independent wiring.
10
ILIM
The pin to set the trip point for over current detection of channel 1.
Since the SINK current source of 65μA (ILIM) is connected in the IC, the over-current detection voltage (ILIM × RLIM) is
generated by connecting a resistor RLIM between this pin and the VIN pin.
The over-current is detected by comparing the voltage between the VIN pin and the ILIM pin to the current detection
resistance RSNS or both end voltage of the upper MOSFET.
11
TD
Start-up delay pin of channel 1.
The time until the IC starts after releasing POR is set by connecting a capacitor between this pin and SGND.
After releasing POR, an external capacitor is charged up by the constant current source of 3.5μA in the IC.
When this terminal voltage becomes 2.6V or more, The IC starts. Also, when this terminal voltage becomes 2.6V or less,
The IC becomes the standby state. If external capacitor is not connected, the IC instantly starts after releasing POR.
12
SS1
The pin to connect a capacitor for soft start of channel 1.
After releasing POR, when the voltage of the TD pin becomes 2.6V or more, the SS1 pin is charged by an internal constant
current source of 3.5μA. Since this pin is connected to the positive (+) input of the transformer conductance amplifier, the
ramp-up wave form of the SS pin becomes the ramp-up wave form of the output.
During POR operations and after the UV_DELAY time-out, the SS1 pin is discharged
13
PGOOD
The power good pin of channel 1. The open drain MOS-FET of the withstand of 18V is connected in the IC.
When the output voltage of channel 1 is less than -13% for the setup voltage, the low level is output.
This pin has hysteresis of about (VREF × 8.0%).
14
UV_DELAY
Common UVP DELAY pin to channel 1 and channel 2.
By connecting a capacitor between this pin and SGND, the time until the IC latches off after detecting the UVP state can be
set. Also, after channel 1 or channel 2 terminated the soft-start function, when the output voltage becomes 82% or less for
the setup voltage, an external capacitor is charged by the constant current source of 8.6μA in the IC.
When this terminal voltage becomes 2.6V or more, the IC is latched off.
If an external capacitor is not connected, the IC is instantly latched off after detecting the UVP state.
Also, when this pin is shorted to GND, the UV_DELAY function is not operated.
Continued on next page.
No.A2003-5/9
LV5065VB
Continued from preceding page.
Pin No.
Pin name
15
VIN
16
CLKO
Description
Power supply pin of the IC.
This pin is observed by the UVLO function and IC starts by 9.0V or more. (After starts, stop by 8.0V or less. )
The clock output pin. The clock that synchronized to the oscillation waveform of the CT pin is output.
To synchronize two or more LV5052Vs, the CLKO pin of the device that becomes a master is connected to the CT pin of the
device that becomes a slave. When two or more the devices are synchronized and the start-up timing is changed by using
the TD pin between each device, the earliest start-up device is determined as the master.
17
CT
The pin to connect an external capacitor for the oscillator. Connect a capacitor between this pin and SGND. When a
capacitor of 270pF is connected between this pin and GND, the oscillation frequency can be set up by 200kHz. Also, this
pin is applied by an external clock signal.
The PWM operation is performed by the frequency of applied clock signal.
When an external clock signal is applied, the rectangular wave of 0V in low level and from 0V / 3.3V to 5V in high level is
applied. The rectangular wave source needs the fan-out of 1mA or more.
18
PGOOD2
The power good pin of channel 2.
19
SS2
The pin to connect a capacitor for soft start of channel 2.
20
TD2
Start-up delay pin of channel 2.
21
ILIM2
The pin to set the trip point for over current detection of channel 2.
22
RSNS2
Channel 2 side input pin of the over current detection comparator / the current detection amplifier.
23
FB2
Feed back input pin of channel 2.
24
COMP2
The phase compensation pin of channel 2.
25
SGND
The system ground of the IC. The reference voltage is generated based on this pin.
26
CBOOT2
The bootstrap capacity connection pin of channel 2.
27
SW2
This pin is connected with the switching node of channel 2.
28
HDRV2
The gate drive pin for an external upper side MOS-FET of channel 2.
29
LDRV2
The gate drive pin of an external lower-side MOS-FET of channel 2.
30
PGND
Power ground pin. This pin becomes the return current path of the LDRV pin.
This pin is connected to the power supply system ground.
No.A2003-6/9
LV5065VB
Start-up Sequence
Each signal control timing at power supply ON is as below.
VIN=15V
9V typ
VIN
UVLO release *
VLIN5=5V
4.0V typ
VLIN5
2.6V typ
TD=5V
TD
SS=1.6V
0.63V
SS
VOUT=Vout × 100%
Vout × 82%
VOUT
PGOOD
* Starts charging the TD at the trigger point of either VIN > 9V(typ) or VLIN5 > 4.5V(typ), whichever is later.
Protection Operate Sequence
(1) Latch-off release by UVLO
The signal control timing diagram for resetting the latch-off condition using UVLO is shown below.
VIN=15V
9V typ
VIN
8V typ
Restart
VLIN5=5V
VLIN5
TD=5V
TD discharge start
2.6V typ
TD
SS=1.6V
0.63V
SS
Vout × 118%
VOUT
Vout × 82%
VOUT=Vout × 100%
Vout × 82%
OVP
PGOOD
(2) Latch off release by TD
The signal control timing diagram for resetting the latch-off condition using UVLO is shown below.
VIN=15V
VIN
VLIN5=5V
VLIN5
TD discharge start
TD=5V
2.6V typ
TD
SS=1.6V
0.63V
SS
Vout × 118%
VOUT
Vout × 82%
OVP
VOUT=Vout × 100%
Vout × 82%
PGOOD
No.A2003-7/9
LV5065VB
Shoot through protection
At the same time on prevention dead time1 (Tdead1): LDRV OFF → HDRV ON
LDRV
At the same time
on prevention
dead time 1
Typ_50ns
HDRV
SW
• HDRV is turned on after typ_50ns after LDRV became 2V in the LDRV off → HDRV on.
At the same time on prevention dead time2 (Tdead2): HDRV OFF → LDRV ON
LDRV
HDRV
At the same time
on prevention
dead time 2
Typ_50ns
SW
Vth_2V
• LDRV is turned on after typ_50ns after SW became 2V in the HDRV off → LDRV on.
LDRV compulsion ON delay time
LDRV compulsion ON timing
LDRV
HDRV
SW
HDRV-SW
(Hi-side_mosfet_Vgs)
MAX_duty time
dead time
Typ_50ns
• Even if SW does not reach 2V when HDRV reaches MAX_duty, LDRV is performed ON of forcibly after about
50ns. This price changes by Ciss of the external MOSFET.
PS No.A2003-8/9
LV5065VB
Synchronized operation
A recommended circuit for synchronizing the LV5056VB is shown below.
Master
Slave
VIN
VIN
VIN (typ 15V)
CLKO
CT
CT
270pF
VIN
CT
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of February, 2012. Specifications and information herein are subject
to change without notice.
PS No.A2003-9/9