STMICROELECTRONICS 74LVQ161

74LVQ161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ161 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
SOP
TSSOP
Table 1: Order Codes
PACKAGE
T&R
SOP
TSSOP
74LVQ161MTR
74LVQ161TTR
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 2
1/14
74LVQ161
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
NAME AND FUNCTION
1
CLEAR
2
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
A, B, C, D
PE
TE
LOAD
QA to QD
Asynchronous Master
Reset
Clock Input (LOW to
HIGH Edge Trigger)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Flip-Flop Outputs
CARRY OUT Terminal Count Output
GND
Ground (0V)
VCC
Positive Supply Voltage
Table 3: Truth Table
INPUTS
OUTPUTS
FUNCTION
CLEAR
LOAD
PE
TE
CK
L
X
X
X
X
H
L
X
X
H
H
X
L
NO CHANGE
NO COUNT
H
H
L
X
NO CHANGE
NO COUNT
H
H
H
H
COUNT UP
COUNT
H
X
X
X
NO CHANGE
NO COUNT
L
L
L
L
RESET TO "0"
A
B
C
D
PRESET DATA
X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT: TE x QA x QB x QC x QD
Figure 3: Logic Diagram
2/14
74LVQ161
Figure 4: Timing Chart
Table 4: Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
Storage Temperature
Tstg
TL
Lead Temperature (10 sec)
V
± 50
mA
± 300
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
3/14
74LVQ161
Table 5: Recommended Operating Conditions
Symbol
VCC
Parameter
Value
Unit
Supply Voltage (note 1)
2 to 3.6
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
dt/dv
Input Rise and Fall Time VCC = 3.0V (note 2)
-55 to 125
°C
0 to 10
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
Table 6: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
Parameter
TA = 25°C
VCC
(V)
Min.
High Level Input Volt. 3.0 to
3.6
Low Level Input Volt.
High Level Output
Voltage
3.0
Value
Typ.
Max.
2.0
Low Level Output
Voltage
3.0
-55 to 125°C
Min.
Min.
IO=-50 µA
2.9
IO=-12 mA
2.58
2.99
2.9
2.9
2.48
2.2
IO=50 µA
0.002
0.1
IO=12 mA
0
0.36
ICC
IOLD
IOHD
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output Current (note 1, 2)
V
0.8
2.48
Unit
Max.
2.0
0.8
V
V
2.2
0.1
IO=24 mA
II
Max.
2.0
0.8
IO=-24 mA
VOL
-40 to 85°C
0.1
0.44
0.44
0.55
0.55
V
3.6
VI = VCC or GND
± 0.1
±1
±1
µA
3.6
VI = VCC or GND
4
40
40
µA
3.6
VOLD = 0.8 V max
36
25
mA
VOHD = 2 V min
-25
-25
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
Value
TA = 25°C
VCC
(V)
Min.
3.3
-0.8
3.3
Typ.
Max.
0.3
0.8
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
V
-0.3
2
V
CL = 50 pF
3.3
0.8
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
4/14
74LVQ161
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time CK to Q
tPLH tPHL Propagation Delay
Time CK to CARRY
OUT
tPLH tPHL Propagation Delay
Time TE to CARRY
OUT
tPHL
Propagation Delay
Time CLR to Q
tPHL
tW(L)
tW
ts
th
ts
th
ts
th
tREM
fMAX
tOSLH
tOSHL
Propagation Delay
Time CLR to
CARRY OUT
CLR Pulse Width,
LOW (LOAD)
CLOCK Pulse
Width, HIGH or
LOW
Setup Time HIGH
or LOW
(INPUT to CLOCK)
Hold Time HIGH or
LOW
(INPUT to CLOCK)
Setup Time HIGH
or LOW (LOAD to
CLOCK)
Hold Time HIGH or
LOW
(LOAD to
CLOCK)
Setup Time HIGH
or LOW (PE or TE
to CLOCK)
Hold Time HIGH or
LOW
(PE or TE
to CLOCK)
Recovery Time
CLR to CK
Maximum Clock
Frequency
Output To Output
Skew Time
(note1, 2)
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Max.
2.7
8.0
13.0
15.0
17.0
3.3(*)
2.7
6.8
9.5
11.0
12.5
9.1
14.0
16.0
18.5
3.3(*)
7.5
10.5
12.0
14.0
2.7
5.6
10.0
11.5
13.0
3.3(*)
4.7
8.0
9.5
10.5
2.7
8.0
12.0
15.0
17.0
3.3(*)
2.7
6.1
9.5
11.0
12.5
8.0
14.0
16.0
18.5
3.3(*)
6.7
10.5
12.0
14.0
2.7
4.0
1.9
4.0
4.0
3.3(*)
2.7
3.0
1.9
3.0
3.0
4.0
1.9
4.0
4.0
3.3(*)
3.0
1.9
3.0
3.0
2.7
5.0
2.5
5.0
5.0
3.3(*)
4.0
2.1
4.0
4.0
2.7
1
-1.3
1
1
3.3(*)
0.5
-1.0
0.5
0.5
2.7
3.0
1.5
3.0
3.0
2.5
1.2
2.5
2.5
1
-0.6
1
1
0.5
-0.5
0.5
0.5
2.7
7.0
3.4
7.0
7.0
3.3(*)
6.0
3.0
6.0
6.0
2.7
0
-2.6
0
0
0
-2.2
0
0
2.7
1
-0.8
1
1
3.3(*)
0.5
-0.6
0.5
0.5
2.7
100
150
80
60
3.3(*)
120
180
100
80
(*)
3.3
2.7
(*)
3.3
(*)
3.3
2.7
(*)
3.3
0.5
0.5
1.0
1.0
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
1.0
1.0
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
5/14
74LVQ161
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
TA = 25°C
VCC
(V)
CIN
Input Capacitance
3.3
CPD
Power Dissipation
Capacitance
(note 1)
3.3
Value
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4
pF
16
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
Figure 5: Test Circuit
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 6: Waveform - Propagation Delays, Count Mode (f=1MHz; 50% duty cycle)
6/14
74LVQ161
Figure 7: Waveform - Propagation Delays Clear Mode (f=1MHz; 50% duty cycle)
Figure 8: Waveform - Propagation Delays Preset Mode (f=1MHz; 50% duty cycle)
7/14
74LVQ161
Figure 9: Waveform - Propagation Delays Countable Mode (f=1MHz; 50% duty cycle)
Figure 10: Waveform - Propagation Delays Cascade Mode (f=1MHz; 50% duty cycle)
8/14
74LVQ161
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.25
a2
MAX.
0.004
0.010
1.64
0.063
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
e3
0.050
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
0016020D
9/14
74LVQ161
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.60
0.0256 BSC
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
10/14
74LVQ161
Tape & Reel SO-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
22.4
0.519
0.882
Ao
6.45
6.65
0.254
0.262
Bo
10.3
10.5
0.406
0.414
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
11/14
74LVQ161
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
12/14
TYP
0.504
22.4
0.519
0.882
Ao
6.7
6.9
0.264
0.272
Bo
5.3
5.5
0.209
0.217
Ko
1.6
1.8
0.063
0.071
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
74LVQ161
Table 10: Revision History
Date
Revision
29-Jul-2004
2
Description of Changes
Ordering Codes Revision - pag. 1.
13/14
74LVQ161
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