L6230
DMOS driver for three-phase brushless DC motor
Features
■
Operating supply voltage from 8 to 52 V
■
2.8 A output peak current (1.4 A RMS)
■
RDS(on) 0.73 Ω typ. value @ TJ = 25 °C
■
Integrated fast free wheeling diodes
■
Operating frequency up to 100 kHz
■
Non dissipative overcurrent detection and
protection
■
Cross conduction protection
■
Diagnostic output
■
Uncommitted comparator
Description
■
Thermal shutdown
■
Under voltage lockout
The L6230 is a DMOS fully integrated threephase motor driver with overcurrent protection,
optimized for FOC application thanks to the
independent current senses.
Application
■
BLDC motor driving
■
Sinusoidal / 6-steps driving
■
Field oriented control driving system
PowerSO36
VFQFPN32
Realized in BCDmultipower technology, the
device combines isolated DMOS Power
Transistors with CMOS and bipolar circuits on the
same chip.
An uncommitted comparator with open-drain
output is available.
Available in PowerSO36 and VFQFPN-32 5x5
packages the L6230 features a non dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.
Table 1.
Device summary
Order codes
Package
L6230PD
Packaging
Tube
PowerSO36
L6230PDTR
Tape and reel
L6230Q
Tube
VFQFPN32
L6230QTR
June 2011
Tape and reel
Doc ID 18094 Rev 2
1/24
www.st.com
24
Contents
L6230
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 16
6.3
Six-step driving method with BEMF zero crossing detection . . . . . . . . . . 17
6.4
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
Doc ID 18094 Rev 2
L6230
1
Block diagram
Block diagram
Figure 1.
Block diagram
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Doc ID 18094 Rev 2
3/24
Electrical data
L6230
2
Electrical data
2.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Symbol
VS
VOD
VBOOT
VIN, VEN
VCP-, VCP+
Parameter
Parameter
Unit
Supply voltage
VSA = VSB = VS
60
V
Differential voltage between: VSA,
OUT1, OUT2, SENSEA and VSB,
OUT3, SENSEB
VSA = VSB = VS = 60 V;
VSENSEx = GND
60
V
Bootstrap peak voltage
VSA = VSB = VS
VS + 10
V
Logic inputs voltage range
-0.3 to +7
V
Voltage range at CP- and CP+ pins
-0.3 to +7
V
-1 to +4
V
VSENSE
Voltage range at SENSEx pins
IS(peak)
Pulsed supply current (for each VS
pin)
VSA = VSB = VS;
TPULSE < 1 ms
3.55
A
RMS supply current (for each VS
pin)
VSA = VSB = VS
1.4
A
-40 to 150
°C
IS
Tstg, TOP
Storage and operating temperature
range
2.2
Recommended operating conditions
Table 3.
Recommended operating conditions
Symbol
VS
VOD
VCP-, VCP+
Parameter
Parameter
Supply voltage
Min
Max
Unit
8
52
V
52
V
-0.1
5
V
0
3
V
pulsed tW < trr
-6
6
V
DC
-1
1
V
1.4
A
+125
°C
100
kHz
VSA = VSB = VS
VSA = VSB = VS;
Differential voltage between VSA,
OUT1A, OUT2A, SENSEA and VSB, VSENSE1 = VSENSE2 =
OUT1B, OUT2B, SENSEB
VSENSE3
Voltage range at CP- and CP+ pins
VCPCM
Common mode voltage at the
comparator inputs
VSENSE
Voltage range at pins SENSEx
IOUT
4/24
Value
RMS output current
TJ
Operating junction temperature
fsw
Switching frequency
Doc ID 18094 Rev 2
-25
L6230
2.3
Electrical data
Thermal data
Table 4.
Thermal data
Value
Symbol
Parameter
Unit
PowerSO36
QFN32
Rth(j-amb)1 Maximum thermal resistance junction-ambient (1)
36
-
°C/W
Rth(j-amb)1 Maximum thermal resistance junction-ambient
(2)
16
-
°C/W
Rth(j-amb)2 Maximum thermal resistance junction-ambient
(3)
63
-
°C/W
42
°C/W
Rth(j-amb)3 Maximum thermal resistance junction-ambient (4)
2
1. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a
thickness of 35 µm).
2. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a
thickness of 35 µm), 16 via holes and a ground layer.
3. Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board.
4. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
Doc ID 18094 Rev 2
5/24
Pin connection
3
L6230
Pin connection
Figure 2.
Pin connection PowerSO36 (top view)
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Figure 3.
6&1&0.
Note:
6/24
The pins 2 to 8 are connected to die PAD.
The die PAD must be connected to GND pin.
Doc ID 18094 Rev 2
L6230
Pin connection
Table 5.
Pin
VBOOT
VCP
Pin description
Type
Function
Power supply Bootstrap voltage needed for driving the upper power MOSFETs.
Output
Charge pump oscillator output.
DIAG-EN
Logic
output/input
Double function: chip Enable as input and Overcurrent/Over-temperature
indication as output.
LOW logic level switches OFF all Power MOSFETs, putting the power
stages in high impedance status.
An internal open drain transistor pulls to GND the pin when an overcurrent
on one of the High Side MOSFETs is detected or during Thermal
Protection.
IN1
Logic input
Logic input half bridge 1.
EN1
Logic input
Enable input half bridge 1.
IN2
Logic input
Logic input half bridge 2.
EN2
Logic input
Enable input half bridge 2.
IN3
Logic input
Logic input half bridge 3.
EN3
Logic input
Enable input half bridge 3.
CP-
Analog input Inverting input of internal comparator.
CP+
Analog input Non-Inverting input of internal comparator.
CPOUT
Output
Half bridge 3 source pin. This pin must be connected to power ground
through a sensing power resistor.
SENSE3
OUT3
VSB
Power output Output half bridge 3.
Power supply
Power output Output half bridge 2.
Half bridge 1 source pin. This pin must be connected to power ground
through a sensing power resistor.
SENSE1
OUT1
Half bridge 3 power supply voltage. it must be connected to the supply
voltage together with pin VSA.
Half bridge 2 source pin. This pin must be connected to power ground
through a sensing power resistor.
SENSE2
OUT2
Open-drain output of internal comparator.
Power output Output half bridge 1.
VSA
Power supply
GND
Ground
Half bridge 1 and half bridge 2 power supply voltage. It must be connected
to the supply voltage together with pin VSB.
Ground terminal.
Doc ID 18094 Rev 2
7/24
Electrical characteristics
4
L6230
Electrical characteristics
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Table 6.
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VSth(ON)
Turn-on threshold
5.8
6.3
6.8
V
VSth(OFF)
Turn-off threshold
5
5.5
6
V
5
10
mA
IS
Tj(OFF)
All bridges OFF;
TJ = -25 °C to 125 °C(1)
Quiescent supply current
Thermal shutdown temperature
°C
165
Output DMOS transistors
RDS(on)
IDSS
TJ = 25 °C
High-side / low-side switch ON
resistance
TJ =125 °C
(1)
0.73
0.85
Ω
1.18
1.35
Ω
2
mA
DIAG-EN = LOW; OUT = VS
Leakage current
DIAG-EN = LOW; OUT = GND
-0.3
mA
Source drain diodes
VSD
Forward ON voltage
ISD = 1.4 A, DIAG-EN = LOW
1.15
1.3
V
trr
Reverse recovery time
If = 1.4 A
300
ns
tfr
Forward recovery time
200
ns
Logic inputs (INx, ENx, DIAG-EN)
VIL
Low level logic input voltage
VIH
High level logic input voltage
IIL
Low level logic input current
GND logic input voltage
IIH
High level logic input current
7 V logic input voltage
0.8
V
2
V
-10
µA
10
µA
800
ns
1000
ns
Switching characteristics
tD(ON)EN
Enable to output turn-on delay
time (2)
500
tD(OFF)EN
Enable to output turn-off delay time (2)
500
tD(ON)IN
tD(OFF)IN
tRISE
tFALL
tDT
fCP
8/24
Other logic inputs to OUT turn-ON delay
time
ILOAD = 1.4 A, resistive load
Other logic inputs to OUT turn-OFF
delay time
Output rise time (2)
Output fall time
(2)
Dead time
Charge pump frequency
TJ = -25 °C to 125 °C
Doc ID 18094 Rev 2
1.6
µs
800
ns
40
250
ns
40
250
ns
0.5
(1)
650
1
0.6
µs
1
MHz
L6230
Table 6.
Electrical characteristics
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
+14
mV
Comparator
Offset voltage
VCP- = 0.5 V
tprop
Propagation delay
(3)
IBIAS
Inputs bias current
VOFFSET
RCPOUT
-14
500
ns
10
µA
40
60
Ω
2.8
3.55
A
IDIAG = 4 mA
40
60
Ω
IDIAG = 4 mA; CDIAG < 100 pF
200
ns
IDIAG = 4 mA; CDIAG < 100 pF
100
ns
Open drain ON resistance
Over current detection and protection
ISOVER
Supply overcurrent protection threshold TJ = -25 to 125 °C (1)
RDIAG
Open drain ON resistance
(4)
tOCD(ON)
OCD turn-ON delay time
tOCD(OFF)
OCD turn-OFF delay time (4)
2
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 4.
3. Measured applying a voltage of 1 V to pin CP+ and a voltage drop from 2 V to 0 V to pin CP-.
4. See Figure 5.
Figure 4.
Switching characteristic definition
DIAG-EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tRISE
tFALL
tD(OFF)EN
Doc ID 18094 Rev 2
tD(ON)EN
9/24
Electrical characteristics
Figure 5.
L6230
Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VDIAG-EN
90%
10%
tOCD(ON)
10/24
Doc ID 18094 Rev 2
tOCD(OFF)
D02IN1387
L6230
Circuit description
5
Circuit description
5.1
Power stages and charge pump
The L6230 integrates a three-phase bridge, which consists of 6 power MOSFETs connected
as shown on the block diagram (see Figure 1), each power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross
conduction protection is implemented by using a dead time (tDT = 1 µs typical value) set by
internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of
a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 6. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Table 7.
Table 7.
Figure 6.
Charge pump external component values
Component
Value
CBOOT
220 nF
CP
10 nF
D1
1N4148
D2
1N4148
Charge pump circuit
VS
D1
CBOOT
D2
CP
VCP
VBOOT
VSA VSB
Doc ID 18094 Rev 2
11/24
Circuit description
5.2
L6230
Logic inputs
Pins INx and ENx are TTL/CMOS and microcontroller compatible logic inputs. The internal
structure is shown in Figure 7. Typical value for turn-on and turn-off thresholds are
respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin DIAG-EN has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 8 or Figure 9. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 8. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN
are connected as shown in Figure 9. The resistor REN should be chosen in the range from
2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and 5.6 nF.
More information on selecting the values is found in the overcurrent protection section.
Figure 7.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
Figure 8.
Pin DIAG-EN open collector driving
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
DIAG-EN
CEN
ESD
PROTECTION
D01IN1330
Figure 9.
Pin DIAG-EN push-pull driving
5V
PUSH-PULL
OUTPUT
REN
DIAG-EN
CEN
ESD
PROTECTION
D01IN1331
12/24
Doc ID 18094 Rev 2
L6230
5.3
Circuit description
Non-dissipative overcurrent detection and protection
The L6230 integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides output-to-output and output-to-ground short circuit protection as well. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 10 shows a simplified schematic for the
overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF. When the
output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG-EN can be used to signal the fault condition to a μC and to shut down the
three-phase bridge simply by connecting the pin to an external R-C (see REN, CEN).
Figure 10. Overcurrent protection simplified schematic
OUT1
VSA
HIGH SIDE DMOS
μC or LOGIC
VDD
REN
VSB
HIGH SIDE DMOS
I2
POWER DMOS
n cells
POWER DMOS
n cells
I3
POWER SENSE
1 cell
POWER DMOS
n cells
POWER SENSE
1 cell
+
OCD
COMPARATOR
DIAG\EN
OUT3
HIGH SIDE DMOS
I1
POWER SENSE
1 cell
TO GATE
LOGIC
OUT2
I1 / n
I2/ n
I1+I2 / n
CEN
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
IREF
OVER TEMPERATURE
I3/ n
IREF
D02IN1381
Figure 11 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 12. The delay time tDELAY before turning off the bridge when
an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 13
CEN is also used for providing immunity to pin DIAG\EN against fast transient noises.
Therefore the value of CEN should be chosen as big as possible according to the maximum
tolerable delay time and the REN value should be chosen according to the desired disable
time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs
disable time.
Doc ID 18094 Rev 2
13/24
Circuit description
L6230
Figure 11. Overcurrent protection waveforms
IOUT
ISOVER
DIAG-EN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tEN(RISE)
tD(ON)EN
tD(OFF)EN
D02IN1383
Figure 12. tDISABLE versus CEN and REN
R EN = 220 kΩ
3
1 .1 0
R EN = 100 kΩ
R EN = 47 kΩ
R EN = 33 kΩ
tDISABLE [µs]
R EN = 10 kΩ
100
10
1
1
10
100
C E N [n F ]
Figure 13. tDELAY versus CEN
tdelay [μs]
10
1
0.1
14/24
1
10
Cen [nF]
Doc ID 18094 Rev 2
100
L6230
6
Application information
Application information
Some typical applications using L6230 are shown in this paragraph. A high quality ceramic
capacitor (C2) in the range of 100 nF to 200 nF should be placed between the power pins
VSA and VSB and ground near the L6230 to improve the high frequency filtering on the
power supply and reduce high frequency transients generated by the switching. The
capacitor (CEN) connected from the DIAG-EN input to ground sets the shut down time when
an over current is detected (see overcurrent protection). The current sensing inputs
(SENSEX) should be connected to the sensing resistors RSENSE with a trace length as short
as possible in the layout. The sense resistors should be non-inductive resistors to minimize
the dI/dt transients across the resistors. To increase noise immunity, unused logic pins are
best connected to 5 V (high logic level) or GND (low logic level) (see pin description). It is
recommended to keep power ground and signal ground separated on PCB.
Table 8.
Component values for typical application
Component
Value
C1
100 µF
C2
100 nF
CBOOT
220 nF
CEN
5.6 nF
CP
10 nF
D1
1N4148
D2
1N4148
REN
100 kΩ
The examples reported describe some typical application to drive a 3-phase BLDC motor
using L6230 device.
In the first example is shown a field oriented control (FOC) system, with this method it is
possible to provide smooth and precise motor control of BLDC motors.
A six-step driving method with current control is reported in the second example, the inputs
sequence is generated by external controller and the L6230 comparator is used to obtain
the information for the peak current control.
Finally, the third example shows how to implement a sensorless motor control system, the
information on rotor position is achieved by BEMF zero-crossing detection.
6.1
Field oriented control driving method
In this configuration (see Figure 14) three sensing resistors are required, one for each
channel. The sensing signals coming from the output power stage are conditioned by
external operational amplifiers which provide the proper feedback signals to the AtoD
converter and the system controller. According to the feedback signals the six input lines are
generated by the controller.
Note that some filtering and level shifting RC networks should be added between the sense
resistor and the correspondent op-amp input.
Doc ID 18094 Rev 2
15/24
Application information
L6230
The uncommitted internal comparator with open-drain output is available.
Figure 14. F.O.C. typical application
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6.2
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Six-step driving method with current control
In this configuration only one sense resistor are needed, the three OUT pins are connected
together to RSENSE (see Figure 15).
The non-inverting input comparator CP+ monitors the voltage drop across the external
sense resistor connected between the source of the three lower power MOS transistors and
ground.
As the current in the motor increases the voltage across the RSENSE increases
proportionally. When the voltage drop across the sense resistor becomes greater than the
reference voltage applied at inverting input CP- the comparator open-drain output is
switched on pulling down the CPOUT pin.
This signal could be managed by controller to generate the proper input sequence for sixstep driving method with current control and select what current decay method to
implement.
When the sense voltage decrease below the CP- voltage, the open-drain is switched off and
the voltage at CPOUT pin start to increase charging the capacitor C3.
The reference voltage at pin CP- will be set according to sense resistor value and the
desired regulated current (VCP- { RSENSE x ITARGET). A very simple way to obtain variable
voltage is to low-pass filter a PWM output of a controller.
16/24
Doc ID 18094 Rev 2
L6230
Application information
Figure 15. Six-step with current control typical application
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Six-step driving method with BEMF zero crossing detection
The BEMF zero crossing information can be used to evaluate the rotor position; in this way
no Hall effect sensors or encoder are needed.
In six-step driving mode one of the three phases is left in high impedance state.
Comparing the voltage of this phase with the center-tap voltage we can detect the BEMF
zero-crossing.
In shown example (see Figure 16), the OUT1 phase voltage is monitored by the CP+; the
center-tap voltage is obtained as combination of three phase voltages and monitored by the
CP- pin. Only when the OUT1 is in high impedance, the CPOUT will perform a commutation
each time a BEMF zero crossing is detected.
In this configuration one sense resistor is needed, the three OUT pins are connected
together to RSENSE.
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Application information
L6230
Figure 16. Six-step with zero crossing detection typical application
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Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.
For instance, using a VFQFPN32L 5 x 5 package the typical Rth(JA) is about 42 °C/W when
mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top
side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC).
Otherwise, using a PowerSO package with copper slug soldered on a 1.5 mm copper
thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35 µm), the Rth(jA)
is about 35°C/W.
Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced
down to 15°C/W.
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Doc ID 18094 Rev 2
L6230
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 9.
VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.80
0.85
0.95
b
0.18
0.25
0.30
b1
0.165
0.175
0.185
D
4.85
5.00
5.15
D2
3.00
3.10
3.20
D3
1.10
1.20
1.30
E
4.85
5.00
5.15
E2
4.20
4.30
4.40
E3
0.60
0.70
0.80
e
L
0.50
0.30
ddd
Note:
0.40
0.50
0.08
VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no
lead. Very thin profile: 0.80 < A < 1.00 mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
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Package mechanical data
L6230
Figure 17. Package dimensions
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Package mechanical data
Table 10.
PowerSO36 mechanical data
Min.
Typ.
A
a1
Max.
3.6
0.1
0.3
a2
3.3
a3
0
0.1
b
0.22
0.38
c
0.23
0.32
D (1)
15.8
16
D1
9.4
9.8
E
13.9
14.5
e
0.65
e3
11.05
E1 (1)
10.9
E2
11.1
2.9
E3
5.8
6.2
E4
2.9
3.2
G
0
0.1
H
15.5
15.9
h
1.1
L
0.8
N
10°(max.)
S
8 °(max.)
Doc ID 18094 Rev 2
1.1
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Package mechanical data
L6230
Figure 18. PowerSO36 mechanical drawings
1
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Doc ID 18094 Rev 2
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L6230
8
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
14-Oct-2010
1
First release
07-Jun-2011
2
Updated maturity status from preliminary data to final datasheet.
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L6230
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