L6728D Single-phase PWM controller with Power Good Features ■ Flexible power supply from 5 V to 12 V ■ Power conversion input as low as 1.5 V ■ 0.8 V internal reference ■ 0.8% output voltage accuracy ■ High-current integrated drivers ■ Power Good output ■ Sensorless and programmable OCP across low-side RDS(on) ■ OV / UV protection ■ VSEN disconnection protection ■ Oscillator internally fixed at 300 kHz ■ LSLess to manage pre-bias startup ■ Adjustable output voltage ■ Disable function ■ Internal soft-start ■ DFN10 package DFN10 Description L6728D is a single-phase step-down controller with integrated high-current drivers that provides complete control logic and protection to simplify the design of general DC-DC converters by using a compact DFN10 package. Device flexibility allows the management of conversions with power input (VIN) as low as 1.5 V, and device supply voltage ranging from 5 V to 12 V. The L6728D provides a simple control loop with voltage mode EA. The integrated 0.8 V reference allows output voltages regulation with ±0.8% accuracy over line and temperature variations. The oscillator is internally fixed to 300 kHz. Applications ■ Memory and termination supply ■ Subsystem power supply (MCH, IOCH, PCI, etc.) ■ CPU and DSP power supply ■ Distributed power supply ■ General DC-DC converters The L6728D provides programmable dual level overcurrent protection, as well as overvoltage and undervoltage protection. Current information is monitored across the low-side MOSFET RDS(on), eliminating the need for expensive and spaceconsuming sense resistors. A PGOOD output easily provides real-time information on output voltage status, through the VSEN dedicated output monitor. Table 1. Device summary Order codes Package L6728D Packaging Tube DFN10 L6728DTR February 2010 Tape and reel Doc ID 16498 Rev 1 1/33 www.st.com 33 Contents L6728D Contents 1 2 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 7 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 8 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low-side-less startup (LSLess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 Overcurrent threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Output voltage setting and protections . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11 2/33 10.1 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10.2 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.2 Output capacitor(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 16498 Rev 1 L6728D 12 Contents 20 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.1 13 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.1 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.2 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.3 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1.5 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 A demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.1 Board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.1 Power input (Vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.2 Output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.3 Signal input (Vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.4 Test points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1.5 Board characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 16498 Rev 1 3/33 Typical application circuit and block diagram L6728D 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical application circuit of the L6728D VIN = 1.5V to 12V VCC = 5V to 12V CDEC 6 RPG VCC 7 COMP / DIS CF CP ROS BOOT PGOOD L6728A 10 PGOOD UGATE PHASE 1 CBULK CHF 3 HS 2 Vout L L6728D RF 8 RFB FB VSEN LGATE / OC GND 9 COUT LS LOAD ROCSET 5 ROS 4 RFB L6728A Reference Schematic L6728D 1.2 Block diagram Block diagram of the L6728D VCC Figure 2. VSEN VOUT MONITOR PGOOD VOCTH OC CONTROL LOGIC & PROTECTIONS BOOT ADAPTIVE ANTI CROSS CONDUCTION CLOCK PWM 300 kHz OSCILLATOR HS UGATE PHASE VCC LS ERROR AMPLIFIER LGATE / OC GND + - L6728A L6728D FB IOCSET COMP / DIS 4/33 0.8V Doc ID 16498 Rev 1 L6728D 2 Pin description and connection diagram Pin description and connection diagram Figure 3. Pin connection (top view) L6728D 2.1 Pin descriptions Table 2. Pins description Pin n° Name 1 BOOT HS driver supply. Connect through a capacitor (100 nF) to the floating node (LS-Drain) pin and provide necessary bootstrap diode from VCC. 2 PHASE HS driver return path, current-reading and adaptive-dead-time monitor. Connect to the LS drain to sense RDS(on) drop to measure the output current. This pin is also used by the adaptive-dead-time control circuitry to monitor when HS MOSFET is OFF. 3 UGATE HS driver output. Connect directly to HS MOSFET gate. 4 Function LGATE: LS driver output. Connect directly to LS MOSFET gate. OC: Overcurrent threshold set. During a short period of time following VCC rising over the UVLO threshold, a 10 μA current is sourced from this pin. Connect to GND with an ROCSET resistor greater than 5 kΩ to LGATE / OC program the OC threshold. The resulting voltage at this pin is sampled and held internally as the OC set point. The maximum programmable OC threshold is 0.55 V. A voltage greater than 0.6 V activates an internal clamp and causes the OC threshold to be set at the maximum value. 5 GND All internal references, logic and drivers are connected to this pin. Connect to the PCB ground plane. 6 VCC Device and driver power supply. Operating range from 5 V to 12 V. Filter with at least 1 µF MLCC to GND. 7 COMP: Error amplifier output. Connect with an RF - CF // CP to FB to compensate the device COMP / DIS control loop. DIS: The device can be disabled by pushing this pin lower than 0.75 V (typ). By setting the pin free, the device is enabled again. 8 FB Error amplifier inverting input. Connect with a resistor RFB to the output regulated voltage. An output resistor divider may be used to regulate voltages higher than the reference. 9 VSEN Regulated voltage sense pin for OVP and UVP protection and PGOOD. Connect to the output regulated voltage, or to the output resistor divider if the regulated voltage is higher than the reference. 10 PGOOD Open drain output set free after SS has finished and pulled low when VSEN is outside the relative window. Pull up to a voltage equal or lower than VCC. If not used it can be left floating. Doc ID 16498 Rev 1 5/33 Thermal data 3 L6728D Thermal data Table 3. Symbol Parameter Value Unit Rth(JA) Thermal resistance junction-to-ambient (device soldered on 2s2p, 67 mm x 69 mm board) 45 °C/W Rth(JC) Thermal resistance junction-to-case 5 °C/W TMAX Maximum junction temperature 150 °C TSTG Storage temperature range -40 to 150 °C TJ Junction temperature range -40 to 125 °C 2.25 W PTOT 6/33 Thermal data Maximum power dissipation at TA = 25 °C Doc ID 16498 Rev 1 L6728D Electrical specifications 4 Electrical specifications 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Value Unit -0.3 to 15 V VBOOT, VUGATE to PHASE to GND to GND; t < 200 ns 15 33 45 V VPHASE to GND to GND; t < 200 ns -5 to 18 -8 to 30 V VLGATE to GND -0.3 to VCC+0.3 V -0.3 to 3.6 V -0.3 to VCC+0.3 V VCC Parameter to GND FB, COMP, VSEN to GND PGOOD to GND 4.2 Electrical characteristics VCC = 5 V to 12 V; TJ = 0 to 70 °C unless otherwise specified Table 5. Symbol Electrical characteristics Parameter Test conditions Min. Typ. Max. Unit Supply current and power-ON ICC IBOOT VCC supply current UGATE and LGATE = OPEN BOOT supply current UGATE = OPEN; PHASE to GND VCC Turn-ON VCC rising 6 mA 0.7 mA 4.1 V UVLO Hysteresis 0.2 V Oscillator FSW Main oscillator accuracy ΔVOSC PWM ramp amplitude dMAX Maximum duty cycle 270 300 330 1.4 kHz V 80 % Reference and error amplifier Output voltage accuracy A0 GBWP DC gain -0.8 (1) Gain-bandwidth product (1) (1) SR Slew-rate DIS Disable threshold COMP falling Doc ID 16498 Rev 1 0.70 - 0.8 % 120 dB 15 MHz 8 V/μs 0.85 V 7/33 Electrical specifications Table 5. Symbol L6728D Electrical characteristics (continued) Parameter Test conditions Min. Typ. Max. Unit Gate drivers IUGATE HS source current BOOT - PHASE = 5 V 1.5 A RUGATE HS sink resistance BOOT - PHASE = 5 V 1.1 Ω ILGATE LS source current VCC = 5 V 1.5 A RLGATE LS sink resistance VCC = 5 V 0.65 Ω Overcurrent protection IOCSET OCSET current source Sourced from LGATE pin, during OC setting phase. VOC_SW OC switch-over threshold VLGATE/OC rising 9 10 11 600 μA mV Over and undervoltage protections OVP UVP VSEN VSEN rising 0.970 1.000 1.030 V un-latch, VSEN falling 0.35 0.40 0.45 V UVP threshold VSEN falling 0.570 0.600 0.630 V VSEN bias current Sourced from VSEN Upper threshold VSEN rising 0.860 0.890 0.920 V Lower threshold VSEN falling 0.680 0.710 0.740 V PGOOD voltage low IPGOOD = -4 mA 0.4 V OVP threshold 100 nA PGOOD PGOOD VPGOODL 1. Guaranteed by design, not subject to test. 8/33 Doc ID 16498 Rev 1 L6728D 5 Device description Device description The L6728D is a single-phase PWM controller with embedded high-current drivers which provides complete control logic and protection features for easy implementation of a general DC-DC step-down converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, this 10-pin device provides a high level of integration to allow a reduction in cost and size of power supply solutions, while also providing real-time PGOOD in a compact DFN10 3x3 mm package. The L6728D is designed to operate from a 5 V or 12 V supply. The output voltage can be precisely regulated to as low as 0.8 V with ±0.8% accuracy over line and temperature variations. The switching frequency is internally set to 300 kHz. This device provides a simple control loop with a voltage-mode error amplifier. The error amplifier features a 15 MHz gain-bandwidth product and 8 V/µs slew rate, allowing high regulator bandwidth for fast transient response. To prevent load damage, the L6728D provides protection against overcurrent, overvoltage, undervoltage and feedback disconnection. The overcurrent trip threshold is programmable using a resistor connected from Lgate to GND. Output current is monitored across the lowside MOSFET RDS(on), eliminating the need for expensive and space-consuming sense resistors. Output voltage is monitored through the dedicated VSEN pin. The L6728D implements soft-start by increasing the internal reference in closed-loop regulation. The low side-less feature allows the device to perform soft-start over a prebiased output, avoiding high current return through the output inductor and dangerous negative spike at the load side. The L6728D is available in a compact DFN10 3x3 mm package with exposed pad. Doc ID 16498 Rev 1 9/33 Driver section 6 L6728D Driver section The integrated high-current drivers permit the use of different types of power MOSFETs (also multiple MOSFETs to reduce the equivalent RDS(on)), maintaining fast switching transition. The driver for the high-side MOSFET uses the BOOT pin for supply and the PHASE pin for return. The driver for low-side MOSFET uses the VCC pin for supply and the GND pin for return. The controller embodies an anti-shoot-through and adaptive dead-time control to minimize low side body diode conduction time, maintaining good efficiency while eliminating the need for a Schottky diode: ● to check the high-side MOSFET turn-off, the PHASE pin is sensed. When the voltage at the PHASE pin drops, the low-side MOSFET gate drive is suddenly applied ● to check the low-side MOSFET turn-off, the LGATE pin is sensed. When the voltage at LGATE has fallen, the high-side MOSFET gate drive is suddenly applied If the current flowing in the inductor is negative, voltage on the PHASE pin will never drop. To allow the low-side MOSFET to turn on even in this case, a watchdog controller is enabled. If the source of the high-side MOSFET does not drop, the low side MOSFET is switched on, thereby allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. Power conversion input is flexible: 5 V, 12 V bus or any bus that allows the conversion (see maximum duty cycle limitations) to be chosen freely. 6.1 Power dissipation The L6728D embeds high current MOSFET drivers for both high side and low side MOSFETs. It is therefore important to consider the power that the device is going to dissipate in driving them, in order to avoid overcoming the maximum junction operating temperature. Two main factors contribute to device power dissipation: bias power and driver power. ● Device bias power (PDC) depends on the static consumption of the device through the supply pins, and is quantifiable as follows (assuming HS and LS drivers with the same VCC of the device): P DC = V CC ⋅ ( I CC + I BOOT ) ● Driver power is the power needed by the driver to continuously switch on and off the external MOSFETs. It is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power PSW dissipated to switch the MOSFETs (easily calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last factor is the most important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs is: P SW = F SW ⋅ ( Q gHS ⋅ V BOOT + Q gLS ⋅ V CC ) 10/33 Doc ID 16498 Rev 1 L6728D Driver section External gate resistors help the device to dissipate the switching power since the same power PSW is shared between the internal driver impedance and the external resistor, resulting in a general cooling of the device. Doc ID 16498 Rev 1 11/33 Soft-start 7 L6728D Soft-start The L6728D implements a soft-start to smoothly charge the output filter, avoiding the high in-rush currents to be required from the input power supply. The device gradually increases the internal reference from 0 V to 0.8 V in 4.5 ms (typ.), in closed-loop regulation, linearly charging the output capacitors to the final regulation voltage. In the event of overcurrent triggering during soft-start, the overcurrent logic overrides the soft-start sequence and shuts down the PWM logic and both the high side and low side gates. This condition is latched. Cycle the VCC to recover. The device begins the soft-start phase only when the VCC power supply is above the UVLO threshold and the overcurrent threshold setting phase has been completed. 7.1 Low-side-less startup (LSLess) In order to avoid any kind of negative undershoot and dangerous return from the load during startup, the L6728D performs a special sequence in enabling the LS driver to switch: during the soft-start phase, the LS driver is disabled (LS = OFF) until the HS starts to switch. This prevents the dangerous negative spike on the output voltage which can happen if starting over a pre-biased output. If the output voltage is pre-biased to a voltage higher than the final one, the HS would never start to switch. In this case, at the end of soft-start time, LS is enabled and discharges the output to the final regulation value. This particular feature of the device masks the LS turn-on only from the control loop point of view: protection features bypass this turning on of the LS MOSFET if needed. Figure 4. 12/33 LSLess startup (left) vs. non-LSLess startup (right) Doc ID 16498 Rev 1 L6728D 8 Overcurrent protection Overcurrent protection The overcurrent function protects the converter from a shorted output or overload, by sensing the output current information across the low side MOSFET drain-source onresistance, RDS(on). This method reduces cost and enhances converter efficiency by avoiding the use of expensive and space-consuming sense resistors. The low side RDS(on) current sense is implemented by comparing the voltage at the PHASE node when the LS MOSFET is turned on with the programmed OCP threshold voltages, internally held. If the monitored voltage is higher than these thresholds, an overcurrent event is detected. For maximum safety and load protection, the L6728D implements a dual-level overcurrent protection system: ● 1st level threshold: This is the user externally-set threshold. If the monitored voltage on PHASE exceeds this threshold, a 1st level overcurrent is detected. If four 1st level OC events are detected in four consecutive switching cycles, overcurrent protection is triggered. ● 2nd level threshold: This is an internal threshold whose value is equal to the 1st level threshold multiplied by a factor 1.5. If the monitored voltage on PHASE exceeds this threshold, overcurrent protection is triggered immediately. When overcurrent protection is triggered, the device turns off both the LS and HS MOSFETs in a latched condition. To recover from an overcurrent protection-triggered condition, the VCC power supply must be cycled. Doc ID 16498 Rev 1 13/33 Overcurrent protection 8.1 L6728D Overcurrent threshold setting The L6728D allows easy programming of a 1st level overcurrent threshold ranging from 50 mV to 550 mV, simply by adding a resistor (ROCSET) between LGATE and GND. The 2nd level threshold is automatically set accordingly. During a short period of time (about 5 ms) following VCC rising over UVLO threshold, an internal 10 µA current (IOCSET) is sourced from the LGATE pin, determining a voltage drop across ROCSET. This voltage drop is sampled and internally held by the device as a 1st level overcurrent threshold. The OC setting procedure’s overall time period is about 5 ms. Connecting an ROCSET resistor between LGATE and GND, the programmed 1st level threshold is: I OCSET ⋅ R OCSET I OCth1 = ------------------------------------------R dsON the programmed 2nd level threshold is: I OCSET ⋅ R OCSET I OCth2 = 1.5 ⋅ -------------------------------------------R dsON ROCSET values range from 5 kΩ to 55 kΩ. In case ROCSET is not connected, the device sets the OCP thresholds to the maximum values: an internal safety clamp on LGATE is triggered as soon as the LGATE voltage reaches 600 mV, setting the maximum threshold and suddenly ending the OC setting phase. 14/33 Doc ID 16498 Rev 1 L6728D 9 Output voltage setting and protections Output voltage setting and protections The L6728D is capable of precisely regulating an output voltage as low as 0.8 V. In fact, the device is equipped with a fixed 0.8 V internal reference that guarantees the output regulated voltage remains within a ±0.8% tolerance over line and temperature variations (excluding output resistor divider tolerance, when present). Output voltages higher than 0.8 V can be easily achieved by adding a resistor ROS between the FB pin and ground. Referring to Figure 1, the steady-state DC output voltage is: R FB ⎞ V OUT = V REF ⋅ ⎛ 1 + ---------⎝ R ⎠ OS where VREF is 0.8 V. The L6728D monitors the voltage at the VSEN pin and compares it to the internal reference voltage in order to provide undervoltage and overvoltage protection as well as a PGOOD signal. Depending on the level of VSEN, different actions are performed by the controller: ● PGOOD: If the voltage monitored through VSEN goes outside the PGOOD window limits, the device de-asserts the PGOOD signal while still continuing to switch and regulate. PGOOD is asserted at the end of the soft-start phase. ● Undervoltage protection: If the voltage at VSEN pin drops below the UV threshold, the device turns off both the HS and LS MOSFETs, latching the condition. Cycle the VCC to recover. ● Overvoltage protection: If the voltage at VSEN pin rises over OV threshold (1 V typ), overvoltage protection turns off the HS MOSFET and turns on the LS MOSFET. The LS MOSFET is turned off as soon as VSEN goes below Vref/2 (0.4 V). The condition is latched. Cycle the VCC to recover. Note that even if the device is latched, the device still controls the LS MOSFET and can switch it on whenever VSEN rises above the OV threshold. ● Feedback disconnection protection: In order to provide load protection even if the VSEN pin is not connected, a 100 nA bias current is always sourced from this pin. If VSEN pin is not connected, this current permanently pulls it up, causing the device to detect an OV. Thus, LS is latched on, preventing the output voltage from rising out of control. Doc ID 16498 Rev 1 15/33 Application details L6728D 10 Application details 10.1 Compensation network The control loop shown in Figure 5 is a voltage mode control loop. The output voltage is regulated to the internal reference (when present, the offset resistor between the FB node and GND can be neglected in control loop calculation). The error amplifier output is compared to the oscillator sawtooth waveform to provide the PWM signal to the driver section. The PWM signal is then transferred to the switching node with VIN amplitude. This waveform is filtered by the output filter. The converter transfer function is the small signal transfer function between the output of the EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT resonance and a zero at FESR depending on the output capacitor ESR. The DC gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage ΔVOSC. Figure 5. PWM control loop VIN OSC ΔV OSC _ L + R V OUT COUT PWM COMPARATOR ERROR AMPLIFIER + CF ESR VREF _ RFB RF CS RS ZFB CP ZF The compensation network closes the loop, joining the VOUT and EA output with transfer function ideally equal to -ZF/ZFB. The compensation goal is to close the control loop while assuring high DC regulation accuracy, good dynamic performance and stability. To achieve this, the overall loop needs high DC gain, high bandwidth and good phase margin. High DC gain is achieved by giving an integrator shape to the compensation network transfer function. The loop bandwidth (F0dB) can be fixed by choosing the correct RF/RFB ratio. However, for stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain must cross the 0 dB axis with -20 dB/decade slope. As an example, Figure 6 shows an asymptotic bode plot of a type III compensation. 16/33 Doc ID 16498 Rev 1 L6728D Application details Figure 6. Example of type III compensation Gain [dB] open loop EA gain FZ1 FZ2 FP2 FP1 closed loop gain compensation gain 20log (RF/RFB) open loop converter gain 20log (VIN/ΔVOSC ) 0dB F0dB FLC ● ● Log (Freq) FESR Open loop converter singularities: a) 1 F LC = --------------------------------2π L ⋅ C OUT b) 1 F ESR = ------------------------------------------2π ⋅ C OUT ⋅ ESR Compensation network singularities frequencies: a) 1 F Z1 = -----------------------------2π ⋅ R F ⋅ C F b) 1 F Z2 = ----------------------------------------------------2π ⋅ ( R FB + R S ) ⋅ C S c) 1 F P1 = -------------------------------------------------CF ⋅ CP 2π ⋅ R F ⋅ ⎛⎝ ---------------------⎞⎠ CF + CP d) 1 F P2 = -----------------------------2π ⋅ R S ⋅ C S To place the poles and zeroes of the compensation network, the following suggestions can be followed: a) Set the gain RF/RFB in order to obtain the desired closed loop regulator bandwidth according to the approximated formula (suggested values for RFB are in the range of a few kΩ): F 0dB ΔV OSC RF = ------------ ⋅ ---------------------------F LC V IN R FB Doc ID 16498 Rev 1 17/33 Application details b) L6728D Place FZ1 below FLC (typically 0.5*FLC): 1 C F = ----------------------------π ⋅ R F ⋅ F LC c) Place FP1 at FESR: CF C P = ---------------------------------------------------------2π ⋅ R F ⋅ C F ⋅ F ESR – 1 d) Place FZ2 at FLC and FP2 at half of the switching frequency: R FB R S = -------------------------F SW ------------------ – 1 2 ⋅ F LC 1 C S = -----------------------------π ⋅ R S ⋅ F SW 10.2 e) Check that the compensation network gain is lower than open loop EA gain before F0dB f) Check the phase margin obtained (it should be greater than 45°) and repeat if necessary. Layout guidelines The L6728D provides control functions and high current integrated drivers to implement high-current step-down DC-DC converters. In this type of application, a good layout is very important. The first priority when placing components for these applications must be reserved for the power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) power connections (highlighted in Figure 7) must be a part of a power plane and in any case constructed with wide and thick copper traces. The loop must be minimized. The critical components, i.e. the power MOSFETs, must be close to each other. The use of multi-layer printed circuit boards is recommended. The input capacitance (CIN), or at least a portion of the total capacitance needed, must be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred. MLCC are suggested to be connected near the HS drain. Use the appropriate number of VIAs when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer reduces the parasitic resistance associated with that connection. Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic inductance and resistance associated with the copper trace, and also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. 18/33 Doc ID 16498 Rev 1 L6728D Application details Figure 7. Power connections (heavy lines) VIN CIN UGATE PHASE L L6728A L6728D COUT LGATE LOAD GND Gate traces and phase traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows the management of applications with the power section far from the controller without compromising performance. In any case, when possible it is recommended to minimize the distance between the controller and power section. Small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. Locate bypass capacitor (VCC and bootstrap capacitor) and feedback compensation components as close to the device as practical. For overcurrent programmability, place ROCSET close to the device and avoid leakage current paths on the LGATE / OC pin, since internal current source is only 10 µA. Systems that do not use a Schottky diode in parallel to the low-side MOSFET might show big negative spikes on the phase pin. This spike must be limited within the absolute maximum ratings (for example, adding a gate resistor in series to the HS MOSFET gate), as well as the positive spike, but has an additional consequence: it causes the bootstrap capacitor to be over-charged. This extra charge can cause, in the worst-case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the absolute maximum ratings, also causing device failures. It is then suggested in this cases to limit this extra charge by adding a small resistor in series to the bootstrap diode. Figure 8. Driver turn-on and turn-off paths LS DRIVER LS MOSFET HS DRIVER VCC HS MOSFET BOOT CGD RGATE CGD RINT RGATE LGATE RINT UGATE CGS CDS GND CGS CDS PHASE Doc ID 16498 Rev 1 19/33 Application information L6728D 11 Application information 11.1 Inductor design The inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (ΔIL) between 20% and 30% of the maximum output current (typ). The inductance value can be calculated with the following equation: V IN – V OUT V OUT L = ------------------------------ ⋅ -------------F SW ⋅ ΔI L V IN Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 9 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5 V and VIN = 12 V. Increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from initial to final value. Until the inductor has finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. If the compensation network is well-designed, during a load variation the device is able to set a duty cycle value very different (0% or 80%) from a steady-state one. When this condition is reached, the response time is limited by the time required to change the inductor current. Figure 9. 20/33 Inductor current ripple vs output voltage Doc ID 16498 Rev 1 L6728D 11.2 Application information Output capacitor(s) The output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During steady-state conditions, the output voltage ripple is influenced by both the ESR and capacitive value of the output capacitors as follow: ΔV OUT_ESR = ΔI L ⋅ ESR 1 ΔV OUT_C = ΔI L ⋅ --------------------------------------8 ⋅ C OUT ⋅ F SW Where ΔIL is the inductor current ripple. In particular, the expression that defines ΔVOUT_C takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. During a load variation, the output capacitor supplies the current to the load or absorbs the current stored into the inductor until the converter reacts. In fact, even if the controller immediately recognizes the load transient and sets the duty cycle at 80% or 0%, the current slope is limited by the inductor value. The output voltage has a drop that, in this case also, depends on the ESR and capacitive charge/discharge as follows: ΔV OUT_ESR = ΔI OUT ⋅ ESR L ⋅ ΔI OUT ΔV OUT_C = ΔI OUT ⋅ -------------------------------------2 ⋅ C OUT ⋅ ΔV L Where ΔVL is the voltage applied to the inductor during the transient response ( D MAX ⋅ VIN – VOUT for the load appliance or VOUT for the load removal). MLCC capacitors have typically low ESR to minimize the ripple but also have low capacitances that do not minimize the voltage deviation during dynamic load variations. On the contrary, electrolytic capacitors have big capacitances to minimize voltage deviation during load transients, while they do not show the same ESR values of the MLCC resulting then in higher ripple voltages. For these reasons, a mix between electrolytic and MLCC capacitor is suggested to minimize ripple and reduce voltage deviation in dynamic mode. 11.3 Input capacitors The input capacitor bank is designed considering mainly the input RMS current, which depends on the output deliverable current (IOUT) and the duty cycle (D) for regulation as follows: I rms = I OUT ⋅ D ⋅ ( 1 – D ) The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depend on the input capacitor’s ESR and, in the worst case, are: P = ESR ⋅ ( I OUT ⁄ 2 ) 2 Doc ID 16498 Rev 1 21/33 20 A demonstration board 12 L6728D 20 A demonstration board The L6728D demonstration board is constructed using a four-layer PCB, and is designed as a step-down DC-DC converter. The board demonstrates the operation of the device in a general-purpose application. The input voltage can range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The application can deliver an output current up to 30 A. The switching frequency is 300 kHz. Figure 10. 20 A demonstration board (left) and component placement (right) Figure 11. 20 A demonstration board top (left) and bottom (right) layers Figure 12. 20 A demonstration board inner layers 22/33 Doc ID 16498 Rev 1 L6728D 20 A demonstration board Figure 13. 20 A demonstration board schematic Doc ID 16498 Rev 1 23/33 20 A demonstration board Table 6. L6728D 20 A demonstration board - bill of material Qty Reference Description Package Capacitors 2 C1, C2 Electrolytic capacitor 1800 µF 16 V Nippon chemi-con KZJ or KZG 1 C10 MLCC, 100 nF, 16V, X7R SMD0603 3 C11 to C13 MLCC, 4.7 μF, 16V, X5R Murata GRM31CR61C475MA01 SMD1206 2 C14, C38 MLCC, 1 μF, 16V, X7R SMD0805 2 C15, C19 MLCC, 10 μF, 6.3 V, X7R Murata GRM31CR70J106KA01L SMD1206 2 C18, C20 Electrolytic capacitor 2200 μF 6.3 V Nippon chemi-con KZJ or KZG 1 C23 MLCC, 6.8 nF, X7R 1 C24 MLCC, 33 nF, X7R 1 C35 MLCC, 68 pF, X7R Radial 10 x 25 mm Radial 10 x 20 mm SMD0603 Resistors 4 R1, R2, R20, R17 Resistor, 3R3, 1/16W, 1% 4 R3, R5, R11, R16 Resistor, 0R, 1/8W, 1% 1 R4 Resistor, 1R8, 1/8W, 1% 2 R6, R9 Resistor, 2K2, 1/16W, 1% 2 R8, R13 Resistor, 3K9, 1/16W, 1% 1 R7 Resistor, 18K, 1/16W, 1% 1 R19 Resistor, 22K, 1/16W, 1% 1 R18 Resistor, 20K, 1/16W, 1% L1 Inductor, 1.25 μH, T60-18, 6 turns Easymagnet AP106019006P-1R1M SMD0603 SMD0805 SMD0603 Inductor 1 na Active components 1 D1 Diode, 1N4148 or BAT54 1 Q5 STD70N02L 1 Q7 STD95NH02LT4 1 U1 Controller, L6728D SOT23 DPACK 24/33 Doc ID 16498 Rev 1 DFN10, 3x3 mm L6728D 20 A demonstration board 12.1 Board description 12.1.1 Power input (Vin) This is the input voltage for the power conversion. The high-side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus. If the voltage is between 4.5 V and 12 V it can also supply the device (through the Vcc pin) and in this case the R16 (0 Ω) resistor must be present. 12.1.2 Output (Vout) The output voltage is fixed at 1.25 V but can be changed by replacing the resistors R8 (sense partition lower resistor) and R13 (feedback partition lower resistor). R18 allows adjustment of the OCP threshold. 12.1.3 Signal input (Vcc) When using the input voltage Vin to supply the controller, no power is required at this input. However the controller can be supplied separately from the power stage through the Vcc input (4.5-12 V) and, in this case, the R16 (0 Ω) resistor must be unsoldered. 12.1.4 Test points Several test points are provided for easy access to all the important signals that characterize the device: 12.1.5 – COMP: The output of the error amplifier – FB: The inverting input of the error amplifier – PGOOD: Signaling regular functioning (active high) – VGDHS: The bootstrap diode anode – PHASE: Phase node – LGATE: Low-side gate pin of the device – HGATE: High-side gate pin of the device Board characterization Figure 14. 20 A demonstration board efficiency Doc ID 16498 Rev 1 25/33 5 A demonstration board 13 L6728D 5 A demonstration board The L6728D demonstration board is constructed using a two-layer PCB, and is designed as a step-down DC-DC converter. The board demonstrates the operation of the device in a general-purpose, low-current application. The input voltage can range from 5 V to 12 V buses and the output voltage is fixed at 1.25 V. The application can deliver an output current in excess of 5 A. The switching frequency is 300 kHz. Figure 15. 5 A demonstration board (left) and component placement (right) Figure 16. 5 A demonstration board top (left) and bottom (right) layers 26/33 Doc ID 16498 Rev 1 GND Doc ID 16498 Rev 1 ᤡ 0 5 GND LGATE UGATE ᤢ 1uF 220pF 68nF 4.7k C35 C24 R13 3.9k R9 0 R8 3.9k R14 VSEN 15 2.2k 6.8nF C36 R1 Vsen VCC 3.3 LGATE LGATE 2.2k R6 R17 3.3 3.3 R5 PHASE R3 C10 100nF BOOT 0 0 HSG1 4 3 Q5a 5 /6 HSD VIN_POWER LSG1 2 1 0 Q5b 7 /8 0 L2 2.2uH C23 6.8nF R4 1.8 2 1 0 ᤡ C12 10uF ᤡ 0 22uF C39 OUT NC ᤢ 0 C51 10uF ᤢ 330uF 0 NC C40 ᤢ C30 NC OUT C29 0 ᤡ ᤢ C18 OUT 0 OUT ᤡ V U R W L F D S D F F L P D U H F R7 FB U H O O N UR U RW Q ZR WF H 1 H QK W R U LD W DH VQ Q HH SF PD O RS & COMP 7 VCC_PIN FB COMP 8 6 VSEN 9 10 R19 22k R2 PHASE PIN PHASE UGATE BAT54 W Q L U S W R R I O D X G 0 C14 VCC COMP FB VSEN PGOOD L6728D L6728 PGOOD 0 VCC_PIN C38 1uF D1 V U R W L F D S D F P X O D W Q D 7 R18 10k 4 3 PHASE BOOT GND VCC R16 0 U R W L F D S D F F L W \ O R U W F H O ( LGATE UGATE 2 1 U1 GNDIN1 / / + 1 ' 6 7 6 W H I V R 0 O D X ' PHASE PIN BOOT 0 GNDCC VCC VCC VIN1 GND 0 GNDIN_POWER VIN_POWER V U R W L F D S D F F L P D U H F W Q L U S W R R I O D X G COMP W Q L U S W R R I O D X G OUT V R P 6 + U D H Q H F D O S FB VOUT 0 GNDOUT1 GNDOUT VOUT1 L6728D 5 A demonstration board Figure 17. 5 A demonstration board schematic 27/33 5 A demonstration board Table 7. L6728D 5 A demonstration board - bill of material Qty Reference Description Package Capacitors 2 C12, C51 MLCC, 10 μF, 25 V, X5R Murata GRM31CR61E106KA12 SMD1206 1 C10 MLCC, 100 nF, 16 V, X7R SMD0603 2 C14, C38 MLCC, 1 μF, 16 V, X7R SMD0805 1 C39 MLCC, 22 μF, 6.3 V, X5R Murata GRM31CR60J226ME19L SMD1206 1 C30 330 μF, 6.3 V, 9 mΩ Sanyo 6TPF330M9L SMD7343 2 C23, C36 MLCC, 6.8 nF, X7R 1 C24 MLCC, 68 nF, X7R 1 C35 MLCC, 220 pF, X7R 3 R1, R2, R17 Resistor, 3R3, 1/16 W, 1% SMD0603 3 R3, R5, R16 Resistor, 0R, 1/16 W, 1% SMD0603 1 R4 Resistor, 1R8, 1/8 W, 1% SMD0805 1 R14 Resistor, 15R, 1/16 W, 1% SMD0603 2 R6, R9 Resistor, 2K2, 1/16 W, 1% 2 R8, R13 Resistor, 3K9, 1/16 W, 1% 1 R7 Resistor, 4K7, 1/16 W, 1% 1 R19 Resistor, 22K, 1/16 W, 1% 1 R18 Resistor, 10K, 1/16 W, 1% L1 Inductor, 2.2 μH, WURTH 744324220LF SMD0603 Resistors SMD0603 Inductor 1 na Active components 28/33 1 D1 Diode, BAT54 1 Q5 STS9D8NH3LL 1 U1 Controller, L6728D Doc ID 16498 Rev 1 SOT23 SO8 DFN10, 3x3 mm L6728D 5 A demonstration board 13.1 Board description 13.1.1 Power input (Vin) This is the input voltage for the power conversion. The high-side drain is connected to this input. This voltage can range from 1.5 V to 12 V bus. If the voltage is between 4.5 V and 12 V, it can also supply the device (through the Vcc pin), and in this case the R16 (0 Ω) resistor must be present. 13.1.2 Output (Vout) The output voltage is fixed at 1.25 V, but can be changed by replacing resistors R8 (sense partition lower resistor) and R13 (feedback partition lower resistor). R18 allows the adjustment of the OCP threshold. 13.1.3 Signal input (Vcc) When using the input voltage Vin to supply the controller, no power is required at this input. However, the controller can be supplied separately from the power stage through the Vcc input (4.5-12 V) and, in this case, the R16 (0 Ω) resistor must be unsoldered. 13.1.4 Test points Several test points are provided for easy access to all the important signals that characterize the device: – COMP: The output of the error amplifier – FB: The inverting input of the error amplifier – PGOOD: Signaling regular functioning (active high) – VGDHS: The bootstrap diode anode – PHASE: Phase node – LGATE: Low-side gate pin of the device – HGATE: High-side gate pin of the device Doc ID 16498 Rev 1 29/33 5 A demonstration board 13.1.5 L6728D Board characterization Figure 18. 5 A demonstration board efficiency 30/33 Doc ID 16498 Rev 1 L6728D Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 8. DFN10 mechanical data mm mils Dim. Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 31.5 35.4 39.4 A1 0.02 0.05 0.8 2.0 A2 0.70 27.6 A3 0.20 7.9 A b 0.18 D D2 2.21 7.1 9.1 2.26 1.49 1.64 2.31 87.0 89.0 0.4 90.9 118.1 1.74 58.7 64.6 0.50 0.3 11.8 118.1 3.00 e L 0.30 3.00 E E2 0.23 68.5 19.7 0.5 11.8 15.7 M 0.75 29.5 m 0.25 9.8 19.7 Doc ID 16498 Rev 1 M Figure 19. Package dimensions m 14 Package mechanical data 31/33 Revision history 15 L6728D Revision history Table 9. 32/33 Document revision history Date Revision 03-Feb-2010 1 Changes Initial release. Doc ID 16498 Rev 1 L6728D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 16498 Rev 1 33/33