RT8204C Single Synchronous Buck with LDO Controller General Description Features The RT8204C PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. z A built-in LDO controller can drive an external N-MOSFET to provide a second output voltage from PWM output or other power source. The RT8204C can provide adjustable voltage down to 0.75V and maximum output voltage is depended on the selected MOSFET. The internal 0.75V reference voltage with ±1.5% accuracy provides tight regulation for the output voltage. The independent enable control, open drain power good indicator, under voltage protection and soft start make RT8204C to power the system friendly. The RT8204C is available in WQFN-16L 3x3 package. Applications z z z Notebook Computers CPU Core Supply Chipset/RAM Supply as Low as 0.75V Ultra-High Efficiency ` Resistor Programmable Current Limit by Low Side RDS(ON) Sense (Lossless Limit) or Sense Resistor (High Accuracy) ` Quick Load Step Response within 100ns ` 1% VOUT Accuracy Over Line and Load ` Adjustable 0.75V to 3.3V Output Voltage Range ` 4.5V to 26V Battery Input Range ` Resistor Programmable Frequency ` Over/Under Voltage Protection ` 2 Steps Current Limit During Soft-Start ` Drives Large Synchronous-Rectifier FETs ` Power-Good Indicator LDO Controller ` 1.5% Accuracy Over Line and Load ` Adjustabe Output Voltage down to 0.75V ` 1ms Soft Start ` Independent Enable and Power Good Indicator ` Drive N-MOSFETs within Rail to Rail Controller Voltage ` MLCC and POSCAP Stable RoHS Compliant and Halogen Free ` The constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The RT8204C achieves high efficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs. The buck conversion allows this device to directly step down high voltage batteries for the highest possible efficiency. The RT8204C is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as 0.75V. PWM Controller z z Ordering Information RT8204C Package Type QW : WQFN-16L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS8204C-03 April 2011 www.richtek.com 1 RT8204C Pin Configurations TON EN/DEM LEN BOOT (TOP VIEW) 16 15 14 13 VOUT VDD FB PGOOD 1 12 2 11 PHASE OC 9 VDDP GND 3 10 17 4 6 7 8 LPGOOD LFB LDRV LGATE 5 UGATE WQFN-16L 3x3 Typical Application Circuit VDDP 5V D1 BAT254 VIN 4.5V to 26V C1 4.7µF R2 100k R4 1M R1 10 RT8204C 16 BOOT 13 TON 9 VDDP UGATE 12 2 C2 1µF VDD 4 PGOOD PGOOD 15 CCM/DEM 14 LDO Enable 5 LDO PGOOD EN/DEM R5 2.2 R6 0 Q2 AO4704 R7 10k VOUT1 1.2V Q1 AO4704 L1 2.4µH C9 220µF R8 C5 FB 3 R9 12k C6 C13 0.1µF R10 20k LEN LPGOOD VOUT 1 R3 100k LDRV 7 VDDP Exposed Pad (17) C3 0.1µF PHASE 11 LGATE 8 OC 10 C4 10µF GND C7 33nF LFB 6 C12 Q3 AO4404 R11 C8 R12 12k C10 220µF C11 10µF VOUT2 1.05V R13 30k www.richtek.com 2 DS8204C-03 April 2011 RT8204C Functional Pin Description Pin No. Pin Name Pin Function 1 VOUT VOUT Sense Input. Connect to the output of PWM converter. VOUT is an input of the PWM controller. 2 VDD Analog Supply Voltage Input for the internal analog integrated circuit. Bypass to GND with a 1μF ceramic capacitor. 3 FB 4 PGOOD 5 LPGOOD Power Good signal Open Drain Output of LDO Regulator. This pin will be pulled high when the output voltage is within the target range. 6 LFB LDO Feedback Input. Connect LFB to a resistor voltage divider from VOUT to GND to adjust the output greater than 0.75V. 7 LDRV 8 LGATE 9 VDDP 10 OC 11 PHASE Inductor Connection. This pin is not only the zero current sense input for the PWM converter, but also the UGATE high side gate driver return. 12 UGATE High Side N-MOSFET Floating Gate-Driver Output for the PWM converter. This pin swings between PHASE and BOOT. 13 BOOT Bootstrap Input for High Side Gate Driver. Connect an external ceramic capacitor to PHASE and an external diode to VDDP. 14 LEN LDO Enable Input with internal pull low resistor. LDO is enabled if LEN is greater than the on level and disabled if LEN is less than the off level. 15 EN/DEM 16 TON 17 (Exposed Pad) GND DS8204C-03 April 2011 VOUT Feedback Input. Connect FB to a resistor voltage divider from VOUT to GND to adjust the output voltage from 0.75V to 3.3V. Power Good Signal Open Drain Output of PWM Converter. This pin will be pulled high when the output voltage is within the target range. Drive Signal for the LDO’s path MOSFET. Low side N-MOSFET Gate-Drive Output for PWM. This pin swings between GND and VDDP. VDDP is the gate driver supply for the external MOSFETs. Bypass to GND with a 1μF ceramic capacitor. PWM Current Limit Setting and sense. Connect a resistor between OC to PHASE for current limit setting. PWM Enable and Operation Mode Selection Input. Connect to VDD for diode-emulation mode, connect to GND for shutdown mode and floating the pin for CCM mode. VIN Sense Input. Connect to VIN through a resistor. TON is an input of the PWM controller. Analog Ground and Power Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. www.richtek.com 3 RT8204C Function Block Diagram PWM Controller TRIG On-time Compute 1-SHOT VOUT TON SS (Internal) - + GM + - - R Comp S + BOOT Q DRV UGATE PHASE Min. TOFF Q TRIG 0.75V VREF OV + 115% VREF DRV - FB - 70% VREF UV + Latch S1 Q SS Timer LGATE PGND Diode Emulation - 90% VREF VDD VDDP 1-SHOT Latch S1 Q + 20µA Thermal Shutdown + OC - GND PGOOD EN/DEM LDO Controller SS LEN 0.75V VREF SS ramp LFB + - X1 LDRV LPGOOD - 90% VREF + - 50% VREF www.richtek.com 4 + DS8204C-03 April 2011 RT8204C Absolute Maximum Ratings z z z z z z z z z z z z z z z z (Note 1) Input Voltage, TON to GND ---------------------------------------------------------------------------------------------BOOT to GND -------------------------------------------------------------------------------------------------------------PHASE to GND DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------UGATE to PHASE DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------LGATE to GND DC ----------------------------------------------------------------------------------------------------------------------------<20ns -----------------------------------------------------------------------------------------------------------------------PHASE to BOOT ---------------------------------------------------------------------------------------------------------VDD, VDDP, VOUT, EN/DEM, LEN, LFB, FB, PGOOD, LPGOOD, LDRV to GND ----------------------UGATE to PHASE -------------------------------------------------------------------------------------------------------OC to GND -----------------------------------------------------------------------------------------------------------------LGATE to GND ------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA ------------------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z z −0.3V to 32V −0.3V to 38V −0.3V to 32V −8V −0.3V to 6V −5V −0.3V to 6V −2.5V −6V to 0.3V −0.3V to 6V −0.3V to 6V −0.3V to 28V −0.3V to 6V 1.471W 68°C/W 7.5C/W 260°C 150°C −65°C to 150°C 2kV 200V (Note 4) Input Voltage, VIN ---------------------------------------------------------------------------------------------------------Supply Voltage, VDD, VDDP ---------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------------- 4.5V to 26V 4.5V to 5.5V −40°C to 125°C −40°C to 85°C Electrical Characteristics (VDD = VDDP = 5V, VIN = 15V, VOUT = 1.25V, EN/DEM = VDD, RTON = 1MΩ, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- -- 1250 μA -- 15 -- μA PWM Controller Quiescent Supply Current TON Operating Current VDD + VDDP FB = 0.8V, forced above the regulation point RTON = 1MΩ To be continued DS8204C-03 April 2011 www.richtek.com 5 RT8204C Parameter Shutdown Current Symbol ISHDN Test Conditions Min Typ Max VDD + VDDP -- 1 10 TON -- 1 -- −10 −1 -- 0.742 0.75 0.758 V −1 0.1 1 μA 0.75 -- 3.3 V 267 334 401 ns 250 400 550 ns EN/DEM = 0V FB Reference Voltage VFB FB Input Bias Current VDD = 4.5 to 5.5V FB = 0.75V Output Voltage Range VIN = 15V, VOUT = 1.25V, RTON = 1MΩ On-Time Unit μA Minimum Off-Time V OUT Shutdown Discharge Resistance Current Sensing EN/DEM = GND -- 20 -- Ω ILIM Source Current LGATE = High 18 20 22 μA Current Comparator Offset GND to OC −10 -- 10 mV Zero Crossing Threshold GND to PHASE, EN/DEM = 5V −10 -- 5 mV GND to PHASE, RILIM = 2.5kΩ 35 50 65 mV GND to PHASE, RILIM = 10kΩ 170 200 230 mV 60 70 80 % 10 15 20 % -- 20 -- μs 4.1 4.3 4.5 V -- 1.35 -- ms -- 3.1 -- ms -- 155 -- °C -- 10 -- °C BOOT to PHASE forced to 5V -- 1.5 5 Ω R UGATEsk BOOT to PHASE forced to 5V -- 1.5 5 Ω Fault Protection Current Limit Sense Voltage Output Under Voltage Threshold Over Voltage Protection Threshold Over Voltage Fault Delay VDD UVLO Threshold Soft-Start Ramp Time Under Voltage Blank Time V RILIM With respect to error comparator threshold FB forced above OV threshold Rising edge, Hysteresis = 20mV, PWM disabled below this level From EN high to internal VREF reach 0.71V (0Æ95%) From EN signal going high Thermal Shutdown Thermal Shutdown Hysteresis Driver On-Resistance UGATE Driver Pull Up UGATE Driver Sink LGATE Driver Pull Up LGATE, High State (Source) -- 1.5 5 Ω LGATE Driver Pull Down UGATE Driver Source/Sink Current LGATE Driver Source Current LGATE Driver Sink Current LGATE, Low State (Sink) UGATE forced to 2.5V, BOOT to PHASE forced to 5V -- 0.6 2.5 Ω -- 1 -- A LGATE forced to 2.5V -- 1 -- A LGATE forced to 2.5V -- 3 -- A LGATE Rising (PHASE = 1.5V) -- 30 -- UGATE Rising -- 30 -- Dead Time ns To be continued www.richtek.com 6 DS8204C-03 April 2011 RT8204C Parameter Symbol Test Conditions Min Typ Max Unit EN/DEM Low -- -- 0.8 V EN/DEM High 2.9 -- -- EN/DEM Float -- 2 -- −13 −10 −7 % -- 2.5 -- μs -- -- 0.4 V High state, forced to 5V -- -- 1 μA PWM off, LDO on, IOUT = 0mA -- -- 400 μA Logic I/O Logic Input Low Voltage Logic Input High Voltage PGOOD (upper side threshold decide by OV threshold) Measured at FB with respect to Trip Threshold (Falling) reference, no load. Hysteresis = 3% Falling edge, FB forced below Fault Propagation Delay PGOOD trip threshold Output Low Voltage ISINK = 1mA Leakage Current V LDO Controller Quiescent Current IQ Shut-down Current ISHDN Input Voltage UVLO -- -- 5 μA 4.1 -- 4.5 V LEN Logic High Voltage VLEN_H 2 -- -- V LEN Logic Low Voltage VLEN_L -- -- 0.8 V LEN Input Current ILEN -- -- 10 μA LFB Reference Voltage VLFB 0.739 0.75 0.761 V LFB Input Current ILFB −1 -- +1 μA 90% Settling -- 1 -- ms ILDRV_sr VLFB = 0.72V 1.4 2 -- ILDRV_sk VLFB = 0.78V 1.4 2 -- Measured at LFB pin 40 50 60 % -- 2.5 -- μs 87 90 93 % -- 2.5 -- μs -- -- 0.4 V -- -- 1 μA -- 155 -- °C -- 10 -- °C Soft Start Rising Time LDRV Sourcing Output Sinking Current Output Under Voltage Protection Threshold Under Voltage Protection Propagation Delay PGOOD Threshold (Falling) LEN = 5V (Internal pull low) Measured at LFB pin PGOOD Low Voltage Falling edge, FB forced below PGOOD trip threshold ISINK = 1mA PGOOD Leakage Current High state, forced to 5V PGOOD Propagation Delay Thermal Shutdown Thermal Shutdown Hysteresis mA Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the WQFN package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8204C-03 April 2011 www.richtek.com 7 RT8204C Typical Operating Characteristics VOUT1 Efficiency vs. Load Current 90 275 Switching Frequency (kHz) 300 80 Efficiency (%) Switching Frequency vs. Output Current 100 DEM 70 60 PWM 50 40 30 20 10 0.01 0.1 1 PWM 225 200 175 150 DEM 125 100 75 50 25 VIN = 8V 0 0.001 250 0 0.001 10 VIN = 8V 0.01 VOUT1 Efficiency vs. Load Current 90 275 Efficiency (%) Switching Frequency (kHz) 300 DEM PWM 60 50 40 30 20 10 0.01 0.1 1 250 225 PWM 200 175 150 DEM 125 100 75 50 25 VIN = 12V 0 0.001 0 0.001 10 VIN = 12V 0.01 90 275 Efficiency (%) Switching Frequency (kHz) 300 70 PWM 60 50 40 30 20 10 0 0.001 VIN = 24V 0.01 0.1 Load Current (A) www.richtek.com 8 1 10 Switching Frequency vs. Output Current VOUT1 Efficiency vs. Load Current 100 DEM 0.1 Output Current (A) Load Current (A) 80 10 Switching Frequency vs. Output Current 100 70 1 Output Current (A) Load Current (A) 80 0.1 1 10 250 225 200 PWM 175 150 DEM 125 100 75 50 25 0 0.001 VIN = 24V 0.01 0.1 1 10 Output Current (A) DS8204C-03 April 2011 RT8204C Standby Current vs. Input Voltage LDO Output Voltage vs. Output Current 400 1.0540 390 380 Standby Current (uA) Output Voltage (V) 1.0535 1.0530 1.0525 1.0520 1.0515 1.0510 370 360 350 340 330 320 310 300 1.0505 290 VIN = 1.25V 1.0500 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 7 5 9 11 13 15 17 19 Output Current (A) Input Voltage (V) Shutdown Current vs. Input Voltage Power On from EN 3.0 Shutdown Current (uA) EN = 5V, No Load 280 21 23 25 PWM-Mode 2.5 VOUT (1V/Div) 2.0 PHASE (10V/Div) 1.5 EN/DEM (2V/Div) 1.0 0.5 EN = GND, No Load PGOOD (5V/Div) 0.0 7 9 11 13 15 17 19 21 23 25 VIN = 12V, EN = Floating, No Load Time (800μs/Div) Input Voltage (V) Power On from EN Power Off from EN DEM-Mode VOUT (1V/Div) VOUT (1V/Div) EN/DEM (2V/Div) PHASE (10V/Div) UGATE (20V/Div) EN/DEM (5V/Div) PGOOD (5V/Div) VIN = 12V, EN = 5V, No Load Time (800μs/Div) DS8204C-03 April 2011 LGATE (5V/Div) VIN = 12V, EN = Floating, No Load Time (4ms/Div) www.richtek.com 9 RT8204C VOUT1 Load Transient Response OVP VOUT_ac (50mV/Div) I LOAD (5A/Div) VOUT (1V/Div) UGATE (20V/Div) UGATE (10V/Div) LGATE (5V/Div) VIN = 12V, EN = Floating, IOUT1 = 0A to 6A LGATE (5V/Div) VIN = 12V, EN = 5V, No Load Time (10μs/Div) Time (40μs/Div) UVP Power On in Short Condition VIN = 12V, EN = Floating, VOUT1 Short VOUT (1V/Div) VOUT (1V/Div) Inductor Current (10A/Div) I LOAD (10A/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) VIN = 12V, EN = Floating, No Load Time (20μs/Div) Time (800μs/Div) LDO Load Transient Response LDO Short-Circuit Protection VIN = 1.25V, COUT = 10μF x 2, IOUT2 = 0.1A to 4A VOUT (1V/Div) VOUT_ac-coupled (100mV/Div) LDRI (5V/Div) LDRI (2V/Div) I LOAD (20A/Div) I LOAD (5A/Div) LPGOOD (5V/Div) Time (100μs/Div) www.richtek.com 10 VIN = 1.25V, COUT = 10μF x 2, VOUT2 Short Time (100μs/Div) DS8204C-03 April 2011 RT8204C Application Information The RT8204C PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low-voltage CPU core, I/O, and chipset RAM supplies in notebook computers. Richtek's Mach ResponseTM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load-transient timing problems of fixed-frequency current mode PWMs while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constantoff-time PWM schemes. The DRV TM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. PWM Operation The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. Refer to the function diagrams of the RT8204C, the synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.). On-Time Control (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it into a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to output voltage and inversely proportional to input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. TON = 3.85p x RTON x VOUT / (VIN − 0.5) And then the switching frequency is : Frequency = VOUT / (VIN x TON) RTON is a resistor connected from the input supply (VIN) to the TON pin. Mode Selection (EN/DEM) Operation The EN/DEM pin enables the supply. When EN/DEM is tied to VDD, the controller is enabled and operates in diode-emulation mode. When the EN/DEM pin is floating, the RT8204C will operate in forced-CCM mode. Diode-Emulation Mode (EN/DEM = High) In diode-emulation mode, the RT8204C automatically reduces switching frequency at light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly without increasing the VOUT ripple or load regulation. As the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low-side MOSFET allows only partial of negative current when the inductor freewheeling current reach negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level than requires the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light load operation can be calculated as follows (Figure 1) : ILOAD ≈ IL (VIN − VOUT ) × TON 2L Slope = (V IN -V OUT) / L iL, peak iLoad = iL, peak / 2 0 tON t Figure 1. Boundary Condition of CCM/DEM DS8204C-03 April 2011 www.richtek.com 11 RT8204C The switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light load efficiency. Trade-off in DEM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degrades load-transient response (especially at low input-voltage levels). Current sensing of the RT8204C can be accomplished in two ways. Users can either use a current sense resistor or the on-state of the low side MOSFET (RDS(ON)). For resistor sensing, a sense resistor is placed between the source of low side MOSFET and PGND (Figure 3(a)). RDS(ON) sensing is more efficient and less expensive (Figure 3(b)). There is a compromise between current limit accuracy and sense resistor power dissipation. PHASE LGATE R ILIM OC Forced-CCM Mode (EN/DEM = floating) The low noise, forced-CCM mode (EN/DEM = floating) disables the zero-crossing comparator, which controls the low-side switch on-time. This causes the low side gatedrive waveform to become the complement of the high side gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio VOUT/VIN. The benefit of forced-CCM mode is to keep the switching frequency fairly constant, but it comes at a cost: The no load battery current can be up to 10mA to 40mA, depending on the external MOSFETs. (a) PHASE LGATE OC R ILIM (b) Figure 3. Current Sense Methods ILoad In both cases, the RILIM resistor between the OC pin and PHASE pin sets the over current threshold. This resistor RILIM is connected to a 20μA current source within the RT8204C which is turned on when the low-side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will be activated. The highside MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. ILIM Choose a current limit resistor by following equation : Current Limit Setting (OCP) The RT8204C has cycle-by-cycle current limiting control. The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at OC is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure 2). IL IL, peak RILIM = ILIMIT x RSENSE / 20μA t 0 Figure 2. Valley Current-Limit www.richtek.com 12 Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signal seen by OC and PGND. Mount the IC close to the low side MOSFET and sense resistor with short, direct traces, making a Kelvin sense connection to the sense resistor. DS8204C-03 April 2011 RT8204C MOSFET Gate Driver (UGATE, LGATE) POR, UVLO and Soft-Start The high side driver is designed to drive high current, low RDS(ON) N-MOSFETs. When configured as a floating driver, 5V bias voltage is delivered from VDDP supply. The average drive current is proportional to the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins. Power On Reset (POR) occurs when VDD rises above to approximately 4.3V, the RT8204C will reset the fault latch and prepare the PWM for operation. If the VDD is below 4.1V(MIN), the VDD under voltage lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low RDS(ON) N-MOSFETs. The internal pull-down transistor that drives LGATE low is robust, with a 0.6Ω typical onresistance. A 5V bias voltage is delivered form VDDP supply. The instantaneous drive current is supplied by the flying capacitor between VDDP and PGND. For high current applications, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time (Figure 4). +5V BOOT Furthermore, the maximum allowed current limit is segment in 2 steps during 1.35ms period. Output Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage protection. When the output voltage exceeds 15% of the its setting voltage threshold, the over voltage protection will be triggered and the low side MOSFET will be latched on. This activates the low side MOSFET to discharge the output capacitor. The RT8204C is latched once OVP is triggered and can only be released by VDD or EN/DEM power on reset. There is a 20us delay built into the over voltage protection circuit to prevent false transitions. V IN R UGATE PHASE Figure 4. The UGATE Rise Time Reduction Power Good Output (PGOOD) The power good output is an open-drain output and requires a pull-up resistor. When the output voltage is 15% above or 10% below its set voltage, the PGOOD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. In soft start, the PGOOD is actively held low and is allowed to be pulled high until soft start is over and the output reaches 93% of its set voltage. There is a 2.5μs delay built into the PGOOD circuitry to prevent false transition. DS8204C-03 April 2011 A built-in soft-start is used to prevent the surge current from power supply input after EN/DEM is enabled. It clamps the ramping of internal reference voltage which is compared with the FB signal. The typical soft-start duration is 1.35ms. Output Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 70% of its set voltage threshold, the under voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. In order to remove the residual charge on the output capacitor during the under voltage period, if the PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is 2.5us delay built into the under voltage protection circuit to prevent false transitions. During the soft-start, the UVP will be blanked around 3.1ms. Output Voltage Setting (FB) The output voltage can be adjusted from 0.75V to 3.3V by setting the feedback resistor R1 and R2 (Figure 5). Choose R2 to be approximately 10kΩ, and solve for R1 using the equation : www.richtek.com 13 RT8204C ⎡ ⎤ VOUT = VFB × ⎢1 + ⎛⎜ R1 ⎞⎟ ⎥ ⎣ ⎝ R2 ⎠ ⎦ where VFB is 0.75V. Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mV at minimum VBAT, and worst case no smaller than 10mV. If Vripple at minimum VBAT is less than 15mV, the above component values should be revisited in order to improve this. Quite often a small capacitor, C1, is required in parallel with the top feedback resistor, R1, in order to ensure that VFB is large enough. The value of C1 can be calculated as follows, where R2 is the bottom feedback resistor. Firstly calculating the value of Z1 required : Z1 = If RTON ≥ 2MΩ then TON Where RTON is TON set resistor and the VOUT_FB is the output signal of resistor divider. Since the switching frequency is FS = ) RTON = RTON = VIN BOOT VOUT R1 C1 C2 R1 C2 R4 R2 GND Figure 6. Output Voltage Setting for VOUT > 3.3V Application Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : L= FB R3 V OUT_FB FB V IN VOUT V OUT PHASE VFB_VBAT(MIN) is the ripple voltage into FB pin in minimum VBAT. BOOT R TON UGATE fsw_VBAT(MIN) is the switching frequency in minimum VBAT; Z1 VOUT − 0.4 VOUT 1 × × VIN VOUT_FB FS × 3.55p V IN ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ R2 ×⎢ ⎥ V 1 ⎢ R2+ ⎥ 1 + 2×π × f ⎢ SW_VBAT(MIN) × C1 ⎥ R1 ⎣ ⎦ where Vripple_VBAT(MIN) is the output ripple voltage in minimum VBAT ; V OUT VOUT − 0.5 VOUT 1 × × VIN VOUT_FB FS × 3.85p If RTON ≥ 2MΩ then Finally using the equation as follows to verify the value of VFB : VFB_VBAT(MIN) = Vripple_VBAT(MIN) PHASE VOUT VIN × TON If RTON < 2MΩ then Secondly calculating the value of C1 required to achieve this : 1 − 1 Z1 R1 C1 = F 2 × π × fSW_VBAT(MIN) UGATE RTON × VOUT_FB VIN − 0.5 RTON × VOUT_FB = 3.55p × VIN − 0.4 If RTON < 2MΩ then TON = 3.85p × For a given switching frequency, we can obtain the RTON as below R2 × V ( ripple_VBAT(MIN) − 0.015 ) Ω 0.015 ( For application that output voltage is higher than 3.3V, user can also use a voltage divider to keep VOUT pin voltage within 0.75V to 2.8V as shown in Figure 6. For this case, TON can be determined as below : TON × (VIN - VOUT ) LIR × ILOAD(MAX) R2 GND Figure 5. Setting The Output Voltage www.richtek.com 14 DS8204C-03 April 2011 RT8204C Find a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough and not to saturate at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)] Output Capacitor Selection The output filter capacitor must have ESR low enough to meet output ripple and load transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : VP-P ESR ≤ ILOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an acceptable level of output voltage ripple : VP-P ESR ≤ LIR × ILOAD(MAX) Organic semiconductor capacitors or specially polymer capacitors are recommended. Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : f 1 fESR = ≤ SW 2 × π × ESR × COUT 4 Do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic and unstable operation. However, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VOUT or FB divider close to the inductor. DS8204C-03 April 2011 There are two related but distinct ways including doublepulsing and feedback loop instability to identify the unstable operation. Double-pulsing occurs due to noise on the output or because the ESR is too low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after 400ns minimum off-time period has expired. Doublepulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with AC probe. Do not allow more than one ringing cycle after the initial step-response under- or over-shoot. LDO Normal Operation The RT8204C LDO controls an N-MOSFET to produce a tightly regulated output voltage from higher supply voltage. It takes 5V power supply for controller and draws maximally 400uA while operating. The feedback voltage is regulated to compare with the internal 0.75V reference voltage. To set the output voltage, feedback the conjunction of a resistor voltage divider from output node to ground for the LFB pin. Depending upon the input voltage used for the device, the LDRV pin can be pulled up near to VDD. Thus the device can be used to regulate a large range of output voltage by careful selection of the external MOSFETs. A built-in active high enable control (LEN pin) is used to turn the RT8204C LDO on. If this pin is pulled low, the LDRV pin is pulled low, turning off the N-MOSFET. If this pin is pulled higher than 2V, the LDRV pin is enabled. www.richtek.com 15 RT8204C A built-in soft start is used to prevent the surge current from power supply input of the LDO. After LEN is enable, it clamps the ramp of the internal reference voltage which is compared with the LFB signal. The typical soft strat duration is 1ms. The RT8204C LDO contains a power good output pin (LPGOOD pin) which is an open drain output that will be pulled low if the output is below the power good threshold (typically 90% of the programmed output voltage, or 93% at the start up). The power good detection is active if the RT8204C LDO is enabled. The RT8204C LDO also includes a under voltage protection circuit that monitors the output voltage. If the output voltage drops below 50% (typical) of the nominal value, as would occur during over current or short condition, the RT8204C LDO will pull the LDRV pin low and latch off. The RT8204C LDO is latched once the UVP is triggered and can only be relieved by the VDD or LEN power-on reset. LDO Driver and Stability Design LDO Output Under Voltage Protection(UVP) The RT8204C LDO has output under voltage protection that looks at the output to see if it is : (a) The LDO output voltage is less than 50% (typical) of its nominal value and (b) The VDRV is within 900mV (typical) of its maximum. This provides inherent immunity to under voltage shut down at start up since VDRV has a slow rate of rising at this moment. If both of these criteria are met, the output will be shut down by means of the VDRV pulled to ground immediately. If the VDDP input is coming prior to the LDO_VIN, it could accidentally meet the UVP fault protection. To avoid entering UVP latch off, using enable control (LEN pin) to turn the system on whenever all power supplies are ready. Please see the power sequencing example as below (Figure 7). VDDP The drive output (LDRV pin) is sink/source capable. The sink current is typically 2mA while the source current is typically 2mA in normal operation. The drive output is also used for stabilizing the loop of the system using different type of the output capacitor. The components listed in the table below should be used. VTH(UV) = 0.88V LDO_VIN VTH(LEN) = 2V LEN VTH(LEN) occurs after VTH(UV) is reached RT8204C Supply Comes Up Before MOSFET Drain Supply Table 1. LDO Configuration and Compensation LDO Configuration Input Output Voltage Voltage 1.25V Compensator VDDP C7 C8 R11 1.05V 33nF 39pF 82Ω 1.5V 1.05V 33nF 47pF 43Ω 1.5V 1.25V 33nF 47pF 30Ω 1.8V 1.5V 33nF 39pF 100Ω Note: test condition is output capacitor 220μF(ESR : 9 to 25mΩ) or 100μF(ESR : 9 to 15mΩ) + MLCC 10uFoutput current is from 0.1A to 5A www.richtek.com 16 VTH(UV) = 0.88V LDO_VIN VTH(LEN) = 2V LEN VTH(LEN) occurs after VTH(UV) is reached LEN rising with VDDP shown MOSFET Drain Supply Comes Up Before RT8204 Supply Figure 7. Power Supply Sequencing DS8204C-03 April 2011 RT8204C LDO Output Voltage Setting The LFB pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistor R3 and R4 (Figure 8). The following equation is for adjusting the output voltage. ⎡ ⎤ VOUT = VLFB × ⎢1 + ⎛⎜ R3 ⎞⎟ ⎥ ⎣ ⎝ R4 ⎠ ⎦ Note that RDS(ON) must be met for operating temperature range at the minimum VGS condition. Power consumptions of the N-MOSFETs should be taken into consideration for the selection of various package types. Layout Considerations Layout is very important in high frequency switching converter design. If the Layout is designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. Certain points must be considered before starting a layout for the RT8204C. where VLFB is 0.75V (typ.). LDO_VIN LDRV ` Connect an RC low pass filter from VDDP to VDD, 1μF and 10Ω are recommended. Place the filter capacitor close to the IC. ` Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high voltage switching node. ` Connections from the drivers to the respective gate of the high side or the low LDO_VOUT R3 LFB R4 Figure 8. LDO Output Voltage Setting LDO Output Capacitor Selection Low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, and ceramic bypass capacitors are recommended for decoupling high frequency transients. LDO Input Capacitor Selection Low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for the input capacitors to provide better load transient response. If the LDO input is connected from the output of buck converter (VOUT1), a 0.1μF ceramic capacitor will sufficient. LDO MOSFET Selection Low-threshold N-MOSFETs are required. For the device to work under all operating conditions, a maximum RDS(ON) must be met to ensure that the output will not go into dropout : VIN(MIN) − VOUT(MAX) RDS(ON)(MAX) = Ω IOUT(PEAK) DS8204C-03 April 2011 www.richtek.com 17 RT8204C Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 18 DS8204C-03 April 2011