STK30N2LLH5 N-channel 25 V, 0.0024 Ω, 30 A, PolarPAK® STripFET™V Power MOSFET Preliminary Data Features Type VDSS RDS(on) max RDS(on)*Qg STK30N2LLH5 25 V < 0.0029 Ω 54 nC*mΩ ■ Ultra low top and bottom junction to case thermal resistance ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ Very low switching gate charge ■ Fully encapsulated die ■ 100% matte tin finish (in compliance with the 2002/95/EC european directive) ■ High avalanche ruggedness ■ PolarPAK® is a trademark of VISHAY PolarPAK® Figure 1. Internal schematic diagram Application ■ Switching applications Description This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Table 1. Bottom View Top View Device summary Order code Marking Package Packaging STK30N2LLH5 302L5 PolarPAK® Tape and reel July 2008 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/13 www.st.com 13 Contents STK30N2LLH5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 6 STK30N2LLH5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit 25 V ± 20 V VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ID (1) Drain current (continuous) at TC = 25 °C 30 A ID Drain current (continuous) at TC = 100 °C 18.75 A Drain current (pulsed) 120 A Total dissipation at TC = 25 °C 5.2 W 0.0416 W/°C IDM (2) PTOT (1) Derating factor EAS (3) Single pulse avalanche energy TBD J Tj Operating junction temperature Storage temperature -55 to 150 °C Tstg 1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10sec 2. Pulse width limited by package 3. Starting TJ = 25 °C, ID = 15 A, VDD = 25 V Table 3. Thermal data Symbol Parameter Rthj-amb(1) Thermal resistance junction-amb Rthj-c(2) Thermal resistance junction-case (top drain) Rthj-c(3) Thermal resistance junction-case (source) Typ. Max. Unit 20 24 °C/W 1 1.2 °C/W 2.8 3.4 °C/W 1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10sec 2. Steady state 3. Measured at source pin when the device is mounted on FR-4 board in steady state 3/13 Electrical characteristics 2 STK30N2LLH5 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol Parameter Test conditions Drain-source breakdown voltage ID = 250 µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating, IGSS Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 15 A V(BR)DSS Table 5. Symbol Ciss Coss Crss Qg Qgs Qgd Qgs1 Qgs2 RG 4/13 On/off states Min. Typ. Max. 25 V VDS = Max rating,Tc=125°C 1 1 10 µA µA ±100 nA 2.5 V 0.0024 0.0029 0.003 0.0036 VGS= 4.5 V, ID= 15 A Unit Ω Ω Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Test conditions VDS =25 V, f=1 MHz, VGS=0 Min. Typ. Max. Unit 2290 555 90 pF pF pF nC nC nC Total gate charge Gate-source charge Gate-drain charge VDD=15 V, ID = 30 A (see Figure 3) 18 TBD TBD Pre Vth gate-to-source charge Post Vth gate-to-source charge VDD=15 V, ID = 30 A TBD nC (see Figure 8) TBD nC f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain TBD Ω Gate input resistance VGS =4.5 V VGS =4.5 V STK30N2LLH5 Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr td(off) tf Table 7. Symbol Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 15 V, ID= 15 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) VDD=15 V, ID= 15 A, RG=4.7 Ω, VGS=4.5 V (see Figure 2) Parameter Test conditions ISDM(1) VSD(2) Forward on Voltage ISD= 30 A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 30 A, di/dt = 100 A/µs, VDD=20 V, Tj=150°C trr Qrr IRRM Typ. Max. Unit TBD TBD ns ns TBD TBD ns ns Source drain diode Source-drain current Source-drain current (pulsed) ISD Min. (see Figure 7) Min. Typ. TBD TBD TBD Max. Unit 30 120 A A 1.1 V ns nC A 1. Pulse width limited by package 2. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/13 Test circuits STK30N2LLH5 3 Test circuits Figure 2. Switching times test circuit for resistive load Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times Unclamped inductive load test circuit Figure 6. Unclamped inductive waveform Switching time waveform 6/13 Figure 3. Figure 7. Gate charge test circuit STK30N2LLH5 Figure 8. Test circuits Gate charge waveform Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd 7/13 Package mechanical data 4 STK30N2LLH5 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 8/13 STK30N2LLH5 Package mechanical data Table 8. PolarPAK® (option “S”) mechanical data mm inch Ref. A Min. Typ. Max. Min. Typ. Max. 0.75 0.80 0.85 0.030 0.031 0.033 A1 0.05 0.002 b1 0.48 0.58 0.68 0.019 0.023 0.027 b2 0.41 0.51 0.61 0.016 0.020 0.024 b3 2.19 2.29 2.39 0.086 0.090 0.094 b4 0.89 1.04 1.19 0.035 0.041 0.047 b5 0.23 0.33 0.43 0.009 0.013 0.017 c 0.20 0.25 0.30 0.008 0.010 0.012 D 6 6.15 6.30 0.236 0.242 0.248 D1 5.74 5.89 6.04 0.226 0.232 0.238 E 5.01 5.16 5.31 0.197 0.203 0.209 E1 4.75 4.90 5.05 0.187 0.193 0.199 H1 0.23 H2 0.45 H3 0.31 H4 0.45 I1 1.92 J1 0.009 0.56 0.018 0.51 0.012 0.56 0.018 1.97 2.02 0.075 0.077 0.079 0.38 0.43 0.48 0.014 0.016 0.018 K1 4.22 4.37 4.52 0.166 0.172 0.178 K4 0.24 M1 4.30 4.50 4.70 0.169 0.177 0.185 M2 3.43 3.58 3.73 0.135 0.141 0.147 M3 0.22 0.009 M4 0.05 0.002 P1 0.15 0.20 0.25 0.006 0.008 0.010 T1 3.48 3.64 4.10 0.137 0.143 0.161 T2 0.56 0.76 0.95 0.022 0.030 0.037 T3 1.20 0.047 T4 3.90 0.154 0.007 0.014 10° 12° T5 < 0° 0.41 0.022 0.016 0.020 0.022 0.009 0.18 0.36 10° 12° 0° 9/13 Package mechanical data Figure 9. 10/13 PolarPAK® (option “S”) drawings STK30N2LLH5 STK30N2LLH5 Package mechanical data Figure 10. Recommended PAD layout 11/13 Revision history 5 STK30N2LLH5 Revision history Table 9. 12/13 Document revision history Date Revision 07-Jul-2008 1 Changes First release STK30N2LLH5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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